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Commit 75a39138 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "msm: kgsl: Move gx_is_on() function to gmu_dev_ops"

parents f601d290 a8d4998b

drivers/gpu/msm/adreno.h

+0 −1
Original line number Original line Diff line number Diff line
@@ -969,7 +969,6 @@ struct adreno_gpudev { 
				unsigned int fsynr1);

				unsigned int fsynr1);

	int (*reset)(struct kgsl_device *, int fault);

	int (*reset)(struct kgsl_device *, int fault);

	int (*soft_reset)(struct adreno_device *);

	int (*soft_reset)(struct adreno_device *);

	bool (*gx_is_on)(struct adreno_device *);

	bool (*sptprac_is_on)(struct adreno_device *);

	bool (*sptprac_is_on)(struct adreno_device *);

	unsigned int (*ccu_invalidate)(struct adreno_device *adreno_dev,

	unsigned int (*ccu_invalidate)(struct adreno_device *adreno_dev,

				unsigned int *cmds);

				unsigned int *cmds);

drivers/gpu/msm/adreno_a6xx.c

+0 −1
Original line number Original line Diff line number Diff line
@@ -2948,7 +2948,6 @@ struct adreno_gpudev adreno_a6xx_gpudev = { 
	.set_marker = a6xx_set_marker,

	.set_marker = a6xx_set_marker,

	.preemption_context_init = a6xx_preemption_context_init,

	.preemption_context_init = a6xx_preemption_context_init,

	.preemption_context_destroy = a6xx_preemption_context_destroy,

	.preemption_context_destroy = a6xx_preemption_context_destroy,

	.gx_is_on = a6xx_gmu_gx_is_on,

	.sptprac_is_on = a6xx_sptprac_is_on,

	.sptprac_is_on = a6xx_sptprac_is_on,

	.ccu_invalidate = a6xx_ccu_invalidate,

	.ccu_invalidate = a6xx_ccu_invalidate,

	.perfcounter_update = a6xx_perfcounter_update,

	.perfcounter_update = a6xx_perfcounter_update,

drivers/gpu/msm/adreno_a6xx.h

+0 −1
Original line number Original line Diff line number Diff line
@@ -196,6 +196,5 @@ void a6xx_snapshot_debugbus(struct adreno_device *adreno_dev, 
void a6xx_crashdump_init(struct adreno_device *adreno_dev);

void a6xx_crashdump_init(struct adreno_device *adreno_dev);

int a6xx_gmu_sptprac_enable(struct adreno_device *adreno_dev);

int a6xx_gmu_sptprac_enable(struct adreno_device *adreno_dev);

void a6xx_gmu_sptprac_disable(struct adreno_device *adreno_dev);

void a6xx_gmu_sptprac_disable(struct adreno_device *adreno_dev);

bool a6xx_gmu_gx_is_on(struct adreno_device *adreno_dev);

bool a6xx_gmu_sptprac_is_on(struct adreno_device *adreno_dev);

bool a6xx_gmu_sptprac_is_on(struct adreno_device *adreno_dev);

#endif
 
#endif

drivers/gpu/msm/adreno_a6xx_gmu.c

+7 −7
Original line number Original line Diff line number Diff line
@@ -724,19 +724,16 @@ void a6xx_gmu_sptprac_disable(struct adreno_device *adreno_dev) 
#define GX_CLK_OFF		BIT(7)

#define GX_CLK_OFF		BIT(7)

#define is_on(val)		(!(val & (GX_GDSC_POWER_OFF | GX_CLK_OFF)))

#define is_on(val)		(!(val & (GX_GDSC_POWER_OFF | GX_CLK_OFF)))

/*

/*

 * a6xx_gx_is_on() - Check if GX is on using pwr status register

 * a6xx_gmu_gx_is_on() - Check if GX is on using pwr status register

 * @adreno_dev - Pointer to adreno_device

 * @adreno_dev - Pointer to adreno_device

 * This check should only be performed if the keepalive bit is set or it

 * This check should only be performed if the keepalive bit is set or it

 * can be guaranteed that the power state of the GPU will remain unchanged

 * can be guaranteed that the power state of the GPU will remain unchanged

 */

 */

bool a6xx_gmu_gx_is_on(struct adreno_device *adreno_dev)

static bool a6xx_gmu_gx_is_on(struct adreno_device *adreno_dev)

{

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	unsigned int val;

	unsigned int val;





	if (!gmu_core_isenabled(device))

		return true;



	gmu_core_regread(device, A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, &val);

	gmu_core_regread(device, A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, &val);

	return is_on(val);

	return is_on(val);

}

}
@@ -1363,12 +1360,12 @@ static void a6xx_gmu_snapshot(struct adreno_device *adreno_dev, 
{

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	struct gmu_device *gmu = KGSL_GMU_DEVICE(device);

	struct gmu_device *gmu = KGSL_GMU_DEVICE(device);

	bool gx_on;

	struct gmu_mem_type_desc desc[] = {

	struct gmu_mem_type_desc desc[] = {

		{gmu->hfi_mem, SNAPSHOT_GMU_HFIMEM},

		{gmu->hfi_mem, SNAPSHOT_GMU_HFIMEM},

		{gmu->gmu_log, SNAPSHOT_GMU_LOG},

		{gmu->gmu_log, SNAPSHOT_GMU_LOG},

		{gmu->bw_mem, SNAPSHOT_GMU_BWMEM},

		{gmu->bw_mem, SNAPSHOT_GMU_BWMEM},

		{gmu->dump_mem, SNAPSHOT_GMU_DUMPMEM} };

		{gmu->dump_mem, SNAPSHOT_GMU_DUMPMEM} };

	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	unsigned int val, i;

	unsigned int val, i;





	if (!gmu_core_isenabled(device))

	if (!gmu_core_isenabled(device))
@@ -1385,7 +1382,9 @@ static void a6xx_gmu_snapshot(struct adreno_device *adreno_dev, 
	adreno_snapshot_registers(device, snapshot, a6xx_gmu_registers,

	adreno_snapshot_registers(device, snapshot, a6xx_gmu_registers,

					ARRAY_SIZE(a6xx_gmu_registers) / 2);

					ARRAY_SIZE(a6xx_gmu_registers) / 2);





	if (gpudev->gx_is_on(adreno_dev)) {

	gx_on = a6xx_gmu_gx_is_on(adreno_dev);



	if (gx_on) {

		/* Set fence to ALLOW mode so registers can be read */

		/* Set fence to ALLOW mode so registers can be read */

		kgsl_regwrite(device, A6XX_GMU_AO_AHB_FENCE_CTRL, 0);

		kgsl_regwrite(device, A6XX_GMU_AO_AHB_FENCE_CTRL, 0);

		kgsl_regread(device, A6XX_GMU_AO_AHB_FENCE_CTRL, &val);

		kgsl_regread(device, A6XX_GMU_AO_AHB_FENCE_CTRL, &val);
@@ -1406,6 +1405,7 @@ struct gmu_dev_ops adreno_a6xx_gmudev = { 
	.hfi_start_msg = a6xx_gmu_hfi_start_msg,

	.hfi_start_msg = a6xx_gmu_hfi_start_msg,

	.enable_lm = a6xx_gmu_enable_lm,

	.enable_lm = a6xx_gmu_enable_lm,

	.rpmh_gpu_pwrctrl = a6xx_gmu_rpmh_gpu_pwrctrl,

	.rpmh_gpu_pwrctrl = a6xx_gmu_rpmh_gpu_pwrctrl,

	.gx_is_on = a6xx_gmu_gx_is_on,

	.wait_for_lowest_idle = a6xx_gmu_wait_for_lowest_idle,

	.wait_for_lowest_idle = a6xx_gmu_wait_for_lowest_idle,

	.wait_for_gmu_idle = a6xx_gmu_wait_for_idle,

	.wait_for_gmu_idle = a6xx_gmu_wait_for_idle,

	.ifpc_store = a6xx_gmu_ifpc_store,

	.ifpc_store = a6xx_gmu_ifpc_store,

drivers/gpu/msm/adreno_a6xx_snapshot.c

+5 −2
Original line number Original line Diff line number Diff line
@@ -1494,7 +1494,7 @@ void a6xx_snapshot(struct adreno_device *adreno_dev, 
	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	struct gmu_dev_ops *gmu_dev_ops = GMU_DEVICE_OPS(device);

	struct gmu_dev_ops *gmu_dev_ops = GMU_DEVICE_OPS(device);

	struct adreno_snapshot_data *snap_data = gpudev->snapshot_data;

	struct adreno_snapshot_data *snap_data = gpudev->snapshot_data;

	bool sptprac_on;

	bool sptprac_on, gx_on = true;

	unsigned int i, roq_size;

	unsigned int i, roq_size;





	/* ROQ size is 0x800 DW on a640 and a680 */

	/* ROQ size is 0x800 DW on a640 and a680 */
@@ -1507,8 +1507,11 @@ void a6xx_snapshot(struct adreno_device *adreno_dev, 




	sptprac_on = gpudev->sptprac_is_on(adreno_dev);

	sptprac_on = gpudev->sptprac_is_on(adreno_dev);





	if (GMU_DEV_OP_VALID(gmu_dev_ops, gx_is_on))

		gx_on = gmu_dev_ops->gx_is_on(adreno_dev);



	/* Return if the GX is off */

	/* Return if the GX is off */

	if (!gpudev->gx_is_on(adreno_dev))

	if (!gx_on)

		return;

		return;





	/* Dump the registers which get affected by crash dumper trigger */

	/* Dump the registers which get affected by crash dumper trigger */