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Commit 74583bf2 authored by Tony Truong's avatar Tony Truong Committed by Gerrit - the friendly Code Review server
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msm: pcie: remove max link speed property 



PCIe bus driver no longer needs to differentiate between the
type of cores since the settings are compatbile with all.
Therefore, remove the max link speed property.

Change-Id: I5935c2c0794eb62fe6a84ed5551c664b2cd89d43
Signed-off-by: default avatarTony Truong <truong@codeaurora.org>
parent 51683be8

Documentation/devicetree/bindings/pci/msm_pcie.txt

+0 −2
Original line number Original line Diff line number Diff line
@@ -73,7 +73,6 @@ Optional Properties: 
  - qcom,common-clk-en: Enables the common clock configuration for the endpoint.

  - qcom,common-clk-en: Enables the common clock configuration for the endpoint.

  - qcom,clk-power-manage-en: Enables the clock power management for the

  - qcom,clk-power-manage-en: Enables the clock power management for the

    endpoint.

    endpoint.

  - qcom,max-link-speed: Max Gen speed Root complex supports.

  - qcom,n-fts: The number of fast training sequences sent when the link state

  - qcom,n-fts: The number of fast training sequences sent when the link state

    is changed from L0s to L0.

    is changed from L0s to L0.

  - qcom,phy-power-down-offset: Offset from PCIe PHY base to control the power state

  - qcom,phy-power-down-offset: Offset from PCIe PHY base to control the power state
@@ -284,7 +283,6 @@ Example: 
		qcom,no-l1-supported;

		qcom,no-l1-supported;

		qcom,no-l1ss-supported;

		qcom,no-l1ss-supported;

		qcom,no-aux-clk-sync;

		qcom,no-aux-clk-sync;

		qcom,max-link-speed = <0x2>;

		qcom,n-fts = <0x50>;

		qcom,n-fts = <0x50>;

		qcom,pcie-phy-ver = <1>;

		qcom,pcie-phy-ver = <1>;

		qcom,boot-option = <0x1>;

		qcom,boot-option = <0x1>;

arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi

+0 −4
Original line number Original line Diff line number Diff line
@@ -210,8 +210,6 @@ 




		qcom,no-l0s-supported;

		qcom,no-l0s-supported;





		qcom,max-link-speed = <0x3>;



		qcom,ep-latency = <10>;

		qcom,ep-latency = <10>;





		qcom,slv-addr-space-size = <0x4000000>;

		qcom,slv-addr-space-size = <0x4000000>;
@@ -534,8 +532,6 @@ 




		qcom,no-l0s-supported;

		qcom,no-l0s-supported;





		qcom,max-link-speed = <0x3>;



		qcom,ep-latency = <10>;

		qcom,ep-latency = <10>;





		qcom,slv-addr-space-size = <0x20000000>;

		qcom,slv-addr-space-size = <0x20000000>;

drivers/pci/host/pci-msm.c

+16 −41
Original line number Original line Diff line number Diff line
@@ -596,7 +596,6 @@ struct msm_pcie_dev_t { 
	bool				aer_enable;

	bool				aer_enable;

	uint32_t			smmu_sid_base;

	uint32_t			smmu_sid_base;

	uint32_t			   n_fts;

	uint32_t			   n_fts;

	uint32_t			max_link_speed;

	bool				 ext_ref_clk;

	bool				 ext_ref_clk;

	uint32_t			   ep_latency;

	uint32_t			   ep_latency;

	uint32_t			switch_latency;

	uint32_t			switch_latency;
@@ -1301,8 +1300,6 @@ static void msm_pcie_show_status(struct msm_pcie_dev_t *dev) 
		dev->linkdown_counter);

		dev->linkdown_counter);

	PCIE_DBG_FS(dev, "wake_counter: %lu\n",

	PCIE_DBG_FS(dev, "wake_counter: %lu\n",

		dev->wake_counter);

		dev->wake_counter);

	PCIE_DBG_FS(dev, "max_link_speed: 0x%x\n",

		dev->max_link_speed);

	PCIE_DBG_FS(dev, "link_turned_on_counter: %lu\n",

	PCIE_DBG_FS(dev, "link_turned_on_counter: %lu\n",

		dev->link_turned_on_counter);

		dev->link_turned_on_counter);

	PCIE_DBG_FS(dev, "link_turned_off_counter: %lu\n",

	PCIE_DBG_FS(dev, "link_turned_off_counter: %lu\n",
@@ -3799,28 +3796,6 @@ static void msm_pcie_release_resources(struct msm_pcie_dev_t *dev) 
	dev->dev_io_res = NULL;

	dev->dev_io_res = NULL;

}

}





static void msm_pcie_setup_gen3(struct msm_pcie_dev_t *dev)

{

	PCIE_DBG(dev, "PCIe: RC%d: Setting up Gen3\n", dev->rc_idx);



	msm_pcie_write_reg_field(dev->dm_core,

		PCIE_GEN3_GEN2_CTRL, 0x1f00, 1);



	msm_pcie_write_mask(dev->dm_core,

		PCIE_GEN3_EQ_CONTROL, 0x20);



	msm_pcie_write_mask(dev->dm_core +

		PCIE_GEN3_RELATED, BIT(0), 0);



	/* configure PCIe preset */

	msm_pcie_write_reg_field(dev->dm_core,

		PCIE_GEN3_MISC_CONTROL, BIT(0), 1);

	msm_pcie_write_reg(dev->dm_core,

		PCIE_GEN3_SPCIE_CAP, 0x77777777);

	msm_pcie_write_reg_field(dev->dm_core,

		PCIE_GEN3_MISC_CONTROL, BIT(0), 0);

}



static int msm_pcie_enable(struct msm_pcie_dev_t *dev, u32 options)

static int msm_pcie_enable(struct msm_pcie_dev_t *dev, u32 options)

{

{

	int ret = 0;

	int ret = 0;
@@ -3940,12 +3915,6 @@ static int msm_pcie_enable(struct msm_pcie_dev_t *dev, u32 options) 
			goto link_fail;

			goto link_fail;

	}

	}





	/* check capability for max link speed */

	if (!dev->max_link_speed) {

		val = readl_relaxed(dev->dm_core + PCIE20_CAP + PCI_EXP_LNKCAP);

		dev->max_link_speed = val & PCI_EXP_LNKCAP_SLS;

	}



	PCIE_DBG(dev, "RC%d: waiting for phy ready...\n", dev->rc_idx);

	PCIE_DBG(dev, "RC%d: waiting for phy ready...\n", dev->rc_idx);





	do {

	do {
@@ -3986,9 +3955,22 @@ static int msm_pcie_enable(struct msm_pcie_dev_t *dev, u32 options) 




	ep_up_timeout = jiffies + usecs_to_jiffies(EP_UP_TIMEOUT_US);

	ep_up_timeout = jiffies + usecs_to_jiffies(EP_UP_TIMEOUT_US);





	/* setup Gen3 specific configurations */

	msm_pcie_write_reg_field(dev->dm_core,

	if (dev->max_link_speed == GEN3_SPEED)

		PCIE_GEN3_GEN2_CTRL, 0x1f00, 1);

		msm_pcie_setup_gen3(dev);



	msm_pcie_write_mask(dev->dm_core,

		PCIE_GEN3_EQ_CONTROL, 0x20);



	msm_pcie_write_mask(dev->dm_core +

		PCIE_GEN3_RELATED, BIT(0), 0);



	/* configure PCIe preset */

	msm_pcie_write_reg_field(dev->dm_core,

		PCIE_GEN3_MISC_CONTROL, BIT(0), 1);

	msm_pcie_write_reg(dev->dm_core,

		PCIE_GEN3_SPCIE_CAP, 0x77777777);

	msm_pcie_write_reg_field(dev->dm_core,

		PCIE_GEN3_MISC_CONTROL, BIT(0), 0);





	if (msm_pcie_force_gen1 & BIT(dev->rc_idx))

	if (msm_pcie_force_gen1 & BIT(dev->rc_idx))

		msm_pcie_write_reg_field(dev->dm_core,

		msm_pcie_write_reg_field(dev->dm_core,
@@ -5970,13 +5952,6 @@ static int msm_pcie_probe(struct platform_device *pdev) 
		PCIE_DBG(&msm_pcie_dev[rc_idx], "n-fts: 0x%x.\n",

		PCIE_DBG(&msm_pcie_dev[rc_idx], "n-fts: 0x%x.\n",

				msm_pcie_dev[rc_idx].n_fts);

				msm_pcie_dev[rc_idx].n_fts);





	msm_pcie_dev[rc_idx].max_link_speed = GEN2_SPEED;

	ret = of_property_read_u32(pdev->dev.of_node,

				"qcom,max-link-speed",

				&msm_pcie_dev[rc_idx].max_link_speed);

	PCIE_DBG(&msm_pcie_dev[rc_idx], "PCIe: RC%d: max-link-speed: 0x%x.\n",

		rc_idx, msm_pcie_dev[rc_idx].max_link_speed);



	msm_pcie_dev[rc_idx].ext_ref_clk =

	msm_pcie_dev[rc_idx].ext_ref_clk =

		of_property_read_bool((&pdev->dev)->of_node,

		of_property_read_bool((&pdev->dev)->of_node,

				"qcom,ext-ref-clk");

				"qcom,ext-ref-clk");