ARC: Fix misspellings in comments.

 * Since xchg() doesn't always do that, it would seem that following defintion

 * is incorrect. But here's the rationale:

 *   SMP : Even xchg() takes the atomic_ops_lock, so OK.

 *   LLSC: atomic_ops_lock are not relevent at all (even if SMP, since LLSC

 *   LLSC: atomic_ops_lock are not relevant at all (even if SMP, since LLSC

 *         is natively "SMP safe", no serialization required).

 *   UP  : other atomics disable IRQ, so no way a difft ctxt atomic_xchg()

 *         could clobber them. atomic_xchg() itself would be 1 insn, so it

	/* free up r9 as scratchpad */

	PROLOG_FREEUP_REG r9, @int\LVL\()_saved_reg

	/* Which mode (user/kernel) was the system in when intr occured */

	/* Which mode (user/kernel) was the system in when intr occurred */

	lr  r9, [status32_l\LVL\()]

	SWITCH_TO_KERNEL_STK

 *  - Utilise some unused free bits to confine PTE flags to 12 bits

 *     This is a must for 4k pg-sz

 *

 * vineetg: Mar 2011 - changes to accomodate MMU TLB Page Descriptor mods

 * vineetg: Mar 2011 - changes to accommodate MMU TLB Page Descriptor mods

 *  -TLB Locking never really existed, except for initial specs

 *  -SILENT_xxx not needed for our port

 *  -Per my request, MMU V3 changes the layout of some of the bits

#define ARC_REG_TIMER1_CTRL	0x101	/* timer 1 control */

#define ARC_REG_TIMER1_CNT	0x100	/* timer 1 count */

#define TIMER_CTRL_IE		(1 << 0) /* Interupt when Count reachs limit */

#define TIMER_CTRL_IE	(1 << 0) /* Interrupt when Count reaches limit */

#define TIMER_CTRL_NH	(1 << 1) /* Count only when CPU NOT halted */

#define ARC_TIMER_MAX	0xFFFFFFFF

/*

 * DMA ops for systems with both L1 and L2 caches, but without IOC

 * Both L1 and L2 lines need to be explicity flushed/invalidated

 * Both L1 and L2 lines need to be explicitly flushed/invalidated

 */

static void __dma_cache_wback_inv_slc(unsigned long start, unsigned long sz)

{