Merge "drm/msm: Add snapshot of SDE and supporting drivers" into msm-next

Optional properties:

- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY

  regulator is wanted.

- qcom,mdss-mdp-transfer-time-us:	Specifies the dsi transfer time for command mode

					panels in microseconds. Driver uses this number to adjust

					the clock rate according to the expected transfer time.

					Increasing this value would slow down the mdp processing

					and can result in slower performance.

					Decreasing this value can speed up the mdp processing,

					but this can also impact power consumption.

					As a rule this time should not be higher than the time

					that would be expected with the processing at the

					dsi link rate since anyways this would be the maximum

					transfer time that could be achieved.

					If ping pong split is enabled, this time should not be higher

					than two times the dsi link rate time.

					If the property is not specified, then the default value is 14000 us.

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

[2] Documentation/devicetree/bindings/graph.txt

		qcom,master-dsi;

		qcom,sync-dual-dsi;

		qcom,mdss-mdp-transfer-time-us = <12000>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&dsi_active>;

		pinctrl-1 = <&dsi_suspend>;

Qualcomm Technologies, Inc. SDE RSC

Snapdragon Display Engine implements display rsc to driver

display core to different modes for power saving

Required properties

- compatible:			Must be "qcom,sde-rsc"

- reg:				Offset and length of the register set for

				the device.

- reg-names:			Names to refer to register sets related

				to this device

Optional properties:

- clocks:			List of phandles for clock device nodes

				needed by the device.

- clock-names:			List of clock names needed by the device.

- vdd-supply:			phandle for vdd regulator device node.

- qcom,sde-rsc-version:		U32 property represents the rsc version. It helps to

				select correct sequence for sde rsc based on version.

- qcom,sde-dram-channels:	U32 property represents the number of channels in the

				Bus memory controller.

- qcom,sde-num-nrt-paths:	U32 property represents the number of non-realtime

				paths in each Bus Scaling Usecase. This value depends on

				number of AXI ports that are dedicated to non-realtime VBIF

				for particular chipset.

				These paths must be defined after rt-paths in

				"qcom,msm-bus,vectors-KBps" vector request.

Bus Scaling Subnodes:

- qcom,sde-data-bus:		Property to provide Bus scaling for data bus access for

				sde blocks.

- qcom,sde-llcc-bus:		Property to provide Bus scaling for data bus access for

				mnoc to llcc.

- qcom,sde-ebi-bus:		Property to provide Bus scaling for data bus access for

				llcc to ebi.

Bus Scaling Data:

- qcom,msm-bus,name:		String property describing client name.

- qcom,msm-bus,active-only:	Boolean context flag for requests in active or

				dual (active & sleep) contex

- qcom,msm-bus,num-cases:	This is the number of Bus Scaling use cases

				defined in the vectors property.

- qcom,msm-bus,num-paths:	This represents the number of paths in each

				Bus Scaling Usecase.

- qcom,msm-bus,vectors-KBps:	* A series of 4 cell properties, with a format

				of (src, dst, ab, ib) which is defined at

				Documentation/devicetree/bindings/arm/msm/msm_bus.txt

				* Current values of src & dst are defined at

				include/linux/msm-bus-board.h

Example:

	sde_rscc {

		cell-index = <0>;

		compatible = "qcom,sde-rsc";

		reg = <0xaf20000 0x1c44>,

			<0xaf30000 0x3fd4>;

		reg-names = "drv", "wrapper";

		clocks = <&clock_mmss clk_mdss_ahb_clk>,

			<&clock_mmss clk_mdss_axi_clk>;

		clock-names = "iface_clk", "bus_clk";

		vdd-supply = <&gdsc_mdss>;

		qcom,sde-rsc-version = <1>;

		qcom,sde-dram-channels = <2>;

		qcom,sde-num-nrt-paths = <1>;

		qcom,sde-data-bus {

		      qcom,msm-bus,name = "sde_rsc";

		      qcom,msm-bus,active-only;

		      qcom,msm-bus,num-cases = <3>;

		      qcom,msm-bus,num-paths = <2>;

		      qcom,msm-bus,vectors-KBps =

		          <22 512 0 0>, <23 512 0 0>,

		          <22 512 0 6400000>, <23 512 0 6400000>,

		          <22 512 0 6400000>, <23 512 0 6400000>;

		};

		qcom,sde-llcc-bus {

			qcom,msm-bus,name = "sde_rsc_llcc";

			qcom,msm-bus,active-only;

			qcom,msm-bus,num-cases = <3>;

			qcom,msm-bus,num-paths = <1>;

			qcom,msm-bus,vectors-KBps =

			    <20001 20513 0 0>,

			    <20001 20513 0 6400000>,

			    <20001 20513 0 6400000>;

		};

		qcom,sde-ebi-bus {

			qcom,msm-bus,name = "sde_rsc_ebi";

			qcom,msm-bus,active-only;

			qcom,msm-bus,num-cases = <3>;

			qcom,msm-bus,num-paths = <1>;

			qcom,msm-bus,vectors-KBps =

			    <20000 20512 0 0>,

			    <20000 20512 0 6400000>,

			    <20000 20512 0 6400000>;

		};

	};

Qualcomm Technologies, Inc.

sde-dp is the master Display Port device which supports DP host controllers that are compatible with VESA Display Port interface specification.

DP Controller: Required properties:

- compatible:           Should be "qcom,dp-display".

- reg:                  Base address and length of DP hardware's memory mapped regions.

- reg-names:            A list of strings that name the list of regs. "dp_ctrl" - DP controller memory region.

			"dp_phy" - DP PHY memory region.

			"dp_ln_tx0" - USB3 DP PHY combo TX-0 lane memory region.

			"dp_ln_tx1" - USB3 DP PHY combo TX-1 lane memory region.

			"dp_mmss_cc" - Display Clock Control memory region.

			"qfprom_physical" - QFPROM Phys memory region.

			"dp_pll" - USB3 DP combo PLL memory region.

			"usb3_dp_com" - USB3 DP PHY combo memory region.

			"hdcp_physical" - DP HDCP memory region.

- cell-index:           Specifies the controller instance.

- clocks:               Clocks required for Display Port operation.

- clock-names:          Names of the clocks corresponding to handles. Following clocks are required:

			"core_aux_clk", "core_usb_ref_clk_src","core_usb_ref_clk", "core_usb_cfg_ahb_clk",

			"core_usb_pipe_clk", "ctrl_link_clk", "ctrl_link_iface_clk", "ctrl_crypto_clk",

			"ctrl_pixel_clk", "pixel_clk_rcg", "pixel_parent".

- gdsc-supply:		phandle to gdsc regulator node.

- vdda-1p2-supply:		phandle to vdda 1.2V regulator node.

- vdda-0p9-supply:		phandle to vdda 0.9V regulator node.

- interrupt-parent	phandle to the interrupt parent device node.

- interrupts:		The interrupt signal from the DSI block.

- qcom,aux-en-gpio:			Specifies the aux-channel enable gpio.

- qcom,aux-sel-gpio:		Specifies the aux-channel select gpio.

- qcom,usbplug-cc-gpio:		Specifies the usbplug orientation gpio.

- qcom,aux-cfg0-settings:		Specifies the DP AUX configuration 0 settings. The first

					entry in this array corresponds to the register offset

					within DP AUX, while the remaining entries indicate the

					programmable values.

- qcom,aux-cfg1-settings:		Specifies the DP AUX configuration 1 settings. The first

					entry in this array corresponds to the register offset

					within DP AUX, while the remaining entries indicate the

					programmable values.

- qcom,aux-cfg2-settings:		Specifies the DP AUX configuration 2 settings. The first

					entry in this array corresponds to the register offset

					within DP AUX, while the remaining entries indicate the

					programmable values.

- qcom,aux-cfg3-settings:		Specifies the DP AUX configuration 3 settings. The first

					entry in this array corresponds to the register offset

					within DP AUX, while the remaining entries indicate the

					programmable values.

- qcom,aux-cfg4-settings:		Specifies the DP AUX configuration 4 settings. The first

					entry in this array corresponds to the register offset

					within DP AUX, while the remaining entries indicate the

					programmable values.

- qcom,aux-cfg5-settings:		Specifies the DP AUX configuration 5 settings. The first

					entry in this array corresponds to the register offset

					within DP AUX, while the remaining entries indicate the

					programmable values.

- qcom,aux-cfg6-settings:		Specifies the DP AUX configuration 6 settings. The first

					entry in this array corresponds to the register offset

					within DP AUX, while the remaining entries indicate the

					programmable values.

- qcom,aux-cfg7-settings:		Specifies the DP AUX configuration 7 settings. The first

					entry in this array corresponds to the register offset

					within DP AUX, while the remaining entries indicate the

					programmable values.

- qcom,aux-cfg8-settings:		Specifies the DP AUX configuration 8 settings. The first

					entry in this array corresponds to the register offset

					within DP AUX, while the remaining entries indicate the

					programmable values.

- qcom,aux-cfg9-settings:		Specifies the DP AUX configuration 9 settings. The first

					entry in this array corresponds to the register offset

					within DP AUX, while the remaining entries indicate the

					programmable values.

- qcom,max-pclk-frequency-khz:	An integer specifying the max. pixel clock in KHz supported by Display Port.

- qcom,dp-usbpd-detection:	Phandle for the PMI regulator node for USB PHY PD detection.

- qcom,<type>-supply-entries:		A node that lists the elements of the supply used by the a particular "type" of DSI module. The module "types"

					can be "core", "ctrl", and "phy". Within the same type,

					there can be more than one instance of this binding,

					in which case the entry would be appended with the

					supply entry index.

					e.g. qcom,ctrl-supply-entry@0

					-- qcom,supply-name: name of the supply (vdd/vdda/vddio)

					-- qcom,supply-min-voltage: minimum voltage level (uV)

					-- qcom,supply-max-voltage: maximum voltage level (uV)

					-- qcom,supply-enable-load: load drawn (uA) from enabled supply

					-- qcom,supply-disable-load: load drawn (uA) from disabled supply

					-- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on

					-- qcom,supply-post-on-sleep: time to sleep (ms) after turning on

					-- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off

					-- qcom,supply-post-off-sleep: time to sleep (ms) after turning off

- pinctrl-names:	List of names to assign mdss pin states defined in pinctrl device node

					Refer to pinctrl-bindings.txt

- pinctrl-<0..n>:	Lists phandles each pointing to the pin configuration node within a pin

					controller. These pin configurations are installed in the pinctrl

					device node. Refer to pinctrl-bindings.txt

msm_ext_disp is a device which manages the interaction between external

display interfaces, e.g. Display Port, and the audio subsystem.

Optional properties:

- qcom,ext-disp:		phandle for msm-ext-display module

- compatible:			Must be "qcom,msm-ext-disp"

[Optional child nodes]: These nodes are for devices which are

dependent on msm_ext_disp. If msm_ext_disp is disabled then

these devices will be disabled as well. Ex. Audio Codec device.

- ext_disp_audio_codec: Node for Audio Codec.

- compatible : "qcom,msm-ext-disp-audio-codec-rx";

Example:

	ext_disp: qcom,msm-ext-disp {

		compatible = "qcom,msm-ext-disp";

		ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {

			compatible = "qcom,msm-ext-disp-audio-codec-rx";

		};

	};

	sde_dp: qcom,dp_display@0{

		cell-index = <0>;

		compatible = "qcom,dp-display";

		gdsc-supply = <&mdss_core_gdsc>;

		vdda-1p2-supply = <&pm8998_l26>;

		vdda-0p9-supply = <&pm8998_l1>;

		reg =	<0xae90000 0xa84>,

			<0x88eaa00 0x200>,

			<0x88ea200 0x200>,

			<0x88ea600 0x200>,

			<0xaf02000 0x1a0>,

			<0x780000 0x621c>,

			<0x88ea030 0x10>,

			<0x88e8000 0x621c>,

			<0x0aee1000 0x034>;

		reg-names = "dp_ctrl", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",

			"dp_mmss_cc", "qfprom_physical", "dp_pll",

			"usb3_dp_com", "hdcp_physical";

		interrupt-parent = <&mdss_mdp>;

		interrupts = <12 0>;

		clocks =  <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>,

			 <&clock_rpmh RPMH_CXO_CLK>,

			 <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>,

			 <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,

			 <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,

			 <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>,

			 <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,

			 <&clock_dispcc DISP_CC_MDSS_DP_CRYPTO_CLK>,

			 <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,

			 <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,

			 <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>;

		clock-names = "core_aux_clk", "core_usb_ref_clk_src",

			"core_usb_ref_clk", "core_usb_cfg_ahb_clk",

			"core_usb_pipe_clk", "ctrl_link_clk",

			"ctrl_link_iface_clk", "ctrl_crypto_clk",

			"ctrl_pixel_clk", "pixel_clk_rcg", "pixel_parent";

		qcom,dp-usbpd-detection = <&pmi8998_pdphy>;

		qcom,ext-disp = <&ext_disp>;

		qcom,aux-cfg0-settings = [1c 00];

		qcom,aux-cfg1-settings = [20 13 23 1d];

		qcom,aux-cfg2-settings = [24 00];

		qcom,aux-cfg3-settings = [28 00];

		qcom,aux-cfg4-settings = [2c 0a];

		qcom,aux-cfg5-settings = [30 26];

		qcom,aux-cfg6-settings = [34 0a];

		qcom,aux-cfg7-settings = [38 03];

		qcom,aux-cfg8-settings = [3c bb];

		qcom,aux-cfg9-settings = [40 03];

		qcom,max-pclk-frequency-khz = <593470>;

		pinctrl-names = "mdss_dp_active", "mdss_dp_sleep";

		pinctrl-0 = <&sde_dp_aux_active &sde_dp_usbplug_cc_active>;

		pinctrl-1 = <&sde_dp_aux_suspend &sde_dp_usbplug_cc_suspend>;

		qcom,aux-en-gpio = <&tlmm 43 0>;

		qcom,aux-sel-gpio = <&tlmm 51 0>;

		qcom,usbplug-cc-gpio = <&tlmm 38 0>;

		qcom,core-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;

			qcom,core-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "gdsc";

				qcom,supply-min-voltage = <0>;

				qcom,supply-max-voltage = <0>;

				qcom,supply-enable-load = <0>;

				qcom,supply-disable-load = <0>;

			};

		};

		qcom,ctrl-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;

			qcom,ctrl-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "vdda-1p2";

				qcom,supply-min-voltage = <1200000>;

				qcom,supply-max-voltage = <1200000>;

				qcom,supply-enable-load = <21800>;

				qcom,supply-disable-load = <4>;

			};

		};

		qcom,phy-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;

			qcom,phy-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "vdda-0p9";

				qcom,supply-min-voltage = <880000>;

				qcom,supply-max-voltage = <880000>;

				qcom,supply-enable-load = <36000>;

				qcom,supply-disable-load = <32>;

			};

		};

	};

};