Merge "iommu: arm-smmu: Print page-table entry (PTE) info on cb fault" (73cb771a) · Commits · e / devices / android_kernel_oneplus_sm8150

drivers/iommu/arm-smmu-regs.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -179,6 +179,7 @@ enum arm_smmu_s2cr_privcfg {
		#define ARM_SMMU_CB_FSRRESTORE 0x5c
		#define ARM_SMMU_CB_FAR 0x60
		#define ARM_SMMU_CB_FSYNR0 0x68
		#define ARM_SMMU_CB_FSYNR1 0x6c
		#define ARM_SMMU_CB_S1_TLBIVA 0x600
		#define ARM_SMMU_CB_S1_TLBIASID 0x610
		#define ARM_SMMU_CB_S1_TLBIALL 0x618

drivers/iommu/arm-smmu.c

+21 −13

Original line number	Diff line number	Diff line
		@@ -1266,7 +1266,7 @@ static phys_addr_t arm_smmu_verify_fault(struct iommu_domain *domain,
		static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
		{
		int flags, ret, tmp;
		u32 fsr, fsynr, resume;
		u32 fsr, fsynr0, fsynr1, frsynra, resume;
		unsigned long iova;
		struct iommu_domain *domain = dev;
		struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
		@@ -1276,7 +1276,7 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
		void __iomem *gr1_base;
		bool fatal_asf = smmu->options & ARM_SMMU_OPT_FATAL_ASF;
		phys_addr_t phys_soft;
		u32 frsynra;
		uint64_t pte;
		bool non_fatal_fault = !!(smmu_domain->attributes &
		(1 << DOMAIN_ATTR_NON_FATAL_FAULTS));

		@@ -1303,8 +1303,9 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
		BUG();
		}

		fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
		flags = fsynr & FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ;
		fsynr0 = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
		fsynr1 = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR1);
		flags = fsynr0 & FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ;
		if (fsr & FSR_TF)
		flags \|= IOMMU_FAULT_TRANSLATION;
		if (fsr & FSR_PF)
		@@ -1321,8 +1322,8 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
		tmp = report_iommu_fault(domain, smmu->dev, iova, flags);
		if (!tmp \|\| (tmp == -EBUSY)) {
		dev_dbg(smmu->dev,
		"Context fault handled by client: iova=0x%08lx, fsr=0x%x, fsynr=0x%x, cb=%d\n",
		iova, fsr, fsynr, cfg->cbndx);
		"Context fault handled by client: iova=0x%08lx, cb=%d, fsr=0x%x, fsynr0=0x%x, fsynr1=0x%x\n",
		iova, cfg->cbndx, fsr, fsynr0, fsynr1);
		dev_dbg(smmu->dev,
		"soft iova-to-phys=%pa\n", &phys_soft);
		ret = IRQ_HANDLED;
		@@ -1332,20 +1333,23 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
		fsr);
		if (__ratelimit(&_rs)) {
		dev_err(smmu->dev,
		"Unhandled context fault: iova=0x%08lx, fsr=0x%x, fsynr=0x%x, cb=%d\n",
		iova, fsr, fsynr, cfg->cbndx);
		"Unhandled context fault: iova=0x%08lx, cb=%d, fsr=0x%x, fsynr0=0x%x, fsynr1=0x%x\n",
		iova, cfg->cbndx, fsr, fsynr0, fsynr1);
		dev_err(smmu->dev, "FAR = %016lx\n",
		(unsigned long)iova);
		dev_err(smmu->dev,
		"FSR = %08x [%s%s%s%s%s%s%s%s%s]\n",
		"FSR = %08x [%s%s%s%s%s%s%s%s%s%s]\n",
		fsr,
		(fsr & 0x02) ? "TF " : "",
		(fsr & 0x02) ? (fsynr0 & 0x10 ?
		"TF W " : "TF R ") : "",
		(fsr & 0x04) ? "AFF " : "",
		(fsr & 0x08) ? "PF " : "",
		(fsr & 0x08) ? (fsynr0 & 0x10 ?
		"PF W " : "PF R ") : "",
		(fsr & 0x10) ? "EF " : "",
		(fsr & 0x20) ? "TLBMCF " : "",
		(fsr & 0x40) ? "TLBLKF " : "",
		(fsr & 0x80) ? "MHF " : "",
		(fsr & 0x100) ? "UUT " : "",
		(fsr & 0x40000000) ? "SS " : "",
		(fsr & 0x80000000) ? "MULTI " : "");
		dev_err(smmu->dev,
		@@ -1354,6 +1358,10 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
		dev_err(smmu->dev,
		"SOFTWARE TABLE WALK FAILED! Looks like %s accessed an unmapped address!\n",
		dev_name(smmu->dev));
		else {
		pte = arm_smmu_iova_to_pte(domain, iova);
		dev_err(smmu->dev, "PTE = %016llx\n", pte);
		}
		if (phys_atos)
		dev_err(smmu->dev, "hard iova-to-phys (ATOS)=%pa\n",
		&phys_atos);
		@@ -5081,8 +5089,8 @@ static phys_addr_t qsmmuv500_iova_to_phys(
		val = readq_relaxed(tbu->base + DEBUG_PAR_REG);
		fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR);
		if (fsr & FSR_FAULT) {
		dev_err(tbu->dev, "ECATS generated a fault interrupt! FSR = %llx\n",
		fsr);
		dev_err(tbu->dev, "ECATS generated a fault interrupt! FSR = %llx, SID=0x%x\n",
		fsr, sid);

		/* Clear pending interrupts */
		writel_relaxed(fsr, cb_base + ARM_SMMU_CB_FSR);