Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 7374c28c authored May 07, 2019 by Manaf Meethalavalappu Pallikunhi

ARM: dts: msm: update thermal zone thresholds for SA8155



Update thermal zone thresholds for gpu, cpu isolation, npu and
cdsp thermal zones based on latest recommendation for SA8155.

Disable pop-mem thermal zone for SA8155.

Change-Id: Ia6e0617e4e57dda5e6ce97acd70f229daa7c56da
Signed-off-by: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>

parent 2e04b40c

arch/arm64/boot/dts/qcom/sa8155.dtsi

+127 −0

Original line number	Diff line number	Diff line
		@@ -382,6 +382,133 @@
		};
		};
		};

		gpuss-max-step {
		trips {
		gpu-trip0 {
		temperature = <100000>;
		};
		};
		};

		pop-mem-step {
		status = "disabled";
		};

		npu-step {
		trips {
		npu-trip0 {
		temperature = <105000>;
		};
		};
		};

		cpu-0-0-step {
		trips {
		cpu00-config {
		temperature = <115000>;
		};
		};
		};

		cpu-0-1-step {
		trips {
		cpu01-config {
		temperature = <115000>;
		};
		};
		};

		cpu-0-2-step {
		trips {
		cpu02-config {
		temperature = <115000>;
		};
		};
		};

		cpu-0-3-step {
		trips {
		cpu03-config {
		temperature = <115000>;
		};
		};
		};

		cpu-1-0-step {
		trips {
		cpu10-config {
		temperature = <115000>;
		};
		};
		};

		cpu-1-1-step {
		trips {
		cpu11-config {
		temperature = <115000>;
		};
		};
		};

		cpu-1-2-step {
		trips {
		cpu12-config {
		temperature = <115000>;
		};
		};
		};

		cpu-1-3-step {
		trips {
		cpu13-config {
		temperature = <115000>;
		};
		};
		};

		cpu-1-4-step {
		trips {
		cpu14-config {
		temperature = <115000>;
		};
		};
		};

		cpu-1-5-step {
		trips {
		cpu15-config {
		temperature = <115000>;
		};
		};
		};

		cpu-1-6-step {
		trips {
		cpu16-config {
		temperature = <115000>;
		};
		};
		};

		cpu-1-7-step {
		trips {
		cpu17-config {
		temperature = <115000>;
		};
		};
		};

		q6-hvx-step {
		trips {
		q6-hvx-step0 {
		temperature = <105000>;
		};
		q6-hvx-step1 {
		temperature = <115000>;
		};
		};
		};
		};

		&mdss_dsi0_pll {