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Commit 72f962fc authored by Tero Kristo's avatar Tero Kristo Committed by Tony Lindgren
Browse files

omap3: clock: Fixed dpll3_m2x2 rate calculation 



Current calculation does not take into account any changes to M2 divisor, and
thus when we change VDD2 OPP, dpll3_m2x2 rate does not change. Fixed by
re-routing dpll3_m2x2 parent to dpll3_m2.

Signed-off-by: default avatarTero Kristo <tero.kristo@nokia.com>
Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 9346f48b

arch/arm/mach-omap2/clock34xx.h

+2 −2
Original line number Diff line number Diff line
@@ -489,9 +489,9 @@ static struct clk core_ck = { 
static struct clk dpll3_m2x2_ck = {

	.name		= "dpll3_m2x2_ck",

	.ops		= &clkops_null,

	.parent		= &dpll3_x2_ck,

	.parent		= &dpll3_m2_ck,

	.clkdm_name	= "dpll3_clkdm",

	.recalc		= &followparent_recalc,

	.recalc		= &omap3_clkoutx2_recalc,

};



/* The PWRDN bit is apparently only available on 3430ES2 and above */