Merge "defconfig: enable devfreq and cpufreq drivers for qcs405 target" (72e19d05) · Commits · e / devices / android_kernel_oneplus_sm8150

arch/arm64/boot/dts/qcom/qcs403.dtsi

+14 −0

Original line number	Diff line number	Diff line
		@@ -18,3 +18,17 @@
		qcom,msm-name = "QCS403";
		qcom,msm-id = <373 0x0>;
		};

		&soc {
		/delete-node/ qcom,cpu0-computemon;

		cpu0_computemon: qcom,cpu0-computemon {
		compatible = "qcom,arm-cpu-mon";
		qcom,cpulist = <&CPU0 &CPU1>;
		qcom,target-dev = <&cpu0_cpu_ddr_latfloor>;
		qcom,core-dev-table =
		< 1113600 MHZ_TO_MBPS( 297, 4) >,
		< 1267200 MHZ_TO_MBPS( 597, 4) >,
		< 1401600 MHZ_TO_MBPS( 710, 4) >;
		};
		};

arch/arm64/boot/dts/qcom/qcs405.dtsi

+56 −0

Original line number	Diff line number	Diff line
		@@ -20,6 +20,9 @@
		#include <dt-bindings/interrupt-controller/arm-gic.h>
		#include <dt-bindings/gpio/gpio.h>

		#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
		#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}

		/ {
		model = "Qualcomm Technologies, Inc. QCS405";
		compatible = "qcom,qcs405";
		@@ -981,6 +984,59 @@

		status = "disabled";
		};

		msm_cpufreq: qcom,msm-cpufreq {
		compatible = "qcom,msm-cpufreq";
		clock-names = "cpu0_clk";
		clocks = <&clock_cpu APCS_MUX_CLK>;

		qcom,cpufreq-table =
		< 1113600 >,
		< 1267200 >,
		< 1401600 >;
		};

		ddr_bw_opp_table: ddr-bw-opp-table {
		compatible = "operating-points-v2";
		BW_OPP_ENTRY( 297, 4); /* 1132 MB/s */
		BW_OPP_ENTRY( 595, 4); /* 2269 MB/s */
		BW_OPP_ENTRY( 710, 4); /* 2708 MB/s */
		};

		cpubw: qcom,cpubw {
		compatible = "qcom,devbw";
		governor = "performance";
		qcom,src-dst-ports = <1 512>;
		qcom,active-only;
		operating-points-v2 = <&ddr_bw_opp_table>;
		};

		qcom,cpu-bwmon {
		compatible = "qcom,bimc-bwmon2";
		reg = <0x408000 0x300>, <0x401000 0x200>;
		reg-names = "base", "global_base";
		interrupts = <0 183 4>;
		qcom,mport = <0>;
		qcom,target-dev = <&cpubw>;
		};

		cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor {
		compatible = "qcom,devbw";
		governor = "performance";
		qcom,src-dst-ports = <1 512>;
		qcom,active-only;
		operating-points-v2 = <&ddr_bw_opp_table>;
		};

		cpu0_computemon: qcom,cpu0-computemon {
		compatible = "qcom,arm-cpu-mon";
		qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
		qcom,target-dev = <&cpu0_cpu_ddr_latfloor>;
		qcom,core-dev-table =
		< 1113600 MHZ_TO_MBPS( 297, 4) >,
		< 1267200 MHZ_TO_MBPS( 597, 4) >,
		< 1401600 MHZ_TO_MBPS( 710, 4) >;
		};
		};

		#include "qcs405-gdsc.dtsi"

arch/arm64/configs/vendor/qcs405_defconfig

+8 −0

Original line number	Diff line number	Diff line
		@@ -50,7 +50,10 @@ CONFIG_PM_DEBUG=y
		CONFIG_CPU_IDLE=y
		CONFIG_ARM_CPUIDLE=y
		CONFIG_CPU_FREQ=y
		CONFIG_CPU_FREQ_GOV_POWERSAVE=y
		CONFIG_CPU_FREQ_GOV_USERSPACE=y
		CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
		CONFIG_CPU_FREQ_MSM=y
		CONFIG_NET=y
		CONFIG_PACKET=y
		CONFIG_UNIX=y
		@@ -429,6 +432,11 @@ CONFIG_MSM_TZ_SMMU=y
		CONFIG_QCOM_GLINK=y
		CONFIG_QCOM_GLINK_PKT=y
		CONFIG_MSM_PM=y
		CONFIG_QCOM_BIMC_BWMON=y
		CONFIG_ARM_MEMLAT_MON=y
		CONFIG_DEVFREQ_GOV_QCOM_BW_HWMON=y
		CONFIG_DEVFREQ_GOV_MEMLAT=y
		CONFIG_QCOM_DEVFREQ_DEVBW=y
		CONFIG_EXTCON_USB_GPIO=y
		CONFIG_IIO=y
		CONFIG_QCOM_SPMI_ADC5=y