diff --git a/.gitignore b/.gitignore index be92dfa89957c112c7231d3b3c637cd46736e354..91230933968bc52bde7f75bcf071554fa048498e 100644 --- a/.gitignore +++ b/.gitignore @@ -125,3 +125,23 @@ all.config # fetched Android config fragments kernel/configs/android-*.cfg + +include/linux/oem +drivers/oem_debug +drivers/param_read_write +drivers/input/oneplus_touchscreen +drivers/input/fingerprint +fs/exfat +fs/proc/adj_chain_stat.c +fs/proc/fg_uid.c +fs/proc/fg_uid.h +mm/memory_monitor.c + +# OP SLA feature +opslalib/slalib + +#front camera motor and hall +drivers/step_motor +drivers/tri_state_key +drivers/oneplus +drivers/vibrator diff --git a/AndroidKernel.mk b/AndroidKernel.mk index 270dc28d357a84ef821ff3ce9646738b55041ec0..e19c5eb406a51d9b50cd6555b102189f7a775fb6 100644 --- a/AndroidKernel.mk +++ b/AndroidKernel.mk @@ -165,31 +165,14 @@ $(KERNEL_CONFIG): $(KERNEL_OUT) echo $(KERNEL_CONFIG_OVERRIDE) >> $(KERNEL_OUT)/.config; \ $(MAKE) -C $(TARGET_KERNEL_SOURCE) O=$(BUILD_ROOT_LOC)$(KERNEL_OUT) $(KERNEL_MAKE_ENV) ARCH=$(KERNEL_ARCH) CROSS_COMPILE=$(KERNEL_CROSS_COMPILE) $(real_cc) oldconfig; fi -ifeq ($(TARGET_KERNEL_APPEND_DTB), true) -TARGET_PREBUILT_INT_KERNEL_IMAGE := $(KERNEL_OUT)/arch/$(KERNEL_ARCH)/boot/Image -$(TARGET_PREBUILT_INT_KERNEL_IMAGE): $(KERNEL_USR) -$(TARGET_PREBUILT_INT_KERNEL_IMAGE): $(KERNEL_OUT) $(KERNEL_HEADERS_INSTALL) - $(hide) echo "Building kernel modules..." - $(MAKE) -C $(TARGET_KERNEL_SOURCE) O=$(BUILD_ROOT_LOC)$(KERNEL_OUT) $(KERNEL_MAKE_ENV) ARCH=$(KERNEL_ARCH) CROSS_COMPILE=$(KERNEL_CROSS_COMPILE) $(real_cc) $(KERNEL_CFLAGS) Image - $(MAKE) -C $(TARGET_KERNEL_SOURCE) O=$(BUILD_ROOT_LOC)$(KERNEL_OUT) $(KERNEL_MAKE_ENV) ARCH=$(KERNEL_ARCH) CROSS_COMPILE=$(KERNEL_CROSS_COMPILE) $(real_cc) $(KERNEL_CFLAGS) modules - $(MAKE) -C $(TARGET_KERNEL_SOURCE) O=$(BUILD_ROOT_LOC)$(KERNEL_OUT) INSTALL_MOD_PATH=$(BUILD_ROOT_LOC)../$(KERNEL_MODULES_INSTALL) INSTALL_MOD_STRIP=1 $(KERNEL_MAKE_ENV) ARCH=$(KERNEL_ARCH) CROSS_COMPILE=$(KERNEL_CROSS_COMPILE) $(real_cc) modules_install - $(mv-modules) - $(clean-module-folder) - -$(TARGET_PREBUILT_INT_KERNEL): $(TARGET_PREBUILT_INT_KERNEL_IMAGE) - $(hide) echo "Building kernel..." - $(hide) rm -rf $(KERNEL_OUT)/arch/$(KERNEL_ARCH)/boot/dts - $(MAKE) -C $(TARGET_KERNEL_SOURCE) O=$(BUILD_ROOT_LOC)$(KERNEL_OUT) $(KERNEL_MAKE_ENV) ARCH=$(KERNEL_ARCH) CROSS_COMPILE=$(KERNEL_CROSS_COMPILE) $(real_cc) $(KERNEL_CFLAGS) -else -TARGET_PREBUILT_INT_KERNEL_IMAGE := $(TARGET_PREBUILT_INT_KERNEL) $(TARGET_PREBUILT_INT_KERNEL): $(KERNEL_OUT) $(KERNEL_HEADERS_INSTALL) $(hide) echo "Building kernel..." + $(hide) rm -rf $(KERNEL_OUT)/arch/$(KERNEL_ARCH)/boot/dts $(MAKE) -C $(TARGET_KERNEL_SOURCE) O=$(BUILD_ROOT_LOC)$(KERNEL_OUT) $(KERNEL_MAKE_ENV) ARCH=$(KERNEL_ARCH) CROSS_COMPILE=$(KERNEL_CROSS_COMPILE) $(real_cc) $(KERNEL_CFLAGS) $(MAKE) -C $(TARGET_KERNEL_SOURCE) O=$(BUILD_ROOT_LOC)$(KERNEL_OUT) $(KERNEL_MAKE_ENV) ARCH=$(KERNEL_ARCH) CROSS_COMPILE=$(KERNEL_CROSS_COMPILE) $(real_cc) $(KERNEL_CFLAGS) modules $(MAKE) -C $(TARGET_KERNEL_SOURCE) O=$(BUILD_ROOT_LOC)$(KERNEL_OUT) INSTALL_MOD_PATH=$(BUILD_ROOT_LOC)../$(KERNEL_MODULES_INSTALL) INSTALL_MOD_STRIP=1 $(KERNEL_MAKE_ENV) ARCH=$(KERNEL_ARCH) CROSS_COMPILE=$(KERNEL_CROSS_COMPILE) $(real_cc) modules_install $(mv-modules) $(clean-module-folder) -endif $(KERNEL_HEADERS_INSTALL): $(KERNEL_OUT) $(hide) if [ ! -z "$(KERNEL_HEADER_DEFCONFIG)" ]; then \ diff --git a/Documentation/devicetree/bindings/arm/msm/msm.txt b/Documentation/devicetree/bindings/arm/msm/msm.txt index 750ef33e09f4b7f3bfb935cc3e4bfa39aa789122..850bb51db595b9664f184deebdb30bd1953854a7 100644 --- a/Documentation/devicetree/bindings/arm/msm/msm.txt +++ b/Documentation/devicetree/bindings/arm/msm/msm.txt @@ -62,12 +62,6 @@ SoCs: - QCS401 compatible = "qcom,qcs401" -- QCS404 - compatible = "qcom,qcs404" - -- QCS407 - compatible = "qcom,qcs407" - - SDXPRAIRIE compatible = "qcom,sdxprairie" @@ -201,8 +195,6 @@ compatible = "qcom,qcs405-rumi" compatible = "qcom,qcs405-iot" compatible = "qcom,qcs403-iot" compatible = "qcom,qcs401-iot" -compatible = "qcom,qcs404-iot" -compatible = "qcom,qcs407-iot" compatible = "qcom,sa8155-adp-star" compatible = "qcom,sa8155p-adp-star" compatible = "qcom,sa8195p-adp-star" @@ -231,7 +223,6 @@ compatible = "qcom,trinket-idp" compatible = "qcom,trinket-qrd" compatible = "qcom,atoll-rumi" compatible = "qcom,atoll-idp" -compatible = "qcom,atoll-atp" compatible = "qcom,atoll-qrd" compatible = "qcom,qcs610-iot" compatible = "qcom,qcs410-iot" diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,osm.txt b/Documentation/devicetree/bindings/arm/msm/qcom,osm.txt index 6a8128765ff736a8604d1be197411526ee38af63..4b688137043574cbffa43dbe5616e21f24089d89 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,osm.txt +++ b/Documentation/devicetree/bindings/arm/msm/qcom,osm.txt @@ -12,8 +12,7 @@ Properties: Definition: must be "qcom,clk-cpu-osm" or "qcom,clk-cpu-osm-sdmshrike" or "qcom,clk-cpu-osm-sm6150" or "qcom,clk-cpu-osm-sdmmagpie" or - "qcom,clk-cpu-osm-trinket" or - "qcom,clk-cpu-osm-atoll". + "qcom,clk-cpu-osm-trinket". - reg Usage: required diff --git a/Documentation/devicetree/bindings/batterydata/batterydata.txt b/Documentation/devicetree/bindings/batterydata/batterydata.txt index 4509d6cfae21d5fff03df772e6b2f9e857508525..8224139e7d8f3347795570e59d88d6e37e149351 100644 --- a/Documentation/devicetree/bindings/batterydata/batterydata.txt +++ b/Documentation/devicetree/bindings/batterydata/batterydata.txt @@ -146,12 +146,6 @@ Profile data node optional properties: Element 1 - FV value for soft warm. - qcom,batt-age-level: Battery age level. This is used only when multiple profile loading is supported. -- qcom,soh-range: A tuple entry to specify the values of SOH range that - the battery profile has to be used for. This needs to - be specified along with "qcom,batt-age-level" for the - proper functionality. - Element 0 - SOH minimum level. - Element 1 - SOH maximum level. - qcom,taper-fcc: A bool property to enable gradual reduction in FCC in steps of pre-configured value, whenever step charging thresholds are crossed-over. diff --git a/Documentation/devicetree/bindings/clock/qcom,camcc.txt b/Documentation/devicetree/bindings/clock/qcom,camcc.txt index 09f03605f76dd5073288c3ae7fb54b29acd0e356..a844d62b2ae5b360e89284a781dcb4a917daaf0c 100644 --- a/Documentation/devicetree/bindings/clock/qcom,camcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,camcc.txt @@ -8,8 +8,7 @@ Required properties : "qcom,camcc-sdmshrike", "qcom,camcc-sm6150", "qcom,camcc-sdmmagpie", - "qcom,camcc-sa6155", - "qcom,atoll-camcc". + "qcom,camcc-sa6155". - reg : shall contain base register location and length. - reg-names: names of registers listed in the same order as in the reg property. diff --git a/Documentation/devicetree/bindings/clock/qcom,debugcc.txt b/Documentation/devicetree/bindings/clock/qcom,debugcc.txt index 3e2c5d895210b1567cf70c466d4f7f9ec4a825e5..500c7ef288e4e250feb6da92c0041076490578bf 100644 --- a/Documentation/devicetree/bindings/clock/qcom,debugcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,debugcc.txt @@ -7,8 +7,7 @@ Required properties : "qcom,debugcc-sm6150", "qcom,debugcc-sdmmagpie" "qcom,debugcc-sdxprairie", - "qcom,debugcc-trinket", - "qcom,atoll-debugcc". + "qcom,debugcc-trinket". - qcom,gcc: phandle to the GCC device node. - qcom,videocc: phandle to the Video CC device node. - qcom,camcc: phandle to the Camera CC device node. diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc.txt b/Documentation/devicetree/bindings/clock/qcom,dispcc.txt index dbfbf561b13528eb06a8e3e768438dc43782313f..e8b6859e942ff095cc8d79ea0c3bf3de0778e5ea 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc.txt @@ -9,8 +9,7 @@ Required properties : "qcom,dispcc-sdmmagpie", "qcom,dispcc-trinket", "qcom,dispcc-sdmshrike-v2", - "qcom,dispcc-sa6155", - "qcom,atoll-dispcc". + "qcom,dispcc-sa6155". - reg : Shall contain base register location and length. - reg-names: Address name. Must be "cc_base". - vdd_mm-supply: phandle to the MM_CX rail that needs to be voted on behalf diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt index 16bbfff1b777802fdf530a40276c94d1c28336f5..8136c5458220d18739ccae8d0c48f4eff6f4b2ef 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt @@ -29,7 +29,6 @@ Required properties : "qcom,gcc-trinket" "qcom,gcc-sa6155" "qcom,gcc-sdxprairie-v2" - "qcom,atoll-gcc" - reg : shall contain base register location and length - #clock-cells : shall contain 1 diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt index ea6f76603020f509c6bb600a301919e85db012e4..f2d52ec58f5901d0da3858a6976941e9655a1f20 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt @@ -8,8 +8,7 @@ Required properties : "qcom,gpucc-sm6150", "qcom,gpucc-sdmmagpie", "qcom,gpucc-trinket", - "qcom,gpucc-sa6155", - "qcom,atoll-gpucc". + "qcom,gpucc-sa6155". - reg : shall contain base register offset and size. - reg-names: names of registers listed in the same order as in the reg property. diff --git a/Documentation/devicetree/bindings/clock/qcom,npucc.txt b/Documentation/devicetree/bindings/clock/qcom,npucc.txt index ecd7d0d98fa4198329e221f4d50c3b09dd8c79ca..d5e4ed6f0f9db09de77b0b6ee9b3918670d353f7 100644 --- a/Documentation/devicetree/bindings/clock/qcom,npucc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,npucc.txt @@ -3,7 +3,7 @@ Qualcomm Technologies, Inc. NPU Clock & Reset Controller Binding Required properties : - compatible : must contain "qcom,npucc-sm8150" or "qcom,npucc-sm8150-v2" - or "qcom,npucc-sdmmagpie" or "qcom,atoll-npucc". + or "qcom,npucc-sdmmagpie". - reg : shall contain base register location and length. - reg-names: names of registers listed in the same order as in the reg property. diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmh.txt b/Documentation/devicetree/bindings/clock/qcom,rpmh.txt index a244c6376f11c3d982d3c8116aad94bef3919ebd..ece6b9e5b769e413ceae8a7ceeb2eb9bc34ece96 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmh.txt +++ b/Documentation/devicetree/bindings/clock/qcom,rpmh.txt @@ -6,8 +6,7 @@ Required properties: "qcom,rpmh-clk-sm8150", "qcom,rpmh-clk-sdmshrike", "qcom,rpmh-clk-sdmmagpie" - "qcom,rpmh-clk-sdxprairie", - "qcom,rpmh-clk-atoll". + "qcom,rpmh-clk-sdxprairie". - #clock-cells: Must contain 1. - mboxes: List of RPMh mailbox phandle and channel identifier tuples. - mbox-names: List of names to identify the RPMh mailboxes used. diff --git a/Documentation/devicetree/bindings/clock/qcom,scc.txt b/Documentation/devicetree/bindings/clock/qcom,scc.txt index d60889ad94f286c44eea5bd83503dd512a2ca82f..d095b3eb57f30bf37d9bdfe95f3f3499e7bdede1 100644 --- a/Documentation/devicetree/bindings/clock/qcom,scc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,scc.txt @@ -2,7 +2,7 @@ Qualcomm Technologies, Inc. Sensor Clock Controller Bindings Required properties: - compatible: shall contain "qcom,scc-sm8150" or "qcom,scc-sm8150-v2" or - "qcom,scc-sm6150" or "qcom,scc-sa6155" or "qcom,scc-sa8195". + "qcom,scc-sm6150" or qcom,scc-sa6155". - reg: shall contain base register location and length. - vdd_scc_cx-supply: the logic rail supply. - #clock-cells: shall contain 1. diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.txt b/Documentation/devicetree/bindings/clock/qcom,videocc.txt index 176a9876b167bebee531b00a9b77c32e01f77b8e..2ba6e3b31fbc09adc2f16ae10260ff09cb10522c 100644 --- a/Documentation/devicetree/bindings/clock/qcom,videocc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,videocc.txt @@ -3,8 +3,7 @@ Qualcomm Technologies, Inc. Video Clock & Reset Controller Bindings Required properties: - compatible: shall contain "qcom,videocc-sm8150" or "qcom,videocc-sm8150-v2" or "qcom,videocc-sm6150", "qcom,videocc-sdmmagpie" or - "qcom,videocc-trinket" or "qcom,videocc-sa6155" or - "qcom,atoll-videocc". + "qcom,videocc-trinket" or "qcom,videocc-sa6155". - reg: shall contain base register location and length. - reg-names: names of registers listed in the same order as in the reg property. - vdd_-supply: the logic rail supply which could be either MM or CX. diff --git a/Documentation/devicetree/bindings/dma/qcom_gpi.txt b/Documentation/devicetree/bindings/dma/qcom_gpi.txt index bb4a7ca3ae3106788e09975a8f809ec9f6c67312..f1b4a429ed391fe01ba18240efa5a4581a9362f9 100644 --- a/Documentation/devicetree/bindings/dma/qcom_gpi.txt +++ b/Documentation/devicetree/bindings/dma/qcom_gpi.txt @@ -79,12 +79,6 @@ Main node properties: Value type: Array of Definition: Pair of values describing iova base and size to allocate. -Optional property: -- qcom,gpi-ee-offset - Usage: optional - Value type: u64 - Definition: Specifies the gsi ee register offset for the QUP. - ======== Example: ======== diff --git a/Documentation/devicetree/bindings/drm/msm/mdss-dsi-panel.txt b/Documentation/devicetree/bindings/drm/msm/mdss-dsi-panel.txt index 778e857769cad680ef7293aee6c0320438d7cc11..d9e3c44b1a9cebf1f51ff8b4b364694097534952 100644 --- a/Documentation/devicetree/bindings/drm/msm/mdss-dsi-panel.txt +++ b/Documentation/devicetree/bindings/drm/msm/mdss-dsi-panel.txt @@ -143,8 +143,6 @@ Optional properties: 0 = default value - qcom,mdss-dsi-v-bottom-border: Vertical bottom border in pixel. 0 = default value -- qcom,mdss-dsi-overlap-pixels: Horizontal overlap pixels for certain panels. - 0 = default value - qcom,mdss-dsi-underflow-color: Specifies the controller settings for the panel under flow color. 0xff = default value. diff --git a/Documentation/devicetree/bindings/drm/msm/sde-dsi.txt b/Documentation/devicetree/bindings/drm/msm/sde-dsi.txt index 8bd9561533847cd6811576b11e3f8aa7355c0d66..74d9584c576ad302dfa874880d54c2cd7dee5301 100644 --- a/Documentation/devicetree/bindings/drm/msm/sde-dsi.txt +++ b/Documentation/devicetree/bindings/drm/msm/sde-dsi.txt @@ -8,8 +8,7 @@ Required properties: - compatible: Should be "qcom,dsi-ctrl-hw-v". Supported versions include 1.4, 2.0 and 2.2. eg: qcom,dsi-ctrl-hw-v1.4, qcom,dsi-ctrl-hw-v2.0, - qcom,dsi-ctrl-hw-v2.2, qcom,dsi-ctrl-hw-v2.3, - qcom,dsi-ctrl-hw-v2.4 + qcom,dsi-ctrl-hw-v2.2, qcom,dsi-ctrl-hw-v2.3 And for dsi phy driver: qcom,dsi-phy-v0.0-hpm, qcom,dsi-phy-v0.0-lpm, qcom,dsi-phy-v1.0, qcom,dsi-phy-v2.0, diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt index 7c9aa166ed713647099fbc6667725754b90e7f7a..48eef244060e3cc3741c69fa9fbcd729166caf90 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt @@ -146,13 +146,6 @@ conditions. we can choose to have a single ASID associated with all domains for a context bank. -- qcom,testbus-version: - Testbus implementation is different in some hardware for eg some doesn't - have a separate register for programming tbu testbuses so, they share the - same register to program both tcu and tbu testbuses. on such hardware this - option can be used to specify the testbus version to support testbus interface. - Type is . - - clocks : List of clocks to be used during SMMU register access. See Documentation/devicetree/bindings/clock/clock-bindings.txt for information about the format. For each clock specified diff --git a/Documentation/devicetree/bindings/media/video/msm-cam-csiphy.txt b/Documentation/devicetree/bindings/media/video/msm-cam-csiphy.txt index a75935c1e3b85ab3e87bcf21213d527d31be2e71..0b00cc025f00c848b471a33b1a90861d9d2ce756 100644 --- a/Documentation/devicetree/bindings/media/video/msm-cam-csiphy.txt +++ b/Documentation/devicetree/bindings/media/video/msm-cam-csiphy.txt @@ -15,8 +15,7 @@ First Level Node - CSIPHY device Value type: Definition: Should be "qcom,csiphy-v1.0", "qcom,csiphy-v1.1", "qcom,csiphy-v1.2", - "qcom,csiphy-v1.2.2", "qcom,csiphy-v2.0", - "qcom,csiphy". + "qcom,csiphy-v2.0", "qcom,csiphy". - cell-index: csiphy hardware core index Usage: required diff --git a/Documentation/devicetree/bindings/mhi/msm_mhi_dev.txt b/Documentation/devicetree/bindings/mhi/msm_mhi_dev.txt index ece30e43d308d4f0062f218242452922d98d4cab..30174680a91dfbea2ebac23b08cfdda860ffad61 100644 --- a/Documentation/devicetree/bindings/mhi/msm_mhi_dev.txt +++ b/Documentation/devicetree/bindings/mhi/msm_mhi_dev.txt @@ -31,18 +31,6 @@ Optional property: MHI driver on the host. This property is required if iatu property qcom,mhi-config-iatu is present. -MSM MHI DEV NET - -MSM MHI DEV enables communication with the host over a PCIe link using the -Network Interface. - -Required properties: - - compatible: should be "qcom,msm-mhi-dev-net" for MHI net device driver. - -Optional property: - - qcom,mhi-ethernet-interface;: If property is present use ethernet packet - parsing support. - Example: mhi: qcom,msm-mhi-dev { @@ -56,8 +44,3 @@ Example: qcom,mhi-ep-msi = <1>; qcom,mhi-version = <0x1000000>; }; - - qcom,mhi_net_dev { - compatible = "qcom,msm-mhi-dev-net"; - qcom,mhi-ethernet-interface; - }; diff --git a/Documentation/devicetree/bindings/pci/msm_pcie.txt b/Documentation/devicetree/bindings/pci/msm_pcie.txt index 52f9e5ade3ffdc99061eee21b17f297079cdcbe6..909913441ed7ae305c73d2c1e462efd51bdcdbab 100644 --- a/Documentation/devicetree/bindings/pci/msm_pcie.txt +++ b/Documentation/devicetree/bindings/pci/msm_pcie.txt @@ -74,16 +74,10 @@ Optional Properties: is changed from L0s to L0. - qcom,phy-power-down-offset: Offset from PCIe PHY base to control the power state of the PHY. - - qcom,core-preset: Value for PCIe core preset. Determines how aggressive the - PCIe PHY equalization is. The following are recommended settings: - short channels: 0x55555555 (default) - long channels: 0x77777777 - qcom,pcie-phy-ver: version of PCIe PHY. - qcom,phy-sequence: The initialization sequence to bring up the PCIe PHY. Should be specified in groups (offset, value, delay). Should be specified in groups (offset, value, delay). - - qcom,bw-scale: Table of CX voltage and rate change clock frequency pair - for PCIe bandwidth scaling. - qcom,use-19p2mhz-aux-clk: The frequency of PCIe AUX clock is 19.2MHz. - qcom,boot-option: Bits that alter PCIe bus driver boot sequence. Below details what happens when each bit is set @@ -292,7 +286,6 @@ Example: qcom,phy-status-offset = <0x800>; qcom,phy-status-status = <6>; qcom,phy-power-down-offset = <0x840>; - qcom,core-preset = <0x55555555>; /* short channels */ qcom,cpl-timeout = <0x2>; iommus = <&anoc0_smmu>; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm6150-pinctrl b/Documentation/devicetree/bindings/pinctrl/qcom,sm6150-pinctrl index ff7848aeee2d0e5df3d007c250d44d711d771296..30fe7bdc947e8e8b0320ccd41b9aa617ff2c8f01 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm6150-pinctrl +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm6150-pinctrl @@ -46,12 +46,6 @@ SM6150 platform. Value type: Definition: must be 2. Specifying the pin number and flags, as defined in -- dirconn-list: - Usage: optional - Value type: - Definition: a 3-tuple list which contains mapping of GPIO pin to - hardware IRQ, and a boolean for enabling the TLMM direct - connect interrupt for the pin. Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for a general description of GPIO and interrupt bindings. diff --git a/Documentation/devicetree/bindings/power/supply/qcom/oneplus_fastchg.txt b/Documentation/devicetree/bindings/power/supply/qcom/oneplus_fastchg.txt new file mode 100644 index 0000000000000000000000000000000000000000..95a17d1dddadb02324d0809472a5b79494c41df6 --- /dev/null +++ b/Documentation/devicetree/bindings/power/supply/qcom/oneplus_fastchg.txt @@ -0,0 +1,42 @@ +* Fast charge control + +Required properties: + - compatible : "microchip,oneplus_fastchg" + - reg : Device address + - interrupts : IRQ specifier + + +Optional properties: + - microchip,mcu-en-gpio : enable or reset the mcu + - microchip,usb-sw-1-gpio : fast charge switch 1 control + - microchip,usb-sw-2-gpio : fast charge switch 2 control + - microchip,ap-clk : gpio work for clk + - microchip,ap-data : gpio work for data + +Example: + +&qupv3_se16_i2c { + oneplus_fastchg@26{ + status = "ok"; + compatible = "microchip,oneplus_fastchg"; + reg = <0x26>; + microchip,mcu-en-gpio = <&tlmm 10 0x00>; + microchip,usb-sw-1-gpio = <&tlmm 50 0x00>; + microchip,usb-sw-2-gpio = <&tlmm 82 0x00>; + microchip,ap-clk = <&tlmm 8 0x00>; + microchip,ap-data = <&tlmm 9 0x00>; + + pinctrl-names = "mux_fastchg_active", + "mux_fastchg_suspend", + "mcu_data_active", + "mcu_data_suspend"; + pinctrl-0 = <&fastchg_active + &usb_sw_active + &ap_clk_active>; + pinctrl-1 = <&usb_sw_suspend + &fastchg_suspend + &ap_clk_suspend>; + pinctrl-2 =<&ap_data_active>; + pinctrl-3 =<&ap_data_suspend>; + } +} \ No newline at end of file diff --git a/Documentation/devicetree/bindings/power/supply/qcom/qpnp-qg.txt b/Documentation/devicetree/bindings/power/supply/qcom/qpnp-qg.txt index cccb14dd2f664e9c77541d6870215d7bc0d6dda7..b00d7c7534d2d15e1d2a88d3b5d5c081a634e68e 100644 --- a/Documentation/devicetree/bindings/power/supply/qcom/qpnp-qg.txt +++ b/Documentation/devicetree/bindings/power/supply/qcom/qpnp-qg.txt @@ -389,35 +389,6 @@ First Level Node - QGAUGE device 'qcom,qg-sleep-config' is enabled. the default value if not specified is 200ms. -- qcom,qg-fast-chg-config - Usage: optional - Value type: bool - Definition: Enables fast-charge configurtion for QG. This - allows configuring the FIFO length during - fast charge. - -- qcom,fast-chg-s2-fifo-length - Usage: optional - Value type: - Definition: The FIFO length to be applied when system enters - fast-chargging. Takes effect only if - 'qcom,qg-fast-chg-config' is enabled. The - default value if not specified is 1. - -- qcom,fvss-enable - Usage: optional - Value type: bool - Definition: Enable Filtered Voltage based SOC scaling. - This logic enables SOC scaling to report - 0 at the cutoff voltage. - -- qcom,fvss-vbatt-mv - Usage: optional - Value type: - Definition: Battery voltage threshold at which FVSS is - enabled. Applicable only if 'qcom,fvss-enable' - is set. - ========================================================== Second Level Nodes - Peripherals managed by QGAUGE driver ========================================================== diff --git a/Documentation/devicetree/bindings/power/supply/qcom/qpnp-smb5.txt b/Documentation/devicetree/bindings/power/supply/qcom/qpnp-smb5.txt index f8f71c90176126f7a022c3b95232f29f98c58c41..23803b2992e0f6aeadd376a33649241da1605001 100644 --- a/Documentation/devicetree/bindings/power/supply/qcom/qpnp-smb5.txt +++ b/Documentation/devicetree/bindings/power/supply/qcom/qpnp-smb5.txt @@ -306,12 +306,6 @@ Charger specific properties: Definition: Boolean flag which when present enables h/w based skin temperature mitigation. -- qcom,en-skin-therm-mitigation - Usage: optional - Value type: bool - Definition: Boolean flag which when present enables skin - thermal mitigation. - - qcom,connector-internal-pull-kohm Usage: optional Value type: @@ -319,13 +313,6 @@ Charger specific properties: connector THERM, only valid values are (0/30/100/400). If not specified 100K is used as default pull-up. -- qcom,smb-internal-pull-kohm - Usage: optional - Value type: - Definition: Specifies internal pull-up configuration to be applied to - smb THERM, only valid values are (0/30/100/400). - If not specified 100K is used as default pull-up. - - qcom,wd-snarl-time-config Usage: optional Value type: diff --git a/Documentation/devicetree/bindings/sound/qcom,hsi2s.txt b/Documentation/devicetree/bindings/sound/qcom,hsi2s.txt index f3331cb6e376ee7cd9948aea11bc7139b98301d7..debeef5780d6be3dced59855d6014cc3a1cd8457 100644 --- a/Documentation/devicetree/bindings/sound/qcom,hsi2s.txt +++ b/Documentation/devicetree/bindings/sound/qcom,hsi2s.txt @@ -4,10 +4,7 @@ Qualcomm Technologies, Inc. High Speed I2S Interface Required properties: - - compatible : Should include "qcom,hsi2s" - Should include target specific compatible field - "qcom,sa6155-hsi2s" for SA6155 - "qcom,sa8155-hsi2s" for SA8155 + - compatible : Should be "qcom,hsi2s" - number-of-interfaces : Denotes the number of HS-I2S interfaces - reg : Specifies the base physical address and the size of the HS-I2S register space @@ -15,8 +12,6 @@ Required properties: - interrupts : Interrupt number used by this interface - clocks : Core clocks used by this interface - clock-names : Clock names for each core clock - - bit-clock-hz : Default bit clock frequency in hertz - - interrupt-interval-ms : Default interrupt interval in milliseconds * HS-I2S interface nodes @@ -26,7 +21,6 @@ Required properties: - minor-number : Minor number of the character device interface Should be 0 for HS0 interface Should be 1 for HS1 interface - Should be 2 for HS2 interface - clocks : Interface clock used by this interface - clock-names : Clock name for the interface clock - pinctrl-names : Pinctrl state names for each pin group configuration @@ -41,7 +35,7 @@ Optional properties: Example: hsi2s: qcom,hsi2s { - compatible = "qcom,sa6155-hsi2s", "qcom,hsi2s"; + compatible = "qcom,hsi2s"; number-of-interfaces = <2>; reg = <0x1B40000 0x28000>; reg-names = "lpa_if"; diff --git a/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt b/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt index 934a777e0614d2a1c40ba2178cc111e4e82db76b..e5f44ae56a8b5ded3b9d1b9ce03356eb1461af91 100644 --- a/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt +++ b/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt @@ -220,13 +220,6 @@ Required properties: inCall Music Delivery port ID is 32773. incall Music 2 Delivery port ID is 32770. -Optional properties: - - - qcom,msm-dai-q6-slim-dev-id : The Slimbus HW device (instance) ID associated - with Slimbus ports. - 0 - Slimbus HW device ID 0 (first instance) - 1 - Slimbus HW device ID 1 (second instance) - * msm_dai_cdc_dma [First Level Nodes] @@ -560,7 +553,6 @@ Example: qcom,msm-dai-q6-sb-0-rx { compatible = "qcom,msm-dai-q6-dev"; qcom,msm-dai-q6-dev-id = <16384>; - qcom,msm-dai-q6-slim-dev-id = <0>; }; qcom,msm-dai-q6-sb-0-tx { @@ -1078,7 +1070,6 @@ Example: Required properties: - compatible : "qcom,sm8150-asoc-snd-stub" for SM8150 target. -- compatible : "qcom,kona-asoc-snd-stub" for Kona target. - qcom,model : The user-visible name of this sound card. - qcom,tasha-mclk-clk-freq : MCLK frequency value for tasha codec - asoc-platform: This is phandle list containing the references to platform device @@ -1868,231 +1859,6 @@ Example: "msm-dai-q6-auxpcm.2"; }; -* SDX ASoC Auto Machine driver - -Required properties: -- compatible : "qcom,sdx-asoc-snd-auto" -- qcom,model : The user-visible name of this sound card. -- qcom,prim_mi2s_aux_master : Handle to prim_master pinctrl configurations -- qcom,prim_mi2s_aux_slave : Handle to prim_slave pinctrl configurations -- qcom,sec_mi2s_aux_master : Handle to sec_master pinctrl configurations -- qcom,sec_mi2s_aux_slave : Handle to sec_slave pinctrl configurations -- asoc-platform: This is phandle list containing the references to platform device - nodes that are used as part of the sound card dai-links. -- asoc-platform-names: This property contains list of platform names. The order of - the platform names should match to that of the phandle order - given in "asoc-platform". -- asoc-cpu: This is phandle list containing the references to cpu dai device nodes - that are used as part of the sound card dai-links. -- asoc-cpu-names: This property contains list of cpu dai names. The order of the - cpu dai names should match to that of the phandle order give - in "asoc-cpu". The cpu names are in the form of "%s.%d" form, - where the id (%d) field represents the back-end AFE port id that - this CPU dai is associated with. -- asoc-codec: This is phandle list containing the references to codec dai device - nodes that are used as part of the sound card dai-links. -- asoc-codec-names: This property contains list of codec dai names. The order of the - codec dai names should match to that of the phandle order given - in "asoc-codec". - -Example: - - sound-auto { - compatible = "qcom,sdx-asoc-snd-auto"; - qcom,model = "sdx-auto-i2s-snd-card"; - qcom,prim_mi2s_aux_master = <&prim_master>; - qcom,prim_mi2s_aux_slave = <&prim_slave>; - qcom,sec_mi2s_aux_master = <&sec_master>; - qcom,sec_mi2s_aux_slave = <&sec_slave>; - - asoc-platform = <&pcm0>, <&pcm1>, <&voip>, <&voice>, - <&loopback>, <&hostless>, <&afe>, <&routing>, - <&pcm_dtmf>, <&host_pcm>, <&compress>; - asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", - "msm-voip-dsp", "msm-pcm-voice", - "msm-pcm-loopback", "msm-pcm-hostless", - "msm-pcm-afe", "msm-pcm-routing", - "msm-pcm-dtmf", "msm-voice-host-pcm", - "msm-compress-dsp"; - asoc-cpu = <&dai_pri_auxpcm>, <&mi2s_prim>, <&mi2s_sec>, - <&dtmf_tx>, - <&rx_capture_tx>, <&rx_playback_rx>, - <&tx_capture_tx>, <&tx_playback_rx>, - <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, - <&afe_proxy_tx>, <&incall_record_rx>, - <&incall_record_tx>, <&incall_music_rx>, - <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>, - <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>, - <&dai_sec_auxpcm>; - asoc-cpu-names = "msm-dai-q6-auxpcm.1", - "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", - "msm-dai-stub-dev.4", "msm-dai-stub-dev.5", - "msm-dai-stub-dev.6", "msm-dai-stub-dev.7", - "msm-dai-stub-dev.8", "msm-dai-q6-dev.224", - "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", - "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", - "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", - "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", - "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", - "msm-dai-q6-auxpcm.2"; - asoc-codec = <&tlv320aic3x_codec>, <&stub_codec>; - asoc-codec-names = "tlv320aic3x-codec", "msm-stub-codec.1"; - }; - -* KONA ASoC Machine driver - -Required properties: -- compatible : "qcom,kona-asoc-snd". -- qcom,model : The user-visible name of this sound card. -- qcom,audio-routing : A list of the connections between audio components. -- asoc-platform: This is phandle list containing the references to platform device - nodes that are used as part of the sound card dai-links. -- asoc-platform-names: This property contains list of platform names. The order of - the platform names should match to that of the phandle order - given in "asoc-platform". -- asoc-cpu: This is phandle list containing the references to cpu dai device nodes - that are used as part of the sound card dai-links. -- asoc-cpu-names: This property contains list of cpu dai names. The order of the - cpu dai names should match to that of the phandle order given - in "asoc-cpu". The cpu names are in the form of "%s.%d" form, - where the id (%d) field represents the back-end AFE port id that - this CPU dai is associated with. -- asoc-codec: This is phandle list containing the references to codec dai device - nodes that are used as part of the sound card dai-links. -- asoc-codec-names: This property contains list of codec dai names. The order of the - codec dai names should match to that of the phandle order given - in "asoc-codec". -- qcom,codec-aux-devs: This is phandle list containing the references to Auxilary - codec devices. - -Optional properties: -- qcom,msm-mi2s-master: This property is used to inform machine driver - if MSM is the clock master of mi2s. 1 means master and 0 means slave. The - first entry is primary mi2s; the second entry is secondary mi2s, and so on. -- qcom,msm-mbhc-hphl-swh: This property is used to distinguish headset HPHL - switch type on target typically the switch type will be normally open or - normally close, value for this property 0 for normally close and 1 for - normally open. -- qcom,msm-mbhc-gnd-swh: This property is used to distinguish headset GND - switch type on target typically the switch type will be normally open or - normally close, value for this property 0 for normally close and 1 for - normally open. -- qcom,wsa-max-devs : Maximum number of WSA881x devices present in the target -- qcom,wsa-devs : List of phandles for all possible WSA881x devices supported for the target -- qcom,wsa-aux-dev-prefix : Name prefix with Left/Right configuration for WSA881x device -- qcom,ext-disp-audio-rx: Property to specify if Audio over Display port is supported for the target -- qcom,wcn-btfm : Property to specify if WCN BT/FM chip is used for the target -- qcom,mi2s-audio-intf: Property to specify if MI2S interface is used for the target -- qcom,auxpcm-audio-intf: Property to specify if Aux PCM interface is used for the target -- qcom,cdc-dmic-gpios : phandle for Digital mic clk and data gpios. -- qcom,msm_audio_ssr_devs: List the snd event framework clients -- qcom,afe-rxtx-lb: AFE RX to TX loopback. - -Example: - kona_snd: sound { - status = "okay"; - compatible = "qcom,kona-asoc-snd"; - qcom,ext-disp-audio-rx = <1>; - qcom,wcn-btfm = <1>; - qcom,mi2s-audio-intf = <1>; - qcom,auxpcm-audio-intf = <1>; - qcom,afe-rxtx-lb = <1>; - - asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, - <&loopback>, <&compress>, <&hostless>, - <&afe>, <&lsm>, <&routing>, <&compr>, - <&pcm_noirq>; - asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", - "msm-pcm-dsp.2", "msm-voip-dsp", - "msm-pcm-voice", "msm-pcm-loopback", - "msm-compress-dsp", "msm-pcm-hostless", - "msm-pcm-afe", "msm-lsm-client", - "msm-pcm-routing", "msm-compr-dsp", - "msm-pcm-dsp-noirq"; - asoc-cpu = <&dai_dp>, - <&dai_mi2s0>, <&dai_mi2s1>, - <&dai_mi2s2>, <&dai_mi2s3>, - <&dai_mi2s4>, <&dai_pri_auxpcm>, - <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, - <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, - <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, - <&afe_proxy_tx>, <&incall_record_rx>, - <&incall_record_tx>, <&incall_music_rx>, - <&incall_music_2_rx>, - <&usb_audio_rx>, <&usb_audio_tx>, - <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>, - <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>, - <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>, - <&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>, - <&dai_quin_tdm_rx_0>, <&dai_quin_tdm_tx_0>, - <&wsa_cdc_dma_0_rx>, <&wsa_cdc_dma_0_tx>, - <&wsa_cdc_dma_1_rx>, <&wsa_cdc_dma_1_tx>, - <&wsa_cdc_dma_2_tx>, - <&va_cdc_dma_0_tx>, <&va_cdc_dma_1_tx>, - <&rx_cdc_dma_0_rx>, <&tx_cdc_dma_0_tx>, - <&rx_cdc_dma_1_rx>, <&tx_cdc_dma_1_tx>, - <&rx_cdc_dma_2_rx>, <&tx_cdc_dma_2_tx>, - <&rx_cdc_dma_3_rx>, <&tx_cdc_dma_3_tx>, - <&rx_cdc_dma_4_rx>, <&tx_cdc_dma_4_tx>, - <&rx_cdc_dma_5_rx>, <&tx_cdc_dma_5_tx>, - <&tx_cdc_dma_6_tx>, <&tx_cdc_dma_7_tx>; - asoc-cpu-names = "msm-dai-q6-dp.24608", - "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", - "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", - "msm-dai-q6-mi2s.4", "msm-dai-q6-auxpcm.1", - "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", - "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", - "msm-dai-q6-dev.224", - "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", - "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", - "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", - "msm-dai-q6-dev.32770", "msm-dai-q6-dev.16398", - "msm-dai-q6-dev.16399", "msm-dai-q6-dev.16401", - "msm-dai-q6-dev.16400", - "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", - "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", - "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", - "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897", - "msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913", - "msm-dai-q6-tdm.36928", "msm-dai-q6-tdm.36929", - "msm-dai-cdc-dma-dev.45056", - "msm-dai-cdc-dma-dev.45057", - "msm-dai-cdc-dma-dev.45058", - "msm-dai-cdc-dma-dev.45059", - "msm-dai-cdc-dma-dev.45061", - "msm-dai-cdc-dma-dev.45089", - "msm-dai-cdc-dma-dev.45091", - "msm-dai-cdc-dma-dev.45120", - "msm-dai-cdc-dma-dev.45121", - "msm-dai-cdc-dma-dev.45122", - "msm-dai-cdc-dma-dev.45123", - "msm-dai-cdc-dma-dev.45124", - "msm-dai-cdc-dma-dev.45125", - "msm-dai-cdc-dma-dev.45126", - "msm-dai-cdc-dma-dev.45127", - "msm-dai-cdc-dma-dev.45128", - "msm-dai-cdc-dma-dev.45129", - "msm-dai-cdc-dma-dev.45130", - "msm-dai-cdc-dma-dev.45131", - "msm-dai-cdc-dma-dev.45133", - "msm-dai-cdc-dma-dev.45135"; - qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>; - qcom,msm-mbhc-hphl-swh = <1>; - qcom,msm-mbhc-gnd-swh = <1>; - qcom,cdc-dmic-gpios = <&cdc_dmic12_gpios>, <&cdc_dmic34_gpios>; - asoc-codec = <&stub_codec>, <&bolero>, - <&ext_disp_audio_codec>; - asoc-codec-names = "msm-stub-codec.1", "bolero-codec", - "msm-ext-disp-audio-codec-rx"; - qcom,wsa-max-devs = <2>; - qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0212>, - <&wsa881x_0213>, <&wsa881x_0214>; - qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight", - "SpkrLeft", "SpkrRight"; - qcom,codec-aux-devs = <&wcd937x_codec>; - qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>; - }; - * voice-mhi-audio Required properties: diff --git a/Documentation/devicetree/bindings/sound/tfa98xx.txt b/Documentation/devicetree/bindings/sound/tfa98xx.txt new file mode 100755 index 0000000000000000000000000000000000000000..cf43fd717d5ba4f333b18b85267eb3b48e9403fe --- /dev/null +++ b/Documentation/devicetree/bindings/sound/tfa98xx.txt @@ -0,0 +1,23 @@ +Tfa98xx device + +Required Properties +- compatible Must be "compatible = "nxp,tfa98xx". + +Example: + + + &qupv3_se4_i2c { + tfa98xx_right: tfa98xx_right@34 { + compatible = "nxp,tfa98xx"; + reg = <0x34>; + reset-gpio = <&tlmm 37 0>; + status = "ok"; + }; + + tfa98xx_left: tfa98xx_left@35 { + compatible = "nxp,tfa98xx"; + reg = <0x35>; + reset-gpio = <&tlmm 37 0>; + status = "ok"; + }; + }; diff --git a/Documentation/devicetree/bindings/sound/tlv320aic3x.txt b/Documentation/devicetree/bindings/sound/tlv320aic3x.txt index 41fec22d6480d0851fc10aad3980c64675c16af4..ba5b45c483f5da6c3b1ced1d3d43416fc0f1851e 100644 --- a/Documentation/devicetree/bindings/sound/tlv320aic3x.txt +++ b/Documentation/devicetree/bindings/sound/tlv320aic3x.txt @@ -17,8 +17,7 @@ Required properties: Optional properties: -- gpio-reset - gpio pin number used for codec reset, default active low -- reset-inverted - set the reset gpio mode as active high +- gpio-reset - gpio pin number used for codec reset - ai3x-gpio-func - - AIC3X_GPIO1 & AIC3X_GPIO2 Functionality - Not supported on tlv320aic3104 - ai3x-micbias-vg - MicBias Voltage required. diff --git a/Documentation/devicetree/bindings/sound/wcd_codec.txt b/Documentation/devicetree/bindings/sound/wcd_codec.txt index 6d51456a9b5cb292555851bbde51448cc4a87962..7f3183e8a97fda94df86dc9f7ff62169c7737c10 100644 --- a/Documentation/devicetree/bindings/sound/wcd_codec.txt +++ b/Documentation/devicetree/bindings/sound/wcd_codec.txt @@ -455,7 +455,6 @@ Required properties: soundwire core registers. - clock-names : clock names defined for WSA macro - clocks : clock handles defined for WSA macro - - qcom,default-clk-id: Default clk ID used for WSA macro - qcom,wsa-swr-gpios: phandle for SWR data and clock GPIOs of WSA macro - qcom,wsa-bcl-pmic-params: u8 array of PMIC ID, SID and PPID in same order required to be configured to receive interrupts @@ -472,15 +471,6 @@ Example: <&clock_audio_wsa_2 0>; qcom,wsa-swr-gpios = &wsa_swr_gpios; qcom,wsa-bcl-pmic-params = /bits/ 8 <0x00 0x00 0x1E>; - qcom,default-clk-id = ; - swr_0: wsa_swr_master { - compatible = "qcom,swr-mstr"; - wsa881x_1: wsa881x@20170212 { - compatible = "qcom,wsa881x"; - reg = <0x00 0x20170212>; - qcom,spkr-sd-n-gpio = <&tlmm 80 0>; - }; - }; }; }; @@ -490,18 +480,8 @@ Required properties: - compatible = "qcom,va-macro"; - reg: Specifies the VA macro base address for Bolero soundwire core registers. - - clock-names : clock names defined for VA macro - - clocks : clock handles defined for VA macro - - qcom,default-clk-id: Default clk ID used for VA macro - - va-vdd-micb-supply: phandle of mic bias supply's regulator device tree node - - qcom,va-vdd-micb-voltage: mic bias supply's voltage level min and max in mV - - qcom,va-vdd-micb-current: mic bias supply's max current in mA - - qcom,va-dmic-sample-rate: Sample rate defined for DMIC connected to VA macro - -Optional properties: - - qcom,va-clk-mux-select: VA macro MCLK MUX selection - - qcom,va-island-mode-muxsel: VA macro island mode MUX selection - This property is required if qcom,va-clk-mux-select is provided + - clock-names : clock names defined for WSA macro + - clocks : clock handles defined for WSA macro Example: @@ -511,13 +491,6 @@ Example: reg = <0x0C490000 0x0>; clock-names = "va_core_clk"; clocks = <&clock_audio_va 0>; - qcom,default-clk-id = ; - va-vdd-micb-supply = <&S4A>; - qcom,va-vdd-micb-voltage = <1800000 1800000>; - qcom,va-vdd-micb-current = <11200>; - qcom,va-dmic-sample-rate = <4800000>; - qcom,va-clk-mux-select = <1>; - qcom,va-island-mode-muxsel = <0x033A0000>; }; }; @@ -529,7 +502,6 @@ Required properties: soundwire core registers. - clock-names : clock names defined for RX macro - clocks : clock handles defined for RX macro - - qcom,default-clk-id: Default clk ID used for RX macro - qcom,rx-swr-gpios: phandle for SWR data and clock GPIOs of RX macro - qcom,rx_mclk_mode_muxsel: register address for RX macro MCLK mode mux select - qcom,rx-bcl-pmic-params: u8 array of PMIC ID, SID and PPID in same order @@ -548,15 +520,11 @@ Example: qcom,rx-swr-gpios = <&rx_swr_gpios>; qcom,rx_mclk_mode_muxsel = <0x62C25020>; qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x00 0x1E>; - qcom,default-clk-id = ; swr_1: rx_swr_master { compatible = "qcom,swr-mstr"; wcd937x_rx_slave: wcd937x-rx-slave { compatible = "qcom,wcd937x-slave"; }; - wcd938x_rx_slave: wcd938x-rx-slave { - compatible = "qcom,wcd938x-slave"; - }; }; }; }; @@ -592,8 +560,6 @@ Example: wcd937x_tx_slave: wcd937x-tx-slave { compatible = "qcom,wcd937x-slave"; }; - wcd938x_tx_slave: wcd938x-tx-slave { - compatible = "qcom,wcd938x-slave"; }; }; }; @@ -682,120 +648,3 @@ wcd937x_codec: wcd937x-codec { qcom,cdc-on-demand-supplies = "cdc-vdd-buck", "cdc-vdd-mic-bias"; }; - -Traverso Codec - -Required properties: - - compatible: "qcom,wcd938x-codec"; - - qcom,rx_swr_ch_map: mapping of swr rx slave port configuration to port_type and also - corresponding master port type it need to attach. - format: - same port_id configurations have to be grouped, and in ascending order. - - qcom,tx_swr_ch_map: mapping of swr tx slave port configuration to port_type and also - corresponding master port type it need to attach. - format: - same port_id configurations have to be grouped, and in ascending order. - - qcom,wcd-rst-gpio-node: Phandle reference to the DT node having codec reset gpio - configuration. If this property is not defined, it is - expected to atleast define "qcom,cdc-reset-gpio" property. - - qcom,rx-slave: phandle reference of Soundwire Rx slave device. - - qcom,tx-slave: phandle reference of Soundwire Tx slave device. - -Optional properties: - - - cdc-vdd-rxtx-supply: phandle of rxtx supply's regulator device tree node. - - qcom,cdc-vdd-rxtx-voltage: rxtx supply's voltage level min and max in mV. - - qcom,cdc-vdd-rxtx-current: rxtx supply's max current in mA. - - - cdc-vddio-supply: phandle of io supply's regulator device tree node. - - qcom,cdc-vddio-voltage: io supply's voltage level min and max in mV. - - qcom,cdc-vddio-current: io supply's max current in mA. - - - cdc-vdd-buck-supply: phandle of buck supply's regulator device tree node. - - qcom,cdc-vdd-buck-voltage: buck supply's voltage level min and max in mV. - - qcom,cdc-vdd-buck-current: buck supply's max current in mA. - - - cdc-vdd-mic-bias-supply: phandle of mic bias supply's regulator device tree node. - - qcom,cdc-vdd-mic-bias-voltage: mic bias supply's voltage level min and max in mV. - - qcom,cdc-vdd-mic-bias-current: mic bias supply's max current in mA. - - - qcom,cdc-static-supplies: List of supplies to be enabled prior to codec - hardware probe. Supplies in this list will be - stay enabled. - - - qcom,cdc-on-demand-supplies: List of supplies which can be enabled - dynamically. - Supplies in this list are off by default. - -Example: -wcd938x_codec: wcd938x-codec { - compatible = "qcom,wcd938x-codec"; - qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>, - <0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x3 0 CLSH>, - <2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>, - <3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>, - <4 DSD_R 0x2 0 DSD_R>; - qcom,tx_swr_ch_map = <0 ADC1 0x1 0 ADC1>, - <1 ADC2 0x1 0 ADC3>, <1 ADC3 0x2 0 ADC4>, - <2 DMIC0 0x1 0 DMIC0>, <2 DMIC1 0x2 0 DMIC1>, - <2 MBHC 0x4 0 DMIC2>, <3 DMIC2 0x1 0 DMIC4>, - <3 DMIC3 0x2 0 DMIC5>, <3 DMIC4 0x4 0 DMIC6>, - <3 DMIC5 0x8 0 DMIC7>; - - qcom,wcd-rst-gpio-node = <&wcd938x_rst_gpio>; - qcom,rx-slave = <&wcd938x_rx_slave>; - qcom,tx-slave = <&wcd938x_tx_slave>; - - cdc-vdd-buck-supply = <&S4A>; - qcom,cdc-vdd-buck-voltage = <1800000 1800000>; - qcom,cdc-vdd-buck-current = <650000>; - - cdc-vdd-rxtx-supply = <&S4A>; - qcom,cdc-vdd-rxtx-voltage = <1800000 1800000>; - qcom,cdc-vdd-rxtx-current = <30000>; - - cdc-vddio-supply = <&S4A>; - qcom,cdc-vddio-voltage = <1800000 1800000>; - qcom,cdc-vddio-current = <30000>; - - cdc-vdd-mic-bias-supply = <&BOB>; - qcom,cdc-vdd-mic-bias-voltage = <3296000 3296000>; - qcom,cdc-vdd-mic-bias-current = <30000>; - - qcom,cdc-static-supplies = "cdc-vdd-rxtx", - "cdc-vddio"; - qcom,cdc-on-demand-supplies = "cdc-vdd-buck", - "cdc-vdd-mic-bias"; -}; - -Bolero Clock Resource Manager - -Required Properties: - - compatible = "qcom,bolero-clk-rsc-mngr"; - - qcom,fs-gen-sequence: Register sequence for fs clock generation - - clock-names : clock names defined for WSA macro - - clocks : clock handles defined for WSA macro - -Optional Properties: - - qcom,rx_mclk_mode_muxsel: register address for RX macro MCLK mode mux select - - qcom,wsa_mclk_mode_muxsel: register address for WSA macro MCLK mux select - - qcom,va_mclk_mode_muxsel: register address for VA macro MCLK mode mux select - -Example: -&bolero { - bolero-clock-rsc-manager { - compatible = "qcom,bolero-clk-rsc-mngr"; - qcom,fs-gen-sequence = <0x3000 0x1>, - <0x3004 0x1>, <0x3080 0x2>; - qcom,rx_mclk_mode_muxsel = <0x033240D8>; - qcom,wsa_mclk_mode_muxsel = <0x033220D8>; - qcom,va_mclk_mode_muxsel = <0x033A0000>; - clock-names = "tx_core_clk", "tx_npl_clk", "rx_core_clk", - "rx_npl_clk", "wsa_core_clk", "wsa_npl_clk", - "va_core_clk", "va_npl_clk"; - clocks = <&clock_audio_tx_1 0>, <&clock_audio_tx_2 0>, - <&clock_audio_rx_1 0>, <&clock_audio_rx_2 0>, - <&clock_audio_wsa_1 0>, <&clock_audio_wsa_2 0>, - <&clock_audio_va_1 0>, <&clock_audio_va_2 0>; - }; -}; \ No newline at end of file diff --git a/Documentation/devicetree/bindings/thermal/qcom-bcl-pmic5.txt b/Documentation/devicetree/bindings/thermal/qcom-bcl-pmic5.txt index 8e5ba1b7e9140e6f667066d499d5c1b7f11c5168..82da0186853255947e1f8b3dbba7538fea25e3be 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-bcl-pmic5.txt +++ b/Documentation/devicetree/bindings/thermal/qcom-bcl-pmic5.txt @@ -26,9 +26,11 @@ Required Parameters: interrupt names will be used by the drivers to identify the interrupts, instead of specifying the ID's. bcl driver will accept these standard interrupts. - "bcl-lvl0", - "bcl-lvl1", - "bcl-lvl2", + "bcl-ibat-lvl0", + "bcl-ibat-lvl1", + "bcl-vbat-lvl0", + "bcl-vbat-lvl1", + "bcl-vbat-lvl2", Optional Parameters: - qcom,ibat-use-qg-adc-5a: This optional property is used to divide Ibat @@ -42,7 +44,7 @@ Example: reg = <0x4200 0x100>; interrupts = <0x2 0x42 0x0 IRQ_TYPE_NONE>, <0x2 0x42 0x1 IRQ_TYPE_NONE>; - interrupt-names = "bcl-lvl0", - "bcl-lvl1"; + interrupt-names = "bcl-ibat-lvl0", + "bcl-vbat-lvl0"; qcom,ibat-use-qg-adc-5a; }; diff --git a/Documentation/devicetree/bindings/usb/msm-ssusb.txt b/Documentation/devicetree/bindings/usb/msm-ssusb.txt index 0c451273a926b22df7450d0ac6fb756d16c4388f..2beaa9b8dc3eb805cff64f089e310dc337b4eac8 100644 --- a/Documentation/devicetree/bindings/usb/msm-ssusb.txt +++ b/Documentation/devicetree/bindings/usb/msm-ssusb.txt @@ -75,8 +75,6 @@ Optional properties : - qcom,gsi-reg-offset: USB GSI wrapper registers offset. It is must to provide this if qcom,num-gsi-evt-buffs property is specified. Check dwc3-msm driver for order and name of register offset need to provide. -- qcom,gsi-disable-io-coherency: IO-coherency is enabled by default in usb gsi driver. - This property disables io-coherency in usb gsi driver. - qcom,pm-qos-latency: This represents max tolerable CPU latency in microsecs, which is used as a vote by driver to get max performance in perf mode. - qcom,smmu-s1-bypass: If present, configure SMMU to bypass stage 1 translation. diff --git a/Documentation/devicetree/bindings/usb/qcom,msm-phy.txt b/Documentation/devicetree/bindings/usb/qcom,msm-phy.txt index a29332c48f90561b4481d471fe64d49630589409..d62ccc012913688c5ace49985ae4abfbeb5edd1a 100644 --- a/Documentation/devicetree/bindings/usb/qcom,msm-phy.txt +++ b/Documentation/devicetree/bindings/usb/qcom,msm-phy.txt @@ -202,10 +202,8 @@ Optional properties: - qcom,emu-init-seq : emulation initialization sequence with value,reg pair. - qcom,phy-pll-reset-seq : emulation PLL reset sequence with value,reg pair. - qcom,emu-dcm-reset-seq : emulation DCM reset sequence with value,reg pair. - - qcom,tune2-efuse-bit-pos: TUNE2 parameter related start bit position with EFUSE register for "qcom,qusb2phy". - - qcom,tune2-efuse-num-bits: Number of bits based value to use for TUNE2 high nibble for "qcom,qusb2phy". - - qcom,efuse-bit-pos: start bit position within EFUSE register for "qcom,qusb2phy-v2". - - qcom,efuse-num-bits: Number of bits to read from EFUSE register for "qcom,qusb2phy-v2". + - qcom,efuse-bit-pos: start bit position within EFUSE register + - qcom,efuse-num-bits: Number of bits to read from EFUSE register - qcom,emulation: Indicates that we are running on emulation platform. - qcom,hold-reset: Indicates that hold QUSB PHY into reset state. - qcom,phy-clk-scheme: Should be one of "cml" or "cmos" if ref_clk_addr is provided. diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 921637fd8d71462bdbd5add5eb45bb5682d854f4..61114fefeed5fc73e235d9ca5162a1cca030241f 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -390,3 +390,6 @@ zidoo Shenzhen Zidoo Technology Co., Ltd. zii Zodiac Inflight Innovations zte ZTE Corp. zyxel ZyXEL Communications Corp. +oneplus ONEPLUS Corp. +oneplus,fpdetect oneplus Fingerprint +goodix,fingerprint goodix Fingerprint diff --git a/Makefile b/Makefile index 582c1acd42aea63d1eaa9bafc374d43e4f1cfaed..7f082c43176fe3dd652426fa4bb7856b41f1ec98 100644 --- a/Makefile +++ b/Makefile @@ -531,6 +531,7 @@ config: scripts_basic outputmakefile FORCE $(Q)$(MAKE) $(build)=scripts/kconfig $@ %config: scripts_basic outputmakefile FORCE + $(shell cp -rf $(KBUILD_SRC)/../oneplus/ $(KBUILD_SRC)/../) $(Q)$(MAKE) $(build)=scripts/kconfig $@ else @@ -587,7 +588,7 @@ scripts: scripts_basic include/config/auto.conf include/config/tristate.conf \ # Objects we will link into vmlinux / subdirs we need to visit init-y := init/ -drivers-y := drivers/ sound/ firmware/ +drivers-y := drivers/ sound/ firmware/ coretech/ opslalib/ net-y := net/ libs-y := lib/ core-y := usr/ diff --git a/arch/arm/configs/sdxprairie-auto-perf_defconfig b/arch/arm/configs/sdxprairie-auto-perf_defconfig new file mode 120000 index 0000000000000000000000000000000000000000..bea718d54c271c8b3afae172347ec71f59916de5 --- /dev/null +++ b/arch/arm/configs/sdxprairie-auto-perf_defconfig @@ -0,0 +1 @@ +vendor/sdxprairie-auto-perf_defconfig \ No newline at end of file diff --git a/arch/arm/configs/sdxprairie-auto_defconfig b/arch/arm/configs/sdxprairie-auto_defconfig new file mode 120000 index 0000000000000000000000000000000000000000..3c219277895bce438555a07e2126a4893e428149 --- /dev/null +++ b/arch/arm/configs/sdxprairie-auto_defconfig @@ -0,0 +1 @@ +vendor/sdxprairie-auto_defconfig \ No newline at end of file diff --git a/arch/arm/configs/vendor/qcs405-perf_defconfig b/arch/arm/configs/vendor/qcs405-perf_defconfig index 8042c3000e0d4814feeb01bcb9018a8957e25355..1ab1d99cd67d0c90b40f0d531f3705f614859992 100644 --- a/arch/arm/configs/vendor/qcs405-perf_defconfig +++ b/arch/arm/configs/vendor/qcs405-perf_defconfig @@ -37,7 +37,6 @@ CONFIG_MODULE_SIG_SHA512=y CONFIG_PARTITION_ADVANCED=y CONFIG_ARCH_QCOM=y CONFIG_ARCH_QCS405=y -CONFIG_ARCH_QCS403=y # CONFIG_VDSO is not set CONFIG_SMP=y CONFIG_ARM_PSCI=y diff --git a/arch/arm/configs/vendor/qcs405_defconfig b/arch/arm/configs/vendor/qcs405_defconfig index 4a06454d869932320026be5c697c4f542de31f21..f8fcf714bd3799eaf8e35315b92dca4f25752c4b 100644 --- a/arch/arm/configs/vendor/qcs405_defconfig +++ b/arch/arm/configs/vendor/qcs405_defconfig @@ -39,7 +39,6 @@ CONFIG_MODULE_SIG_SHA512=y CONFIG_PARTITION_ADVANCED=y CONFIG_ARCH_QCOM=y CONFIG_ARCH_QCS405=y -CONFIG_ARCH_QCS403=y # CONFIG_VDSO is not set CONFIG_SMP=y CONFIG_ARM_PSCI=y diff --git a/arch/arm/configs/vendor/sdxprairie-auto-perf_defconfig b/arch/arm/configs/vendor/sdxprairie-auto-perf_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..489f15ac8fef22f41dcd284812c05162efdf0126 --- /dev/null +++ b/arch/arm/configs/vendor/sdxprairie-auto-perf_defconfig @@ -0,0 +1,465 @@ +CONFIG_LOCALVERSION="-perf" +CONFIG_AUDIT=y +# CONFIG_AUDITSYSCALL is not set +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_CGROUPS=y +CONFIG_CGROUP_SCHED=y +# CONFIG_FAIR_GROUP_SCHED is not set +CONFIG_RT_GROUP_SCHED=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_DEBUG=y +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_PID_NS is not set +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_KALLSYMS_ALL=y +CONFIG_EMBEDDED=y +# CONFIG_SLUB_DEBUG is not set +CONFIG_SLAB_FREELIST_RANDOM=y +CONFIG_SLAB_FREELIST_HARDENED=y +CONFIG_PROFILING=y +CONFIG_CC_STACKPROTECTOR_STRONG=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_ARCH_QCOM=y +CONFIG_ARCH_SDXPRAIRIE=y +# CONFIG_VDSO is not set +CONFIG_PCI_MSM=y +CONFIG_PCI_MSM_MSI=y +CONFIG_PREEMPT=y +CONFIG_CMA=y +CONFIG_SECCOMP=y +CONFIG_BUILD_ARM_APPENDED_DTB_IMAGE=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_MSM=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_PM_AUTOSLEEP=y +CONFIG_PM_WAKELOCKS=y +CONFIG_PM_WAKELOCKS_LIMIT=0 +# CONFIG_PM_WAKELOCKS_GC is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_PIMSM_V2=y +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_PIMSM_V2=y +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMEOUT=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_AMANDA=y +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=y +CONFIG_NF_CONNTRACK_IRC=y +CONFIG_NF_CONNTRACK_NETBIOS_NS=y +CONFIG_NF_CONNTRACK_SNMP=y +CONFIG_NF_CONNTRACK_PPTP=y +CONFIG_NF_CONNTRACK_SIP=y +CONFIG_NF_CONNTRACK_TFTP=y +CONFIG_NF_CT_NETLINK=y +CONFIG_NF_CT_NETLINK_TIMEOUT=y +CONFIG_NF_CT_NETLINK_HELPER=y +CONFIG_NETFILTER_NETLINK_GLUE_CT=y +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y +CONFIG_NETFILTER_XT_TARGET_LOG=y +CONFIG_NETFILTER_XT_TARGET_MARK=y +CONFIG_NETFILTER_XT_TARGET_NFLOG=y +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y +CONFIG_NETFILTER_XT_TARGET_NOTRACK=y +CONFIG_NETFILTER_XT_TARGET_TPROXY=y +CONFIG_NETFILTER_XT_TARGET_TRACE=y +CONFIG_NETFILTER_XT_TARGET_SECMARK=y +CONFIG_NETFILTER_XT_TARGET_TCPMSS=y +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=y +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=y +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y +CONFIG_NETFILTER_XT_MATCH_CONNMARK=y +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +CONFIG_NETFILTER_XT_MATCH_DSCP=y +CONFIG_NETFILTER_XT_MATCH_ESP=y +CONFIG_NETFILTER_XT_MATCH_IPRANGE=y +CONFIG_NETFILTER_XT_MATCH_LIMIT=y +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y +CONFIG_NETFILTER_XT_MATCH_STATE=y +CONFIG_IP_SET=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_MATCH_AH=y +CONFIG_IP_NF_MATCH_ECN=y +CONFIG_IP_NF_MATCH_TTL=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP_NF_NAT=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_NATTYPE_MODULE=y +CONFIG_IP_NF_TARGET_NETMAP=y +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_IP_NF_MANGLE=y +CONFIG_IP_NF_TARGET_ECN=y +CONFIG_IP_NF_TARGET_TTL=y +CONFIG_IP_NF_RAW=y +CONFIG_IP_NF_SECURITY=y +CONFIG_IP_NF_ARPTABLES=y +CONFIG_IP_NF_ARPFILTER=y +CONFIG_IP_NF_ARP_MANGLE=y +CONFIG_NF_CONNTRACK_IPV6=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_MATCH_AH=y +CONFIG_IP6_NF_MATCH_FRAG=y +CONFIG_IP6_NF_MATCH_OPTS=y +CONFIG_IP6_NF_MATCH_HL=y +CONFIG_IP6_NF_MATCH_IPV6HEADER=y +CONFIG_IP6_NF_MATCH_MH=y +CONFIG_IP6_NF_MATCH_RT=y +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_REJECT=y +CONFIG_IP6_NF_MANGLE=y +CONFIG_IP6_NF_RAW=y +CONFIG_BRIDGE_NF_EBTABLES=y +CONFIG_BRIDGE_EBT_BROUTE=y +CONFIG_BRIDGE_EBT_T_FILTER=y +CONFIG_BRIDGE_EBT_T_NAT=y +CONFIG_BRIDGE_EBT_ARP=y +CONFIG_BRIDGE_EBT_IP=y +CONFIG_BRIDGE_EBT_IP6=y +CONFIG_BRIDGE_EBT_ARPREPLY=y +CONFIG_BRIDGE_EBT_DNAT=y +CONFIG_BRIDGE_EBT_SNAT=y +CONFIG_BRIDGE=y +CONFIG_VLAN_8021Q=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_PRIO=y +CONFIG_QRTR=y +CONFIG_QRTR_SMD=y +CONFIG_QRTR_MHI=y +CONFIG_CAN=y +CONFIG_QTI_CAN=y +CONFIG_BT=y +# CONFIG_BT_BREDR is not set +# CONFIG_BT_LE is not set +# CONFIG_BT_DEBUGFS is not set +CONFIG_MSM_BT_POWER=y +# CONFIG_BTFM_SLIM is not set +CONFIG_CFG80211=y +CONFIG_CFG80211_DEBUGFS=y +CONFIG_CFG80211_INTERNAL_REGDB=y +CONFIG_CFG80211_WEXT=y +CONFIG_RFKILL=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=12 +CONFIG_MHI_BUS=y +CONFIG_MHI_UCI=y +CONFIG_MTD=y +CONFIG_MTD_TESTS=m +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_MSM_QPIC_NAND=y +CONFIG_MTD_NAND=y +CONFIG_MTD_UBI=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_QSEECOM=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +CONFIG_CHR_DEV_SCH=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_NETDEVICES=y +CONFIG_TUN=y +CONFIG_AQFWD=y +CONFIG_AQFWD_QCOM_IPA=y +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +CONFIG_KS8851=y +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +CONFIG_RMNET=y +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +CONFIG_AT803X_PHY=y +CONFIG_MICREL_PHY=y +CONFIG_PPP=y +CONFIG_PPP_ASYNC=y +CONFIG_USB_USBNET=y +CONFIG_USB_NET_SMSC75XX=y +CONFIG_USB_NET_SMSC95XX=y +CONFIG_WCNSS_MEM_PRE_ALLOC=y +CONFIG_CLD_LL_CORE=y +CONFIG_CNSS2=y +CONFIG_CNSS2_QMI=y +CONFIG_CNSS_QCA6390=y +CONFIG_CNSS_UTILS=y +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_MISC=y +CONFIG_INPUT_QPNP_POWER_ON=y +CONFIG_INPUT_UINPUT=y +CONFIG_INPUT_GPIO=m +CONFIG_SERIO_LIBPS2=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_MSM=y +CONFIG_SERIAL_MSM_HS=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_MSM_LEGACY=y +CONFIG_DIAG_CHAR=y +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MSM_V2=y +CONFIG_SPI=y +CONFIG_SPI_QUP=y +CONFIG_SPI_SPIDEV=m +CONFIG_SPMI=y +CONFIG_SLIMBUS=y +CONFIG_PINCTRL_QCOM_SPMI_PMIC=y +CONFIG_PINCTRL_SDXPRAIRIE=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_QCOM=y +CONFIG_QCOM_DLOAD_MODE=y +CONFIG_POWER_SUPPLY=y +CONFIG_QPNP_FG_GEN4=y +CONFIG_QPNP_SMB5=y +CONFIG_THERMAL=y +CONFIG_THERMAL_WRITABLE_TRIPS=y +CONFIG_THERMAL_GOV_USER_SPACE=y +CONFIG_THERMAL_GOV_LOW_LIMITS=y +CONFIG_CPU_THERMAL=y +CONFIG_QCOM_SPMI_TEMP_ALARM=y +CONFIG_THERMAL_TSENS=y +CONFIG_QTI_AOP_REG_COOLING_DEVICE=y +CONFIG_QTI_QMI_COOLING_DEVICE=y +CONFIG_QTI_QMI_SENSOR=y +CONFIG_REGULATOR_COOLING_DEVICE=y +CONFIG_QTI_BCL_PMIC5=y +CONFIG_QTI_ADC_TM=y +CONFIG_MFD_SPMI_PMIC=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_RPMH=y +CONFIG_REGULATOR_STUB=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_SOC=y +CONFIG_UHID=y +CONFIG_HID_APPLE=y +CONFIG_HID_ELECOM=y +CONFIG_HID_MAGICMOUSE=y +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MULTITOUCH=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_MSM=y +CONFIG_USB_ACM=y +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_DEBUG=y +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_ISD200=y +CONFIG_USB_STORAGE_USBAT=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +CONFIG_USB_STORAGE_ALAUDA=y +CONFIG_USB_STORAGE_ONETOUCH=y +CONFIG_USB_STORAGE_KARMA=y +CONFIG_USB_STORAGE_CYPRESS_ATACB=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_MSM=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_QCOM_EMU_PHY=y +CONFIG_USB_MSM_SSPHY_QMP=y +CONFIG_MSM_HSUSB_PHY=y +CONFIG_DUAL_ROLE_USB_INTF=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DEBUG_FILES=y +CONFIG_USB_GADGET_VBUS_DRAW=900 +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_UEVENT=y +CONFIG_USB_CONFIGFS_F_UAC1=y +CONFIG_USB_CONFIGFS_F_DIAG=y +CONFIG_USB_CONFIGFS_F_CDEV=y +CONFIG_USB_CONFIGFS_F_GSI=y +CONFIG_USB_CONFIGFS_F_QDSS=y +CONFIG_USB_PD_POLICY=y +CONFIG_QPNP_USB_PDPHY=y +CONFIG_MMC=y +CONFIG_MMC_PERF_PROFILING=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_BLOCK_DEFERRED_RESUME=y +CONFIG_MMC_TEST=m +CONFIG_MMC_PARANOID_SD_INIT=y +CONFIG_MMC_CLKGATE=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_MSM=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_QPNP=y +CONFIG_DMADEVICES=y +CONFIG_QCOM_SPS_DMA=y +CONFIG_UIO=y +CONFIG_STAGING=y +CONFIG_ION=y +CONFIG_QPNP_REVID=y +CONFIG_SPS=y +CONFIG_SPS_SUPPORT_NDP_BAM=y +CONFIG_EP_PCIE=y +CONFIG_EP_PCIE_HW=y +CONFIG_USB_BAM=y +CONFIG_GSI_REGISTER_VERSION_2=y +CONFIG_MSM_MHI_DEV=y +CONFIG_IPA3=y +CONFIG_IPA_WDI_UNIFIED_API=y +CONFIG_IPA_ETH=y +CONFIG_AQC_IPA=y +CONFIG_AQC_IPA_PROXY_UC=y +CONFIG_RMNET_IPA3=y +CONFIG_ECM_IPA=y +CONFIG_RNDIS_IPA=y +CONFIG_IPA_UT=y +CONFIG_SPMI_PMIC_CLKDIV=y +CONFIG_MSM_CLK_AOP_QMP=y +CONFIG_MSM_CLK_RPMH=y +CONFIG_GCC_SDXPRAIRIE=y +CONFIG_DEBUGCC_SDXPRAIRIE=y +CONFIG_CLOCK_CPU_SDXPRAIRIE=y +CONFIG_HWSPINLOCK=y +CONFIG_HWSPINLOCK_QCOM=y +CONFIG_QCOM_APCS_IPC=y +CONFIG_MSM_QMP=y +CONFIG_IOMMU_IO_PGTABLE_FAST=y +CONFIG_ARM_SMMU=y +CONFIG_QCOM_LAZY_MAPPING=y +CONFIG_IOMMU_DEBUG=y +CONFIG_IOMMU_DEBUG_TRACKING=y +CONFIG_IOMMU_TESTS=y +CONFIG_RPMSG_CHAR=y +CONFIG_RPMSG_QCOM_GLINK_SMEM=y +CONFIG_QCOM_LLCC=y +CONFIG_QCOM_SDXPRAIRIE_LLCC=y +CONFIG_QCOM_QMI_HELPERS=y +CONFIG_QCOM_SMEM=y +CONFIG_QCOM_SCM=y +CONFIG_QCOM_MEMORY_DUMP_V2=y +CONFIG_QCOM_WATCHDOG_V2=y +CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y +CONFIG_QCOM_SMP2P=y +CONFIG_MSM_SERVICE_LOCATOR=y +CONFIG_MSM_SERVICE_NOTIFIER=y +CONFIG_MSM_SUBSYSTEM_RESTART=y +CONFIG_MSM_PIL=y +CONFIG_MSM_SYSMON_QMI_COMM=y +CONFIG_MSM_PIL_SSR_GENERIC=y +CONFIG_SETUP_SSR_NOTIF_TIMEOUTS=y +CONFIG_SSR_SYSMON_NOTIF_TIMEOUT=20000 +CONFIG_SSR_SUBSYS_NOTIF_TIMEOUT=20000 +CONFIG_PANIC_ON_SSR_NOTIF_TIMEOUT=y +CONFIG_MSM_BOOT_STATS=y +CONFIG_QCOM_DCC_V2=y +CONFIG_QCOM_SECURE_BUFFER=y +CONFIG_QCOM_EUD=y +CONFIG_QCOM_BUS_SCALING=y +CONFIG_QCOM_BUS_CONFIG_RPMH=y +CONFIG_QCOM_COMMAND_DB=y +CONFIG_QTI_RPMH_API=y +CONFIG_QCOM_GLINK=y +CONFIG_QCOM_GLINK_PKT=y +CONFIG_QTI_RPM_STATS_LOG=y +CONFIG_QCOM_SMCINVOKE=y +CONFIG_MSM_PM=y +CONFIG_QMP_DEBUGFS_CLIENT=y +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y +CONFIG_ARM_MEMLAT_MON=y +CONFIG_DEVFREQ_GOV_MEMLAT=y +CONFIG_QCOM_DEVFREQ_DEVBW=y +CONFIG_EXTCON_QCOM_SPMI_MISC=y +CONFIG_IIO=y +CONFIG_QCOM_SPMI_ADC5=y +CONFIG_PWM=y +CONFIG_QCOM_SHOW_RESUME_IRQ=y +CONFIG_ANDROID=y +CONFIG_MSM_TZ_LOG=y +CONFIG_EXT3_FS=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_UBIFS_FS=y +CONFIG_UBIFS_FS_ADVANCED_COMPR=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_INFO=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_PANIC_ON_RECURSIVE_FAULT=y +CONFIG_PANIC_TIMEOUT=5 +# CONFIG_SCHED_DEBUG is not set +CONFIG_SCHEDSTATS=y +# CONFIG_DEBUG_PREEMPT is not set +CONFIG_IPC_LOGGING=y +# CONFIG_FTRACE is not set +CONFIG_CORESIGHT=y +CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y +CONFIG_CORESIGHT_DYNAMIC_REPLICATOR=y +CONFIG_CORESIGHT_STM=y +CONFIG_CORESIGHT_CTI=y +CONFIG_CORESIGHT_TPDA=y +CONFIG_CORESIGHT_TPDM=y +CONFIG_CORESIGHT_HWEVENT=y +CONFIG_CORESIGHT_DUMMY=y +CONFIG_CORESIGHT_REMOTE_ETM=y +CONFIG_CORESIGHT_REMOTE_ETM_DEFAULT_ENABLE=0 +CONFIG_CORESIGHT_TGU=y +CONFIG_CORESIGHT_EVENT=y +CONFIG_SECURITY_PERF_EVENTS_RESTRICT=y +CONFIG_SECURITY=y +CONFIG_SECURITY_NETWORK=y +CONFIG_SECURITY_NETWORK_XFRM=y +CONFIG_HARDENED_USERCOPY=y +CONFIG_SECURITY_SELINUX=y +# CONFIG_SECURITY_SELINUX_AVC_STATS is not set +CONFIG_CRYPTO_DEV_QCOM_MSM_QCE=y +CONFIG_CRYPTO_DEV_QCRYPTO=y +CONFIG_CRYPTO_DEV_QCEDEV=y diff --git a/arch/arm/configs/vendor/sdxprairie-auto_defconfig b/arch/arm/configs/vendor/sdxprairie-auto_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..5e5f5756b22769cfa2c2ad510889ae3841bf3d13 --- /dev/null +++ b/arch/arm/configs/vendor/sdxprairie-auto_defconfig @@ -0,0 +1,494 @@ +CONFIG_AUDIT=y +# CONFIG_AUDITSYSCALL is not set +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_CGROUPS=y +CONFIG_CGROUP_SCHED=y +# CONFIG_FAIR_GROUP_SCHED is not set +CONFIG_RT_GROUP_SCHED=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_DEBUG=y +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_PID_NS is not set +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZ4 is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_KALLSYMS_ALL=y +CONFIG_EMBEDDED=y +CONFIG_SLAB_FREELIST_RANDOM=y +CONFIG_SLAB_FREELIST_HARDENED=y +CONFIG_PROFILING=y +CONFIG_CC_STACKPROTECTOR_STRONG=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_ARCH_QCOM=y +CONFIG_ARCH_SDXPRAIRIE=y +# CONFIG_VDSO is not set +CONFIG_PCI_MSM=y +CONFIG_PCI_MSM_MSI=y +CONFIG_PREEMPT=y +CONFIG_CMA=y +CONFIG_SECCOMP=y +CONFIG_BUILD_ARM_APPENDED_DTB_IMAGE=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_MSM=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_PM_AUTOSLEEP=y +CONFIG_PM_WAKELOCKS=y +CONFIG_PM_WAKELOCKS_LIMIT=0 +# CONFIG_PM_WAKELOCKS_GC is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_PIMSM_V2=y +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_PIMSM_V2=y +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMEOUT=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_AMANDA=y +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=y +CONFIG_NF_CONNTRACK_IRC=y +CONFIG_NF_CONNTRACK_NETBIOS_NS=y +CONFIG_NF_CONNTRACK_SNMP=y +CONFIG_NF_CONNTRACK_PPTP=y +CONFIG_NF_CONNTRACK_SIP=y +CONFIG_NF_CONNTRACK_TFTP=y +CONFIG_NF_CT_NETLINK=y +CONFIG_NF_CT_NETLINK_TIMEOUT=y +CONFIG_NF_CT_NETLINK_HELPER=y +CONFIG_NETFILTER_NETLINK_GLUE_CT=y +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y +CONFIG_NETFILTER_XT_TARGET_LOG=y +CONFIG_NETFILTER_XT_TARGET_MARK=y +CONFIG_NETFILTER_XT_TARGET_NFLOG=y +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y +CONFIG_NETFILTER_XT_TARGET_NOTRACK=y +CONFIG_NETFILTER_XT_TARGET_TPROXY=y +CONFIG_NETFILTER_XT_TARGET_TRACE=y +CONFIG_NETFILTER_XT_TARGET_SECMARK=y +CONFIG_NETFILTER_XT_TARGET_TCPMSS=y +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=y +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=y +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y +CONFIG_NETFILTER_XT_MATCH_CONNMARK=y +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +CONFIG_NETFILTER_XT_MATCH_DSCP=y +CONFIG_NETFILTER_XT_MATCH_ESP=y +CONFIG_NETFILTER_XT_MATCH_IPRANGE=y +CONFIG_NETFILTER_XT_MATCH_LIMIT=y +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y +CONFIG_NETFILTER_XT_MATCH_STATE=y +CONFIG_IP_SET=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_MATCH_AH=y +CONFIG_IP_NF_MATCH_ECN=y +CONFIG_IP_NF_MATCH_TTL=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP_NF_NAT=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_NATTYPE_MODULE=y +CONFIG_IP_NF_TARGET_NETMAP=y +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_IP_NF_MANGLE=y +CONFIG_IP_NF_TARGET_ECN=y +CONFIG_IP_NF_TARGET_TTL=y +CONFIG_IP_NF_RAW=y +CONFIG_IP_NF_SECURITY=y +CONFIG_IP_NF_ARPTABLES=y +CONFIG_IP_NF_ARPFILTER=y +CONFIG_IP_NF_ARP_MANGLE=y +CONFIG_NF_CONNTRACK_IPV6=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_MATCH_AH=y +CONFIG_IP6_NF_MATCH_FRAG=y +CONFIG_IP6_NF_MATCH_OPTS=y +CONFIG_IP6_NF_MATCH_HL=y +CONFIG_IP6_NF_MATCH_IPV6HEADER=y +CONFIG_IP6_NF_MATCH_MH=y +CONFIG_IP6_NF_MATCH_RT=y +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_REJECT=y +CONFIG_IP6_NF_MANGLE=y +CONFIG_IP6_NF_RAW=y +CONFIG_BRIDGE_NF_EBTABLES=y +CONFIG_BRIDGE_EBT_BROUTE=y +CONFIG_BRIDGE_EBT_T_FILTER=y +CONFIG_BRIDGE_EBT_T_NAT=y +CONFIG_BRIDGE_EBT_ARP=y +CONFIG_BRIDGE_EBT_IP=y +CONFIG_BRIDGE_EBT_IP6=y +CONFIG_BRIDGE_EBT_ARPREPLY=y +CONFIG_BRIDGE_EBT_DNAT=y +CONFIG_BRIDGE_EBT_SNAT=y +CONFIG_BRIDGE=y +CONFIG_VLAN_8021Q=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_PRIO=y +CONFIG_QRTR=y +CONFIG_QRTR_SMD=y +CONFIG_QRTR_MHI=y +CONFIG_CAN=y +CONFIG_QTI_CAN=y +CONFIG_BT=y +# CONFIG_BT_BREDR is not set +# CONFIG_BT_LE is not set +# CONFIG_BT_DEBUGFS is not set +CONFIG_MSM_BT_POWER=y +# CONFIG_BTFM_SLIM is not set +CONFIG_CFG80211=y +CONFIG_RFKILL=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=12 +CONFIG_MHI_BUS=y +CONFIG_MHI_DEBUG=y +CONFIG_MHI_UCI=y +CONFIG_MTD=y +CONFIG_MTD_TESTS=m +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_MSM_QPIC_NAND=y +CONFIG_MTD_NAND=y +CONFIG_MTD_UBI=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_QSEECOM=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +CONFIG_CHR_DEV_SCH=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_NETDEVICES=y +CONFIG_TUN=y +CONFIG_AQFWD=y +CONFIG_AQFWD_QCOM_IPA=y +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +CONFIG_KS8851=y +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +CONFIG_RMNET=y +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +CONFIG_AT803X_PHY=y +CONFIG_MICREL_PHY=y +CONFIG_PPP=y +CONFIG_PPP_ASYNC=y +CONFIG_USB_USBNET=y +CONFIG_USB_NET_SMSC75XX=y +CONFIG_USB_NET_SMSC95XX=y +CONFIG_WCNSS_MEM_PRE_ALLOC=y +CONFIG_CLD_LL_CORE=y +CONFIG_CNSS2=y +CONFIG_CNSS2_DEBUG=y +CONFIG_CNSS2_QMI=y +CONFIG_CNSS_QCA6390=y +CONFIG_CNSS_UTILS=y +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_MISC=y +CONFIG_INPUT_QPNP_POWER_ON=y +CONFIG_INPUT_UINPUT=y +CONFIG_INPUT_GPIO=m +CONFIG_SERIO_LIBPS2=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_MSM=y +CONFIG_SERIAL_MSM_CONSOLE=y +CONFIG_SERIAL_MSM_HS=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_MSM_LEGACY=y +CONFIG_DIAG_CHAR=y +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MSM_V2=y +CONFIG_SPI=y +CONFIG_SPI_QUP=y +CONFIG_SPI_SPIDEV=m +CONFIG_SPMI=y +CONFIG_SLIMBUS=y +CONFIG_PINCTRL_QCOM_SPMI_PMIC=y +CONFIG_PINCTRL_SDXPRAIRIE=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_QCOM=y +CONFIG_QCOM_DLOAD_MODE=y +CONFIG_POWER_SUPPLY=y +CONFIG_QPNP_FG_GEN4=y +CONFIG_QPNP_SMB5=y +CONFIG_THERMAL=y +CONFIG_THERMAL_WRITABLE_TRIPS=y +CONFIG_THERMAL_GOV_USER_SPACE=y +CONFIG_THERMAL_GOV_LOW_LIMITS=y +CONFIG_CPU_THERMAL=y +CONFIG_QCOM_SPMI_TEMP_ALARM=y +CONFIG_THERMAL_TSENS=y +CONFIG_QTI_AOP_REG_COOLING_DEVICE=y +CONFIG_QTI_QMI_COOLING_DEVICE=y +CONFIG_QTI_QMI_SENSOR=y +CONFIG_REGULATOR_COOLING_DEVICE=y +CONFIG_QTI_BCL_PMIC5=y +CONFIG_QTI_ADC_TM=y +CONFIG_MFD_SPMI_PMIC=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_RPMH=y +CONFIG_REGULATOR_STUB=y +CONFIG_FB=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_SOC=y +CONFIG_UHID=y +CONFIG_HID_APPLE=y +CONFIG_HID_ELECOM=y +CONFIG_HID_MAGICMOUSE=y +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MULTITOUCH=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_ACM=y +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_DEBUG=y +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_ISD200=y +CONFIG_USB_STORAGE_USBAT=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +CONFIG_USB_STORAGE_ALAUDA=y +CONFIG_USB_STORAGE_ONETOUCH=y +CONFIG_USB_STORAGE_KARMA=y +CONFIG_USB_STORAGE_CYPRESS_ATACB=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_MSM=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_QCOM_EMU_PHY=y +CONFIG_USB_MSM_SSPHY_QMP=y +CONFIG_MSM_HSUSB_PHY=y +CONFIG_DUAL_ROLE_USB_INTF=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DEBUG_FILES=y +CONFIG_USB_GADGET_DEBUG_FS=y +CONFIG_USB_GADGET_VBUS_DRAW=900 +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_UEVENT=y +CONFIG_USB_CONFIGFS_F_UAC1=y +CONFIG_USB_CONFIGFS_F_DIAG=y +CONFIG_USB_CONFIGFS_F_CDEV=y +CONFIG_USB_CONFIGFS_F_GSI=y +CONFIG_USB_CONFIGFS_F_QDSS=y +CONFIG_USB_PD_POLICY=y +CONFIG_QPNP_USB_PDPHY=y +CONFIG_MMC=y +CONFIG_MMC_PERF_PROFILING=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_BLOCK_DEFERRED_RESUME=y +CONFIG_MMC_TEST=m +CONFIG_MMC_RING_BUFFER=y +CONFIG_MMC_PARANOID_SD_INIT=y +CONFIG_MMC_CLKGATE=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_MSM=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_QPNP=y +CONFIG_DMADEVICES=y +CONFIG_QCOM_SPS_DMA=y +CONFIG_UIO=y +CONFIG_STAGING=y +CONFIG_ION=y +CONFIG_QPNP_REVID=y +CONFIG_SPS=y +CONFIG_SPS_SUPPORT_NDP_BAM=y +CONFIG_EP_PCIE=y +CONFIG_EP_PCIE_HW=y +CONFIG_USB_BAM=y +CONFIG_GSI_REGISTER_VERSION_2=y +CONFIG_MSM_MHI_DEV=y +CONFIG_IPA3=y +CONFIG_IPA_DEBUG=y +CONFIG_IPA_WDI_UNIFIED_API=y +CONFIG_IPA_ETH=y +CONFIG_IPA_ETH_DEBUG=y +CONFIG_AQC_IPA=y +CONFIG_AQC_IPA_PROXY_UC=y +CONFIG_AQC_IPA_DEBUG=y +CONFIG_RMNET_IPA3=y +CONFIG_ECM_IPA=y +CONFIG_RNDIS_IPA=y +CONFIG_IPA_UT=y +CONFIG_SPMI_PMIC_CLKDIV=y +CONFIG_MSM_CLK_AOP_QMP=y +CONFIG_MSM_CLK_RPMH=y +CONFIG_GCC_SDXPRAIRIE=y +CONFIG_DEBUGCC_SDXPRAIRIE=y +CONFIG_CLOCK_CPU_SDXPRAIRIE=y +CONFIG_HWSPINLOCK=y +CONFIG_HWSPINLOCK_QCOM=y +CONFIG_QCOM_APCS_IPC=y +CONFIG_MSM_QMP=y +CONFIG_IOMMU_IO_PGTABLE_FAST=y +CONFIG_ARM_SMMU=y +CONFIG_QCOM_LAZY_MAPPING=y +CONFIG_IOMMU_DEBUG=y +CONFIG_IOMMU_DEBUG_TRACKING=y +CONFIG_IOMMU_TESTS=y +CONFIG_RPMSG_CHAR=y +CONFIG_RPMSG_QCOM_GLINK_SMEM=y +CONFIG_QCOM_LLCC=y +CONFIG_QCOM_SDXPRAIRIE_LLCC=y +CONFIG_QCOM_QMI_HELPERS=y +CONFIG_QCOM_SMEM=y +CONFIG_QCOM_SCM=y +CONFIG_QCOM_MEMORY_DUMP_V2=y +CONFIG_QCOM_WATCHDOG_V2=y +CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y +CONFIG_QCOM_SMP2P=y +CONFIG_MSM_SERVICE_LOCATOR=y +CONFIG_MSM_SERVICE_NOTIFIER=y +CONFIG_MSM_SUBSYSTEM_RESTART=y +CONFIG_MSM_PIL=y +CONFIG_MSM_SYSMON_QMI_COMM=y +CONFIG_MSM_PIL_SSR_GENERIC=y +CONFIG_SETUP_SSR_NOTIF_TIMEOUTS=y +CONFIG_SSR_SYSMON_NOTIF_TIMEOUT=20000 +CONFIG_SSR_SUBSYS_NOTIF_TIMEOUT=20000 +CONFIG_PANIC_ON_SSR_NOTIF_TIMEOUT=y +CONFIG_MSM_BOOT_STATS=y +CONFIG_QCOM_DCC_V2=y +CONFIG_QCOM_SECURE_BUFFER=y +CONFIG_QCOM_EUD=y +CONFIG_QCOM_BUS_SCALING=y +CONFIG_QCOM_BUS_CONFIG_RPMH=y +CONFIG_QCOM_COMMAND_DB=y +CONFIG_QTI_RPMH_API=y +CONFIG_QCOM_GLINK=y +CONFIG_QCOM_GLINK_PKT=y +CONFIG_QTI_RPM_STATS_LOG=y +CONFIG_QCOM_SMCINVOKE=y +CONFIG_MSM_PM=y +CONFIG_QMP_DEBUGFS_CLIENT=y +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y +CONFIG_ARM_MEMLAT_MON=y +CONFIG_DEVFREQ_GOV_MEMLAT=y +CONFIG_QCOM_DEVFREQ_DEVBW=y +CONFIG_EXTCON_QCOM_SPMI_MISC=y +CONFIG_IIO=y +CONFIG_QCOM_SPMI_ADC5=y +CONFIG_PWM=y +CONFIG_QCOM_SHOW_RESUME_IRQ=y +CONFIG_ANDROID=y +CONFIG_MSM_TZ_LOG=y +CONFIG_EXT3_FS=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_UBIFS_FS=y +CONFIG_UBIFS_FS_ADVANCED_COMPR=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_PRINTK_TIME=y +CONFIG_DYNAMIC_DEBUG=y +CONFIG_DEBUG_INFO=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_PAGEALLOC=y +CONFIG_DEBUG_KMEMLEAK=y +CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y +CONFIG_DEBUG_STACK_USAGE=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_PANIC_ON_RECURSIVE_FAULT=y +CONFIG_PANIC_TIMEOUT=5 +CONFIG_SCHEDSTATS=y +CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_SPINLOCK_PANIC_ON_BUG=y +CONFIG_DEBUG_MUTEXES=y +CONFIG_DEBUG_ATOMIC_SLEEP=y +CONFIG_DEBUG_LIST=y +CONFIG_DEBUG_CREDENTIALS=y +CONFIG_FAULT_INJECTION=y +CONFIG_FAIL_PAGE_ALLOC=y +CONFIG_FAULT_INJECTION_DEBUG_FS=y +CONFIG_FAULT_INJECTION_STACKTRACE_FILTER=y +CONFIG_IPC_LOGGING=y +CONFIG_QCOM_RTB=y +CONFIG_FUNCTION_TRACER=y +CONFIG_PREEMPTIRQ_EVENTS=y +CONFIG_IRQSOFF_TRACER=y +CONFIG_PREEMPT_TRACER=y +CONFIG_LKDTM=m +CONFIG_PANIC_ON_DATA_CORRUPTION=y +CONFIG_DEBUG_USER=y +CONFIG_CORESIGHT=y +CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y +CONFIG_CORESIGHT_SOURCE_ETM3X=y +CONFIG_CORESIGHT_DYNAMIC_REPLICATOR=y +CONFIG_CORESIGHT_STM=y +CONFIG_CORESIGHT_CTI=y +CONFIG_CORESIGHT_TPDA=y +CONFIG_CORESIGHT_TPDM=y +CONFIG_CORESIGHT_HWEVENT=y +CONFIG_CORESIGHT_DUMMY=y +CONFIG_CORESIGHT_REMOTE_ETM=y +CONFIG_CORESIGHT_REMOTE_ETM_DEFAULT_ENABLE=0 +CONFIG_CORESIGHT_TGU=y +CONFIG_CORESIGHT_EVENT=y +CONFIG_SECURITY_PERF_EVENTS_RESTRICT=y +CONFIG_SECURITY=y +CONFIG_SECURITY_NETWORK=y +CONFIG_SECURITY_NETWORK_XFRM=y +CONFIG_HARDENED_USERCOPY=y +CONFIG_HARDENED_USERCOPY_PAGESPAN=y +CONFIG_SECURITY_SELINUX=y +# CONFIG_SECURITY_SELINUX_AVC_STATS is not set +CONFIG_CRYPTO_DEV_QCOM_MSM_QCE=y +CONFIG_CRYPTO_DEV_QCRYPTO=y +CONFIG_CRYPTO_DEV_QCEDEV=y +CONFIG_XZ_DEC=y diff --git a/arch/arm/configs/vendor/sdxprairie-perf_defconfig b/arch/arm/configs/vendor/sdxprairie-perf_defconfig index ccd851bd5dca7a3d5cc889af41de0f458fc59350..d629857a60fe118494723de80d8b6cba5ce83e5f 100644 --- a/arch/arm/configs/vendor/sdxprairie-perf_defconfig +++ b/arch/arm/configs/vendor/sdxprairie-perf_defconfig @@ -156,10 +156,8 @@ CONFIG_VLAN_8021Q=y CONFIG_NET_SCHED=y CONFIG_NET_SCH_PRIO=y CONFIG_QRTR=y -CONFIG_QRTR_NODE_ID=2 CONFIG_QRTR_SMD=y CONFIG_QRTR_MHI=y -CONFIG_QRTR_MHI_DEV=y CONFIG_BT=y # CONFIG_BT_BREDR is not set # CONFIG_BT_LE is not set @@ -381,9 +379,6 @@ CONFIG_RPMSG_QCOM_GLINK_SMEM=y CONFIG_QCOM_LLCC=y CONFIG_QCOM_SDXPRAIRIE_LLCC=y CONFIG_QCOM_QMI_HELPERS=y -CONFIG_QCOM_QMI_RMNET=y -CONFIG_QCOM_QMI_DFC=y -CONFIG_QCOM_QMI_POWER_COLLAPSE=y CONFIG_QCOM_SMEM=y CONFIG_QCOM_SCM=y CONFIG_QCOM_MEMORY_DUMP_V2=y diff --git a/arch/arm/configs/vendor/sdxprairie_defconfig b/arch/arm/configs/vendor/sdxprairie_defconfig index 994ee3ad74b9b818b2e605af00d0c6f5a8b9d437..04b5b0310ce40361e6835c92896407a4a1555c25 100644 --- a/arch/arm/configs/vendor/sdxprairie_defconfig +++ b/arch/arm/configs/vendor/sdxprairie_defconfig @@ -156,10 +156,8 @@ CONFIG_VLAN_8021Q=y CONFIG_NET_SCHED=y CONFIG_NET_SCH_PRIO=y CONFIG_QRTR=y -CONFIG_QRTR_NODE_ID=2 CONFIG_QRTR_SMD=y CONFIG_QRTR_MHI=y -CONFIG_QRTR_MHI_DEV=y CONFIG_BT=y # CONFIG_BT_BREDR is not set # CONFIG_BT_LE is not set @@ -386,9 +384,6 @@ CONFIG_RPMSG_QCOM_GLINK_SMEM=y CONFIG_QCOM_LLCC=y CONFIG_QCOM_SDXPRAIRIE_LLCC=y CONFIG_QCOM_QMI_HELPERS=y -CONFIG_QCOM_QMI_RMNET=y -CONFIG_QCOM_QMI_DFC=y -CONFIG_QCOM_QMI_POWER_COLLAPSE=y CONFIG_QCOM_SMEM=y CONFIG_QCOM_SCM=y CONFIG_QCOM_MEMORY_DUMP_V2=y diff --git a/arch/arm/mach-qcom/Kconfig b/arch/arm/mach-qcom/Kconfig index 8b77bab0f1793fff103b2360693f134b1f72b384..fc17977d52a2b1f814aac518d723f8f75c986534 100644 --- a/arch/arm/mach-qcom/Kconfig +++ b/arch/arm/mach-qcom/Kconfig @@ -2,7 +2,7 @@ if ARCH_QCOM menu "QCOM SoC Type" config ARCH_QCS405 - bool "Enable Support for QCS405" + bool "Enable Support for QCS405" select CLKDEV_LOOKUP select HAVE_CLK select HAVE_CLK_PREPARE @@ -37,42 +37,6 @@ config ARCH_QCS405 This enables support for the QCS405 chipset. If you do not wish to build a kernel that runs on this chipset, say 'N' here. -config ARCH_QCS403 - bool "Enable Support for QCS403" - select CLKDEV_LOOKUP - select HAVE_CLK - select HAVE_CLK_PREPARE - select PM_OPP - select SOC_BUS - select MSM_IRQ - select THERMAL_WRITABLE_TRIPS - select ARM_GIC - select ARM_AMBA - select SPARSE_IRQ - select MULTI_IRQ_HANDLER - select HAVE_ARM_ARCH_TIMER - select MAY_HAVE_SPARSE_IRQ - select COMMON_CLK - select QCOM_GDSC - select PINCTRL_MSM - select USE_PINCTRL_IRQ - select MSM_PM if PM - select QMI_ENCDEC - select CPU_FREQ - select CPU_FREQ_MSM - select PM_DEVFREQ - select MSM_DEVFREQ_DEVBW - select DEVFREQ_SIMPLE_DEV - select DEVFREQ_GOV_MSM_BW_HWMON - select MSM_BIMC_BWMON - select MSM_QDSP6V2_CODECS - select MSM_AUDIO_QDSP6V2 if SND_SOC - select MSM_RPM_SMD - select MSM_JTAGV8 if CORESIGHT_ETMV4 - help - This enables support for the QCS403 chipset. If you do not - wish to build a kernel that runs on this chipset, say 'N' here. - config ARCH_MSM8X60 bool "Enable support for MSM8X60" select ARCH_SUPPORTS_BIG_ENDIAN diff --git a/arch/arm/mach-qcom/Makefile b/arch/arm/mach-qcom/Makefile index 27a323e0bee7c30df1f2f848678b415c49c7c4c5..23af561084b8abc58369834d3f7dbd914ff0042d 100644 --- a/arch/arm/mach-qcom/Makefile +++ b/arch/arm/mach-qcom/Makefile @@ -1,5 +1,4 @@ obj-$(CONFIG_USE_OF) += board-dt.o obj-$(CONFIG_SMP) += platsmp.o obj-$(CONFIG_ARCH_QCS405) += board-qcs405.o -obj-$(CONFIG_ARCH_QCS403) += board-qcs403.o obj-$(CONFIG_ARCH_SDXPRAIRIE) += board-sdxprairie.o diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index 1a4d48a38416983bda13420e2c6f04789dc4aceb..204a63061aa64f3994c6529a505f642eb4a95009 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -2718,13 +2718,10 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, if (dev->dma_ops) return; - if (arm_setup_iommu_dma_ops(dev, dma_base, size, iommu)) { + if (arm_setup_iommu_dma_ops(dev, dma_base, size, iommu)) dma_ops = arm_get_iommu_dma_map_ops(coherent); - dev->archdata.dma_ops_setup = true; - } else { + else dma_ops = arm_get_dma_map_ops(coherent); - dev->archdata.dma_ops_setup = false; - } set_dma_ops(dev, dma_ops); @@ -2734,6 +2731,7 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, dev->dma_ops = xen_dma_ops; } #endif + dev->archdata.dma_ops_setup = true; } EXPORT_SYMBOL(arch_setup_dma_ops); diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 0668ea29ca9c3bb93ce3db418f981ac335fd452c..7457f0e57125c137b462f0dac4f69aedb5918351 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -522,16 +522,6 @@ config ARM64_ERRATUM_1286807 invalidated has been observed by other observers. The workaround repeats the TLBI+DSB operation. -config ARM64_ERRATUM_1188873 - bool "Cortex-A76: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" - default y - help - This option adds work arounds for ARM Cortex-A76 erratum 1188873 - - Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could cause - register corruption when accessing the timer registers from - AArch32 userspace. - If unsure, say Y. config CAVIUM_ERRATUM_22375 @@ -1465,3 +1455,4 @@ source "arch/arm64/crypto/Kconfig" endif source "lib/Kconfig" +source "coretech/Kconfig" diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 1b524f2c04330b8226f5808b4a9f343ed6d3d0f2..6ce416f15959e32e6591c6491023e3b26eced588 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -186,16 +186,6 @@ config ARCH_QCS405 If you do not wish to build a kernel that runs on this chipset, say 'N' here. -config ARCH_QCS403 - bool "Enable Support for Qualcomm Technologies, Inc. QCS403" - depends on ARCH_QCOM - select COMMON_CLK_QCOM - help - This configuration option enables support to build kernel for - QCS403 SoC. - If you do not wish to build a kernel that runs on this chipset, - say 'N' here. - config ARCH_SDMMAGPIE bool "Enable Support for Qualcomm Technologies, Inc. SDMMAGPIE" depends on ARCH_QCOM diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile old mode 100644 new mode 100755 index e7157c9d7534b02d0d73d9b9da33453f514ed68c..d88908cf753e2b6f1aff75e0a40aa147aea31bc1 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY_QCOM),y) dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb @@ -6,26 +7,27 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb - -dtb-$(CONFIG_ARCH_QCS403) += qcs403-iot-sku1.dtb \ - qcs403-iot-sku3.dtb \ - qcs403-iot-sku5.dtb \ - qcs401-iot-sku5.dtb \ - qcs404-iot-sku3.dtb \ - qcs404-iot-sku5.dtb \ - qcs404-iot-sku6.dtb - -dtb-$(CONFIG_ARCH_QCS405) += qcs405-iot-sku1.dtb \ - qcs407-iot-sku1.dtb \ +ifeq ($(CONFIG_ARM64),y) +dtb-$(CONFIG_ARCH_QCS405) += qcs405-rumi.dtb \ + qcs405-iot-sku1.dtb \ + qcs405-iot-sku2.dtb \ qcs405-iot-sku3.dtb \ - qcs407-iot-sku3.dtb \ qcs405-iot-sku4.dtb \ - qcs407-iot-sku4.dtb \ + qcs405-iot-sku5.dtb \ qcs405-iot-sku6.dtb \ - qcs407-iot-sku6.dtb \ - qcs407-iot-sku9.dtb \ + qcs405-iot-sku7.dtb \ + qcs405-iot-sku8.dtb \ + qcs405-iot-sku9.dtb \ + qcs405-iot-sku10.dtb \ + qcs405-iot-sku11.dtb \ qcs405-iot-sku12.dtb \ - qcs407-iot-sku12.dtb + qcs401-iot-sku1.dtb +else +dtb-$(CONFIG_ARCH_QCS405) += qcs403-iot-sku1.dtb \ + qcs403-iot-sku2.dtb \ + qcs403-iot-sku3.dtb \ + qcs403-iot-sku4.dtb +endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) dtbo-$(CONFIG_ARCH_SM8150) += \ @@ -68,6 +70,72 @@ sm8150-sdx50m-mtp-2.5k-panel-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm815 sm8150-sdx50m-qrd-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb sm8150-sdxprairie-cdp-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb sm8150-sdxprairie-mtp-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +endif +endif + +ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) + dtbo-$(CONFIG_ARCH_SM8150) += \ + sm8150-mtp-overlay.dtbo \ + sm8150-sdxprairie-mtp-overlay.dtbo \ + guacamole-overlay-t0.dtbo \ + guacamole-overlay-evt1.dtbo \ + guacamole-overlay-evt2.dtbo \ + guacamole-overlay-evt2-second.dtbo \ + guacamole-overlay-evt3.dtbo \ + guacamole-overlay-dvt.dtbo \ + guacamole-overlay-pvt.dtbo \ + guacamoleb-overlay-t0.dtbo \ + guacamoleb-overlay-evt.dtbo \ + guacamoleb-overlay-dvt.dtbo \ + guacamoleb-overlay-pvt.dtbo \ + sm8150-sdx50m-mtp-overlay.dtbo \ + guacamole-sdx50m-overlay-t0.dtbo \ + guacamole-sdx50m-overlay-evt1.dtbo \ + guacamole-sdx50m-overlay-evt2.dtbo \ + guacamole-sdx50m-overlay-dvt.dtbo \ + guacamole-sdx50m-overlay-pvt.dtbo \ + guacamoles-sdx50m-overlay-t0.dtbo \ + guacamoles-sdx50m-overlay-evt.dtbo \ + guacamoles-sdx50m-overlay-dvt.dtbo \ + guacamoles-sdx50m-overlay-pvt.dtbo \ + hotdogb-overlay-t0.dtbo \ + hotdogb-overlay-evt.dtbo \ + hotdogb-overlay-evt-second.dtbo \ + hotdogb-overlay-dvt.dtbo \ + hotdogb-overlay-dvt-second.dtbo \ + hotdogb-overlay-pvt.dtbo \ + hotdogb-overlay-pvt-second.dtbo + +sm8150-mtp-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +sm8150-sdxprairie-mtp-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-overlay-t0.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-overlay-evt1.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-overlay-evt2.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-overlay-evt2-second.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-overlay-evt3.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-overlay-dvt.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-overlay-pvt.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamoleb-overlay-t0.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamoleb-overlay-evt.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamoleb-overlay-dvt.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamoleb-overlay-pvt.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +sm8150-sdx50m-mtp-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-sdx50m-overlay-t0.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-sdx50m-overlay-evt1.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-sdx50m-overlay-evt2.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-sdx50m-overlay-dvt.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-sdx50m-overlay-pvt.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamoles-sdx50m-overlay-t0.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamoles-sdx50m-overlay-evt.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamoles-sdx50m-overlay-dvt.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamoles-sdx50m-overlay-pvt.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +hotdogb-overlay-t0.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +hotdogb-overlay-evt.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +hotdogb-overlay-evt-second.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +hotdogb-overlay-dvt.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +hotdogb-overlay-dvt-second.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +hotdogb-overlay-pvt.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +hotdogb-overlay-pvt-second.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb sm8150-sdxprairie-v2-cdp-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb sm8150-sdxprairie-v2-mtp-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb else @@ -246,24 +314,15 @@ endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) dtbo-$(CONFIG_ARCH_ATOLL) += \ atoll-idp-overlay.dtbo\ - atoll-atp-overlay.dtbo\ atoll-qrd-overlay.dtbo\ - atoll-wcd937x-idp-overlay.dtbo\ - atoll-usbc-idp-overlay.dtbo\ atoll-rumi-overlay.dtbo atoll-idp-overlay.dtbo-base := atoll.dtb -atoll-atp-overlay.dtbo-base := atoll.dtb atoll-qrd-overlay.dtbo-base := atoll.dtb atoll-rumi-overlay.dtbo-base := atoll.dtb -atoll-wcd937x-idp-overlay.dtbo-base := atoll.dtb -atoll-usbc-idp-overlay.dtbo-base := atoll.dtb else dtb-$(CONFIG_ARCH_ATOLL) += atoll-idp.dtb\ - atoll-atp.dtb\ atoll-qrd.dtb\ - atoll-wcd937x-idp.dtb\ - atoll-usbc-idp.dtb\ atoll-rumi.dtb endif diff --git a/arch/arm64/boot/dts/qcom/OP-fg-batterydata-3700mah.dtsi b/arch/arm64/boot/dts/qcom/OP-fg-batterydata-3700mah.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..131fb2dc9e0dc730ec1799455de1d4b1caac1582 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/OP-fg-batterydata-3700mah.dtsi @@ -0,0 +1,144 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +qcom,OP_3700mAh { + qcom,max-voltage-uv = <4370000>; + qcom,fastchg-current-ma = <3000>; + qcom,jeita-fcc-ranges = <0 100 2500000 + 110 400 5400000 + 410 450 2500000>; + qcom,jeita-fv-ranges = <0 100 4250000 + 110 400 4350000 + 410 450 4250000>; + qcom,step-chg-ranges = <3600000 3800000 5400000 + 3801000 4300000 3600000 + 4301000 4350000 2500000>; + qcom,ocv-based-step-chg; + qcom,batt-id-kohm = <200>; + qcom,battery-beta = <4250>; + qcom,therm-room-temp = <100000>; + qcom,fg-cc-cv-threshold-mv = <4340>; + qcom,battery-type = "OP_3700mAh"; + qcom,therm-coefficients = <0x2318 0xd0c 0xdaf7 0xc556 0x848d>; + qcom,therm-center-offset = <0x70>; + qcom,therm-pull-up = <100>; + qcom,rslow-normal-coeffs = <0xdf 0x02 0x77 0x1a>; + qcom,rslow-low-coeffs = <0x51 0x04 0xd0 0x13>; + qcom,checksum = <0x1538>; + qcom,gui-version = "PM855GUI - 1.0.0.10"; + qcom,fg-profile-data = [ + 09 00 C7 EA + C4 DC 8E E2 + 3A DD 00 00 + 15 BC A5 8A + 02 80 D1 92 + AB 9D 47 80 + 10 00 DF 02 + 77 1A 85 EC + E1 FD CE 07 + 32 00 75 EB + AA ED F3 CD + 0C 0A 7A E4 + ED C5 40 1B + D0 02 1F CA + FF 00 52 00 + 4D 00 4A 00 + 3C 00 35 00 + 38 00 39 00 + 48 00 43 00 + 3F 00 FF 00 + 38 00 40 00 + 46 00 50 00 + 45 00 5C 00 + 7E 64 60 00 + 50 08 50 10 + FF 00 6A 00 + 5F 00 63 00 + 6E 00 60 00 + 7D 20 96 40 + 75 50 6B 13 + 63 00 D8 00 + 14 22 7E 0D + 21 02 AA 04 + ED 1C D4 09 + 64 0C D3 23 + A4 18 D3 42 + B5 55 91 02 + 90 12 2A 1F + 02 06 1F 0A + A3 06 AE 1C + 8D 02 96 04 + D2 03 D1 17 + 51 23 3F 45 + 28 53 69 14 + 93 20 8E EC + 18 CB C8 C5 + DB 1C 7B C9 + 7C 05 E6 C2 + B9 17 2C 93 + 87 85 A2 92 + 91 A8 09 80 + 92 F2 1A 0D + F4 FC 5E EB + 00 F8 FB ED + 15 E2 F6 0F + 75 02 72 05 + 49 01 10 00 + FA E5 E2 03 + 8D 05 85 02 + CE 07 32 00 + 23 03 46 02 + 9C 04 03 02 + 48 07 0A 00 + BA 03 97 02 + 65 05 50 00 + 3A 00 41 00 + 43 64 45 00 + 45 10 45 18 + 46 08 44 00 + 47 00 3A 08 + 4B 08 37 00 + 47 20 4E 40 + 54 58 60 10 + 57 00 5F 00 + 57 08 55 00 + 4B 00 50 00 + 3E 08 52 08 + 52 00 5C 20 + 6F 40 7D 58 + 67 10 63 00 + 69 08 4F 10 + D8 00 8C 2A + DB 04 28 02 + AD 04 0B 1D + 50 22 A7 45 + 0D 52 A2 18 + 74 03 AD 04 + 35 02 AE 13 + 3F 0A 5A 20 + DD 04 F1 02 + D8 05 C7 1C + DD 02 3D 04 + EB 03 97 18 + 52 03 D5 04 + 19 02 72 00 + 14 22 7E 05 + 21 02 AA 04 + ED 1C D4 01 + 64 04 D3 03 + A4 18 D3 02 + B5 05 91 02 + 90 00 7C 01 + C0 00 FA 00 + 04 0E 00 00 + ]; +}; diff --git a/arch/arm64/boot/dts/qcom/OP-fg-batterydata-3800mah.dtsi b/arch/arm64/boot/dts/qcom/OP-fg-batterydata-3800mah.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..f24c758591f2c2bfe8bb0331ba8f26571cd76fae --- /dev/null +++ b/arch/arm64/boot/dts/qcom/OP-fg-batterydata-3800mah.dtsi @@ -0,0 +1,144 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +qcom,OP_3800mAh { + qcom,max-voltage-uv = <4370000>; + qcom,fastchg-current-ma = <3000>; + qcom,jeita-fcc-ranges = <0 100 2500000 + 110 400 5400000 + 410 450 2500000>; + qcom,jeita-fv-ranges = <0 100 4250000 + 110 400 4350000 + 410 450 4250000>; + qcom,step-chg-ranges = <3600000 3800000 5400000 + 3801000 4300000 3600000 + 4301000 4350000 2500000>; + qcom,ocv-based-step-chg; + qcom,batt-id-kohm = <200>; + qcom,battery-beta = <4250>; + qcom,therm-room-temp = <100000>; + qcom,fg-cc-cv-threshold-mv = <4340>; + qcom,battery-type = "OP_3800mAh"; + qcom,therm-coefficients = <0x2318 0xd0c 0xdaf7 0xc556 0x848d>; + qcom,therm-center-offset = <0x70>; + qcom,therm-pull-up = <100>; + qcom,rslow-normal-coeffs = <0xdf 0x02 0x77 0x1a>; + qcom,rslow-low-coeffs = <0x51 0x04 0xd0 0x13>; + qcom,checksum = <0x1538>; + qcom,gui-version = "PM855GUI - 1.0.0.10"; + qcom,fg-profile-data = [ + 09 00 C7 EA + C4 DC 8E E2 + 3A DD 00 00 + 15 BC A5 8A + 02 80 D1 92 + AB 9D 47 80 + 10 00 DF 02 + 77 1A 85 EC + E1 FD CE 07 + 32 00 75 EB + AA ED F3 CD + 0C 0A 7A E4 + ED C5 40 1B + D0 02 1F CA + FF 00 52 00 + 4D 00 4A 00 + 3C 00 35 00 + 38 00 39 00 + 48 00 43 00 + 3F 00 FF 00 + 38 00 40 00 + 46 00 50 00 + 45 00 5C 00 + 7E 64 60 00 + 50 08 50 10 + FF 00 6A 00 + 5F 00 63 00 + 6E 00 60 00 + 7D 20 96 40 + 75 50 6B 13 + 63 00 D8 00 + 14 22 7E 0D + 21 02 AA 04 + ED 1C D4 09 + 64 0C D3 23 + A4 18 D3 42 + B5 55 91 02 + 90 12 2A 1F + 02 06 1F 0A + A3 06 AE 1C + 8D 02 96 04 + D2 03 D1 17 + 51 23 3F 45 + 28 53 69 14 + 93 20 8E EC + 18 CB C8 C5 + DB 1C 7B C9 + 7C 05 E6 C2 + B9 17 2C 93 + 87 85 A2 92 + 91 A8 09 80 + 92 F2 1A 0D + F4 FC 5E EB + 00 F8 FB ED + 15 E2 F6 0F + 75 02 72 05 + 49 01 10 00 + FA E5 E2 03 + 8D 05 85 02 + CE 07 32 00 + 23 03 46 02 + 9C 04 03 02 + 48 07 0A 00 + BA 03 97 02 + 65 05 50 00 + 3A 00 41 00 + 43 64 45 00 + 45 10 45 18 + 46 08 44 00 + 47 00 3A 08 + 4B 08 37 00 + 47 20 4E 40 + 54 58 60 10 + 57 00 5F 00 + 57 08 55 00 + 4B 00 50 00 + 3E 08 52 08 + 52 00 5C 20 + 6F 40 7D 58 + 67 10 63 00 + 69 08 4F 10 + D8 00 8C 2A + DB 04 28 02 + AD 04 0B 1D + 50 22 A7 45 + 0D 52 A2 18 + 74 03 AD 04 + 35 02 AE 13 + 3F 0A 5A 20 + DD 04 F1 02 + D8 05 C7 1C + DD 02 3D 04 + EB 03 97 18 + 52 03 D5 04 + 19 02 72 00 + 14 22 7E 05 + 21 02 AA 04 + ED 1C D4 01 + 64 04 D3 03 + A4 18 D3 02 + B5 05 91 02 + 90 00 7C 01 + C0 00 FA 00 + 04 0E 00 00 + ]; +}; diff --git a/arch/arm64/boot/dts/qcom/OP-fg-batterydata-4000mah.dtsi b/arch/arm64/boot/dts/qcom/OP-fg-batterydata-4000mah.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..3f0116c033bab78eecd8028b4b4181c19cfd6f67 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/OP-fg-batterydata-4000mah.dtsi @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +qcom,OP_4000mAh { + qcom,max-voltage-uv = <4370000>; + qcom,fastchg-current-ma = <3000>; + qcom,jeita-fcc-ranges = <0 100 2500000 + 110 400 5400000 + 410 450 2500000>; + qcom,jeita-fv-ranges = <0 100 4250000 + 110 400 4350000 + 410 450 4250000>; + qcom,step-chg-ranges = <3600000 3800000 5400000 + 3801000 4300000 3600000 + 4301000 4350000 2500000>; + qcom,ocv-based-step-chg; + qcom,batt-id-kohm = <200>; + qcom,battery-beta = <4250>; + qcom,therm-room-temp = <100000>; + qcom,fg-cc-cv-threshold-mv = <4340>; + qcom,battery-type = "OP_4000mAh "; + qcom,therm-coefficients = <0x2318 0xd0c 0xdaf7 0xc556 0x848d>; + qcom,therm-center-offset = <0x70>; + qcom,therm-pull-up = <100>; + qcom,rslow-normal-coeffs = <0xdf 0x02 0x77 0x1a>; + qcom,rslow-low-coeffs = <0x51 0x04 0xd0 0x13>; + qcom,checksum = <0x1538>; + qcom,gui-version = "PM855GUI - 1.0.0.10"; + qcom,fg-profile-data = [ + 09 00 C7 EA + C4 DC 8E E2 + 3A DD 00 00 + 15 BC A5 8A + 02 80 D1 92 + AB 9D 47 80 + 10 00 DF 02 + 77 1A 85 EC + E1 FD CE 07 + 32 00 75 EB + AA ED F3 CD + 0C 0A 7A E4 + ED C5 40 1B + D0 02 1F CA + FF 00 52 00 + 4D 00 4A 00 + 3C 00 35 00 + 38 00 39 00 + 48 00 43 00 + 3F 00 FF 00 + 38 00 40 00 + 46 00 50 00 + 45 00 5C 00 + 7E 64 60 00 + 50 08 50 10 + FF 00 6A 00 + 5F 00 63 00 + 6E 00 60 00 + 7D 20 96 40 + 75 50 6B 13 + 63 00 D8 00 + 14 22 7E 0D + 21 02 AA 04 + ED 1C D4 09 + 64 0C D3 23 + A4 18 D3 42 + B5 55 91 02 + 90 12 2A 1F + 02 06 1F 0A + A3 06 AE 1C + 8D 02 96 04 + D2 03 D1 17 + 51 23 3F 45 + 28 53 69 14 + 93 20 8E EC + 18 CB C8 C5 + DB 1C 7B C9 + 7C 05 E6 C2 + B9 17 2C 93 + 87 85 A2 92 + 91 A8 09 80 + 92 F2 1A 0D + F4 FC 5E EB + 00 F8 FB ED + 15 E2 F6 0F + 75 02 72 05 + 49 01 10 00 + FA E5 E2 03 + 8D 05 85 02 + CE 07 32 00 + 23 03 46 02 + 9C 04 03 02 + 48 07 0A 00 + BA 03 97 02 + 65 05 50 00 + 3A 00 41 00 + 43 64 45 00 + 45 10 45 18 + 46 08 44 00 + 47 00 3A 08 + 4B 08 37 00 + 47 20 4E 40 + 54 58 60 10 + 57 00 5F 00 + 57 08 55 00 + 4B 00 50 00 + 3E 08 52 08 + 52 00 5C 20 + 6F 40 7D 58 + 67 10 63 00 + 69 08 4F 10 + D8 00 8C 2A + DB 04 28 02 + AD 04 0B 1D + 50 22 A7 45 + 0D 52 A2 18 + 74 03 AD 04 + 35 02 AE 13 + 3F 0A 5A 20 + DD 04 F1 02 + D8 05 C7 1C + DD 02 3D 04 + EB 03 97 18 + 52 03 D5 04 + 19 02 72 00 + 14 22 7E 05 + 21 02 AA 04 + ED 1C D4 01 + 64 04 D3 03 + A4 18 D3 02 + B5 05 91 02 + 90 00 7C 01 + C0 00 FA 00 + 04 0E 00 00 + ]; +}; diff --git a/arch/arm64/boot/dts/qcom/OP-fg-batterydata-4085mah.dtsi b/arch/arm64/boot/dts/qcom/OP-fg-batterydata-4085mah.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..c6c284df1b9bc616264af1db0ab7f56cc8ba550d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/OP-fg-batterydata-4085mah.dtsi @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +qcom,OP_4085mAh { + qcom,max-voltage-uv = <4370000>; + qcom,fastchg-current-ma = <3000>; + qcom,jeita-fcc-ranges = <0 100 2500000 + 110 400 5400000 + 410 450 2500000>; + qcom,jeita-fv-ranges = <0 100 4250000 + 110 400 4350000 + 410 450 4250000>; + qcom,step-chg-ranges = <3600000 3800000 5400000 + 3801000 4300000 3600000 + 4301000 4350000 2500000>; + qcom,ocv-based-step-chg; + qcom,batt-id-kohm = <200>; + qcom,battery-beta = <4250>; + qcom,therm-room-temp = <100000>; + qcom,fg-cc-cv-threshold-mv = <4340>; + qcom,battery-type = "OP_4085mAh "; + qcom,therm-coefficients = <0x2318 0xd0c 0xdaf7 0xc556 0x848d>; + qcom,therm-center-offset = <0x70>; + qcom,therm-pull-up = <100>; + qcom,rslow-normal-coeffs = <0xdf 0x02 0x77 0x1a>; + qcom,rslow-low-coeffs = <0x51 0x04 0xd0 0x13>; + qcom,checksum = <0x1538>; + qcom,gui-version = "PM855GUI - 1.0.0.10"; + qcom,fg-profile-data = [ + 09 00 C7 EA + C4 DC 8E E2 + 3A DD 00 00 + 15 BC A5 8A + 02 80 D1 92 + AB 9D 47 80 + 10 00 DF 02 + 77 1A 85 EC + E1 FD CE 07 + 32 00 75 EB + AA ED F3 CD + 0C 0A 7A E4 + ED C5 40 1B + D0 02 1F CA + FF 00 52 00 + 4D 00 4A 00 + 3C 00 35 00 + 38 00 39 00 + 48 00 43 00 + 3F 00 FF 00 + 38 00 40 00 + 46 00 50 00 + 45 00 5C 00 + 7E 64 60 00 + 50 08 50 10 + FF 00 6A 00 + 5F 00 63 00 + 6E 00 60 00 + 7D 20 96 40 + 75 50 6B 13 + 63 00 D8 00 + 14 22 7E 0D + 21 02 AA 04 + ED 1C D4 09 + 64 0C D3 23 + A4 18 D3 42 + B5 55 91 02 + 90 12 2A 1F + 02 06 1F 0A + A3 06 AE 1C + 8D 02 96 04 + D2 03 D1 17 + 51 23 3F 45 + 28 53 69 14 + 93 20 8E EC + 18 CB C8 C5 + DB 1C 7B C9 + 7C 05 E6 C2 + B9 17 2C 93 + 87 85 A2 92 + 91 A8 09 80 + 92 F2 1A 0D + F4 FC 5E EB + 00 F8 FB ED + 15 E2 F6 0F + 75 02 72 05 + 49 01 10 00 + FA E5 E2 03 + 8D 05 85 02 + CE 07 32 00 + 23 03 46 02 + 9C 04 03 02 + 48 07 0A 00 + BA 03 97 02 + 65 05 50 00 + 3A 00 41 00 + 43 64 45 00 + 45 10 45 18 + 46 08 44 00 + 47 00 3A 08 + 4B 08 37 00 + 47 20 4E 40 + 54 58 60 10 + 57 00 5F 00 + 57 08 55 00 + 4B 00 50 00 + 3E 08 52 08 + 52 00 5C 20 + 6F 40 7D 58 + 67 10 63 00 + 69 08 4F 10 + D8 00 8C 2A + DB 04 28 02 + AD 04 0B 1D + 50 22 A7 45 + 0D 52 A2 18 + 74 03 AD 04 + 35 02 AE 13 + 3F 0A 5A 20 + DD 04 F1 02 + D8 05 C7 1C + DD 02 3D 04 + EB 03 97 18 + 52 03 D5 04 + 19 02 72 00 + 14 22 7E 05 + 21 02 AA 04 + ED 1C D4 01 + 64 04 D3 03 + A4 18 D3 02 + B5 05 91 02 + 90 00 7C 01 + C0 00 FA 00 + 04 0E 00 00 + ]; +}; diff --git a/arch/arm64/boot/dts/qcom/atoll-coresight.dtsi b/arch/arm64/boot/dts/qcom/atoll-coresight.dtsi index 30469db9e54b534f7a3a3b9a3c69c51cf95efd8e..1cd3070a79187fd3dc4e7fd1211bd22b33a3c76d 100644 --- a/arch/arm64/boot/dts/qcom/atoll-coresight.dtsi +++ b/arch/arm64/boot/dts/qcom/atoll-coresight.dtsi @@ -240,7 +240,7 @@ compatible = "qcom,coresight-remote-etm"; coresight-name = "coresight-npu-etm0"; - qcom,inst-id = <14>; + qcom,inst-id = <2>; port { npu_etm0_out_funnel_npu: endpoint { diff --git a/arch/arm64/boot/dts/qcom/atoll-gdsc.dtsi b/arch/arm64/boot/dts/qcom/atoll-gdsc.dtsi index 0eba4a21ff28f6ae242c9d6d3a0cc88e44d90623..723bdb0495c87e6cb83cb405372be48807aeec51 100644 --- a/arch/arm64/boot/dts/qcom/atoll-gdsc.dtsi +++ b/arch/arm64/boot/dts/qcom/atoll-gdsc.dtsi @@ -14,7 +14,7 @@ &soc { /* GDSCs in Global CC */ ufs_phy_gdsc: qcom,gdsc@177004 { - compatible = "qcom,gdsc"; + compatible = "regulator-fixed"; regulator-name = "ufs_phy_gdsc"; reg = <0x177004 0x4>; qcom,poll-cfg-gdscr; @@ -22,7 +22,7 @@ }; usb30_prim_gdsc: qcom,gdsc@10f004 { - compatible = "qcom,gdsc"; + compatible = "regulator-fixed"; regulator-name = "usb30_prim_gdsc"; reg = <0x10f004 0x4>; qcom,poll-cfg-gdscr; @@ -30,7 +30,7 @@ }; hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d040 { - compatible = "qcom,gdsc"; + compatible = "regulator-fixed"; regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc"; reg = <0x17d040 0x4>; qcom,no-status-check-on-disable; @@ -39,7 +39,7 @@ }; hlos1_vote_mmnoc_mmu_tbu_sf_gdsc: qcom,gdsc@17d044 { - compatible = "qcom,gdsc"; + compatible = "regulator-fixed"; regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc"; reg = <0x17d044 0x4>; qcom,no-status-check-on-disable; @@ -49,7 +49,7 @@ /* GDSCs in Camera CC */ bps_gdsc: qcom,gdsc@ad06004 { - compatible = "qcom,gdsc"; + compatible = "regulator-fixed"; regulator-name = "bps_gdsc"; reg = <0xad06004 0x4>; qcom,poll-cfg-gdscr; @@ -57,7 +57,7 @@ }; ipe_0_gdsc: qcom,gdsc@ad07004 { - compatible = "qcom,gdsc"; + compatible = "regulator-fixed"; regulator-name = "ipe_0_gdsc"; reg = <0xad07004 0x4>; qcom,poll-cfg-gdscr; @@ -65,7 +65,7 @@ }; ife_0_gdsc: qcom,gdsc@ad09004 { - compatible = "qcom,gdsc"; + compatible = "regulator-fixed"; regulator-name = "ife_0_gdsc"; reg = <0xad09004 0x4>; qcom,poll-cfg-gdscr; @@ -73,7 +73,7 @@ }; ife_1_gdsc: qcom,gdsc@ad0a004 { - compatible = "qcom,gdsc"; + compatible = "regulator-fixed"; regulator-name = "ife_1_gdsc"; reg = <0xad0a004 0x4>; qcom,poll-cfg-gdscr; @@ -81,7 +81,7 @@ }; titan_top_gdsc: qcom,gdsc@ad0b134 { - compatible = "qcom,gdsc"; + compatible = "regulator-fixed"; regulator-name = "titan_top_gdsc"; reg = <0xad0b134 0x4>; qcom,poll-cfg-gdscr; @@ -90,7 +90,7 @@ /* GDSCs in Display CC */ mdss_core_gdsc: qcom,gdsc@af03000 { - compatible = "qcom,gdsc"; + compatible = "regulator-fixed"; regulator-name = "mdss_core_gdsc"; reg = <0xaf03000 0x4>; qcom,poll-cfg-gdscr; @@ -117,7 +117,7 @@ }; gpu_cx_gdsc: qcom,gdsc@509106c { - compatible = "qcom,gdsc"; + compatible = "regulator-fixed"; regulator-name = "gpu_cx_gdsc"; reg = <0x509106c 0x4>; hw-ctrl-addr = <&gpu_cx_hw_ctrl>; @@ -128,7 +128,7 @@ }; gpu_gx_gdsc: qcom,gdsc@509100c { - compatible = "qcom,gdsc"; + compatible = "regulator-fixed"; regulator-name = "gpu_gx_gdsc"; reg = <0x509100c 0x4>; qcom,poll-cfg-gdscr; @@ -139,14 +139,14 @@ /* GDSCs in Video CC */ vcodec0_gdsc: qcom,gdsc@ab00874 { - compatible = "qcom,gdsc"; + compatible = "regulator-fixed"; regulator-name = "vcodec0_gdsc"; reg = <0xab00874 0x4>; status = "disabled"; }; venus_gdsc: qcom,gdsc@ab00814 { - compatible = "qcom,gdsc"; + compatible = "regulator-fixed"; regulator-name = "venus_gdsc"; reg = <0xab00814 0x4>; status = "disabled"; @@ -154,7 +154,7 @@ /* GDSCs in NPU CC */ npu_core_gdsc: qcom,gdsc@9981004 { - compatible = "qcom,gdsc"; + compatible = "regulator-fixed"; regulator-name = "npu_core_gdsc"; reg = <0x9981004 0x4>; status = "disabled"; diff --git a/arch/arm64/boot/dts/qcom/atoll-idp-overlay.dts b/arch/arm64/boot/dts/qcom/atoll-idp-overlay.dts index aec92407329378e1b99f17962b31d348ecd6b3f3..46b35d146ce3348efbaadff662cb5200d4f9407b 100644 --- a/arch/arm64/boot/dts/qcom/atoll-idp-overlay.dts +++ b/arch/arm64/boot/dts/qcom/atoll-idp-overlay.dts @@ -16,7 +16,6 @@ #include #include "atoll-idp.dtsi" -#include "atoll-audio-overlay.dtsi" / { model = "IDP"; @@ -24,7 +23,3 @@ qcom,msm-id = <407 0x0>; qcom,board-id = <34 0>; }; - -&dsi_rm69299_visionox_amoled_vid_display { - qcom,dsi-display-active; -}; diff --git a/arch/arm64/boot/dts/qcom/atoll-idp.dts b/arch/arm64/boot/dts/qcom/atoll-idp.dts index dcd5edb3d055a1d8a7063c67f7e8208f2d0328cd..ff2b4c4266c9773d0f85bfafd0b176516a7d3a94 100644 --- a/arch/arm64/boot/dts/qcom/atoll-idp.dts +++ b/arch/arm64/boot/dts/qcom/atoll-idp.dts @@ -20,7 +20,3 @@ compatible = "qcom,atoll-idp", "qcom,atoll", "qcom,idp"; qcom,board-id = <34 0>; }; - -&dsi_rm69299_visionox_amoled_vid_display { - qcom,dsi-display-active; -}; diff --git a/arch/arm64/boot/dts/qcom/atoll-idp.dtsi b/arch/arm64/boot/dts/qcom/atoll-idp.dtsi index 649190984014251715644acb5d065a022e5d6564..a9c5ba4e4177b83717cca072b74ea7cedeeb09c9 100644 --- a/arch/arm64/boot/dts/qcom/atoll-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/atoll-idp.dtsi @@ -10,18 +10,9 @@ * GNU General Public License for more details. */ -#include -#include #include -#include -#include "atoll-sde-display.dtsi" -#include "atoll-camera-sensor-idp.dtsi" &soc { - mtp_batterydata: qcom,battery-data { - qcom,batt-id-range-pct = <15>; - #include "qg-batterydata-alium-3600mah.dtsi" - }; }; &pm6150l_vadc { @@ -66,77 +57,6 @@ }; }; -&usb0 { - extcon = <&pm6150_pdphy>, <&pm6150_charger>, <&eud>; -}; - -&usb_qmp_dp_phy { - extcon = <&pm6150_pdphy>; -}; - -&ufsphy_mem { - compatible = "qcom,ufs-phy-qmp-v3"; - - vdda-phy-supply = <&pm6150_l4>; /* 0.9v */ - vdda-pll-supply = <&pm6150l_l3>; /* 1.2v */ - vdda-phy-max-microamp = <62900>; - vdda-pll-max-microamp = <18300>; - - status = "ok"; -}; - -&ufshc_mem { - vdd-hba-supply = <&ufs_phy_gdsc>; - vdd-hba-fixed-regulator; - vcc-supply = <&pm6150_l19>; - vcc-voltage-level = <2960000 2960000>; - vcc-max-microamp = <600000>; - vccq2-supply = <&pm6150_l12>; - vccq2-voltage-level = <1750000 1950000>; - vccq2-max-microamp = <600000>; - - qcom,vddp-ref-clk-supply = <&pm6150l_l3>; /* PX10 */ - qcom,vddp-ref-clk-max-microamp = <100>; - - status = "ok"; -}; - -&sdhc_1 { - vdd-supply = <&pm6150_l19>; - qcom,vdd-voltage-level = <2960000 2960000>; - qcom,vdd-current-level = <0 570000>; - - vdd-io-supply = <&pm6150_l12>; - qcom,vdd-io-always-on; - qcom,vdd-io-lpm-sup; - qcom,vdd-io-voltage-level = <1800000 1800000>; - qcom,vdd-io-current-level = <0 325000>; - - pinctrl-names = "active", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; - - status = "ok"; -}; - -&sdhc_2 { - vdd-supply = <&pm6150l_l9>; - qcom,vdd-voltage-level = <2960000 2960000>; - qcom,vdd-current-level = <0 800000>; - - vdd-io-supply = <&pm6150l_l6>; - qcom,vdd-io-voltage-level = <1800000 2950000>; - qcom,vdd-io-current-level = <0 22000>; - - pinctrl-names = "active", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; - - cd-gpios = <&tlmm 69 GPIO_ACTIVE_LOW>; - - status = "ok"; -}; - &spmi_bus { qcom,pm6150l@4 { pm6150l_adc_tm_iio: adc_tm@3400 { @@ -185,136 +105,3 @@ }; }; }; - -&pm6150a_amoled { - status = "ok"; -}; - -&pm6150_qg { - qcom,battery-data = <&mtp_batterydata>; - qcom,qg-iterm-ma = <100>; - qcom,hold-soc-while-full; - qcom,linearize-soc; - qcom,cl-feedback-on; -}; - -&pm6150_charger { - io-channels = <&pm6150_vadc ADC_USB_IN_V_16>, - <&pm6150_vadc ADC_USB_IN_I>, - <&pm6150_vadc ADC_CHG_TEMP>, - <&pm6150_vadc ADC_DIE_TEMP>, - <&pm6150_vadc ADC_AMUX_THM3_PU2>, - <&pm6150_vadc ADC_SBUx>, - <&pm6150_vadc ADC_VPH_PWR>; - io-channel-names = "usb_in_voltage", - "usb_in_current", - "chg_temp", - "die_temp", - "conn_temp", - "sbux_res", - "vph_voltage"; - qcom,battery-data = <&mtp_batterydata>; - qcom,auto-recharge-soc = <98>; - qcom,step-charging-enable; - qcom,sw-jeita-enable; - qcom,fcc-stepping-enable; - qcom,suspend-input-on-debug-batt; - qcom,sec-charger-config = <3>; - qcom,thermal-mitigation = <4200000 3500000 3000000 - 2500000 2000000 1500000 1000000 500000>; - dpdm-supply = <&qusb_phy0>; - qcom,charger-temp-max = <800>; - qcom,smb-temp-max = <800>; -}; - -&pm6150l_gpios { - key_vol_up { - key_vol_up_default: key_vol_up_default { - pins = "gpio2"; - function = "normal"; - input-enable; - bias-pull-up; - power-source = <0>; - }; - }; -}; - -&soc { - gpio_keys { - compatible = "gpio-keys"; - label = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&key_vol_up_default>; - - vol_up { - label = "volume_up"; - gpios = <&pm6150l_gpios 2 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - linux,can-disable; - debounce-interval = <15>; - gpio-key,wakeup; - }; - }; -}; - -&qupv3_se7_i2c { - status = "ok"; - - synaptics_tcm@20 { - compatible = "synaptics,tcm-i2c"; - reg = <0x20>; - interrupt-parent = <&tlmm>; - interrupts = <9 0x2008>; - pinctrl-names = "pmx_ts_active","pmx_ts_suspend", - "pmx_ts_release"; - pinctrl-0 = <&ts_active>; - pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; - pinctrl-2 = <&ts_release>; - vdd-supply = <&pm6150_l10>; - avdd-supply = <&pm6150l_l7>; - synaptics,pwr-reg-name = "avdd"; - synaptics,bus-reg-name = "vdd"; - synaptics,irq-gpio = <&tlmm 9 0x2008>; - synaptics,irq-on-state = <0>; - synaptics,reset-gpio = <&tlmm 8 0x00>; - synaptics,reset-on-state = <0>; - synaptics,reset-active-ms = <20>; - synaptics,reset-delay-ms = <200>; - synaptics,power-delay-ms = <200>; - synaptics,ubl-i2c-addr = <0x20>; - }; -}; - -&dsi_rm69299_visionox_amoled_video { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb_amoled>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <255>; - qcom,platform-te-gpio = <&tlmm 10 0>; - qcom,platform-reset-gpio = <&pm6150l_gpios 3 0>; -}; - -&qupv3_se0_i2c { - status = "ok"; - qcom,clk-freq-out = <1000000>; - #address-cells = <1>; - #size-cells = <0>; - nq@28 { - compatible = "qcom,nq-nci"; - reg = <0x28>; - qcom,nq-irq = <&tlmm 37 0x00>; - qcom,nq-ven = <&tlmm 12 0x00>; - qcom,nq-firm = <&tlmm 36 0x00>; - qcom,nq-clkreq = <&tlmm 31 0x00>; - interrupt-parent = <&tlmm>; - interrupts = <37 0>; - interrupt-names = "nfc_irq"; - pinctrl-names = "nfc_active", "nfc_suspend"; - pinctrl-0 = <&nfc_int_active &nfc_enable_active - &nfc_clk_req_active>; - pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend - &nfc_clk_req_suspend>; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/atoll-ion.dtsi b/arch/arm64/boot/dts/qcom/atoll-ion.dtsi index 533574d8ff0406a3f55b2c5397db5e64fd00277c..fa7262d64552f1b0c72efff8b5b2746d93bce3bb 100644 --- a/arch/arm64/boot/dts/qcom/atoll-ion.dtsi +++ b/arch/arm64/boot/dts/qcom/atoll-ion.dtsi @@ -27,12 +27,6 @@ qcom,ion-heap-type = "DMA"; }; - qcom,ion-heap@19 { /* QSEECOM TA HEAP */ - reg = <19>; - memory-region = <&qseecom_ta_mem>; - qcom,ion-heap-type = "DMA"; - }; - qcom,ion-heap@9 { reg = <9>; qcom,ion-heap-type = "SYSTEM_SECURE"; @@ -43,14 +37,5 @@ memory-region = <&secure_display_memory>; qcom,ion-heap-type = "HYP_CMA"; }; - - qcom,ion-heap@14 { /* SECURE CARVEOUT HEAP */ - reg = <14>; - qcom,ion-heap-type = "SECURE_CARVEOUT"; - cdsp { - memory-region = <&cdsp_sec_mem>; - token = <0x20000000>; - }; - }; }; }; diff --git a/arch/arm64/boot/dts/qcom/atoll-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/atoll-pinctrl.dtsi index 99472bb0be26b4e4c3d772f717ea963ae486e9a8..328f975d136b0efb0f1d1483a1b2551d2886bee9 100644 --- a/arch/arm64/boot/dts/qcom/atoll-pinctrl.dtsi +++ b/arch/arm64/boot/dts/qcom/atoll-pinctrl.dtsi @@ -218,864 +218,6 @@ }; }; - qupv3_se0_spi_pins: qupv3_se0_spi_pins { - qupv3_se0_spi_active: qupv3_se0_spi_active { - mux { - pins = "gpio34", "gpio35", - "gpio36", "gpio37"; - function = "qup00"; - }; - - config { - pins = "gpio34", "gpio35", - "gpio36", "gpio37"; - drive-strength = <6>; - bias-disable; - }; - }; - - qupv3_se0_spi_sleep: qupv3_se0_spi_sleep { - mux { - pins = "gpio34", "gpio35", - "gpio36", "gpio37"; - function = "gpio"; - }; - - config { - pins = "gpio34", "gpio35", - "gpio36", "gpio37"; - drive-strength = <6>; - bias-disable; - }; - }; - }; - - qupv3_se1_spi_pins: qupv3_se1_spi_pins { - qupv3_se1_spi_active: qupv3_se1_spi_active { - mux { - pins = "gpio0", "gpio1", - "gpio2", "gpio3"; - function = "qup01"; - }; - - config { - pins = "gpio0", "gpio1", - "gpio2", "gpio3"; - drive-strength = <6>; - bias-disable; - }; - }; - - qupv3_se1_spi_sleep: qupv3_se1_spi_sleep { - mux { - pins = "gpio0", "gpio1", - "gpio2", "gpio3"; - function = "gpio"; - }; - - config { - pins = "gpio0", "gpio1", - "gpio2", "gpio3"; - drive-strength = <6>; - bias-disable; - }; - }; - }; - - qupv3_se3_spi_pins: qupv3_se3_spi_pins { - qupv3_se3_spi_active: qupv3_se3_spi_active { - mux { - pins = "gpio38", "gpio39", - "gpio40 ", "gpio41"; - function = "qup03"; - }; - - config { - pins = "gpio38", "gpio39", - "gpio40 ", "gpio41"; - drive-strength = <6>; - bias-disable; - }; - }; - - qupv3_se3_spi_sleep: qupv3_se3_spi_sleep { - mux { - pins = "gpio38", "gpio39", - "gpio40 ", "gpio41"; - function = "gpio"; - }; - - config { - pins = "gpio38", "gpio39", - "gpio40 ", "gpio41"; - drive-strength = <6>; - bias-disable; - }; - }; - }; - - qupv3_se5_spi_pins: qupv3_se5_spi_pins { - qupv3_se5_spi_active: qupv3_se5_spi_active { - mux { - pins = "gpio25", "gpio26", - "gpio27", "gpio28"; - function = "qup05"; - }; - - config { - pins = "gpio25", "gpio26", - "gpio27", "gpio28"; - drive-strength = <6>; - bias-disable; - }; - }; - - qupv3_se5_spi_sleep: qupv3_se5_spi_sleep { - mux { - pins = "gpio25", "gpio26", - "gpio27", "gpio28"; - function = "gpio"; - }; - - config { - pins = "gpio25", "gpio26", - "gpio27", "gpio28"; - drive-strength = <6>; - bias-disable; - }; - }; - }; - - qupv3_se0_i2c_pins: qupv3_se0_i2c_pins { - qupv3_se0_i2c_active: qupv3_se0_i2c_active { - mux { - pins = "gpio34", "gpio35"; - function = "qup00"; - }; - - config { - pins = "gpio34", "gpio35"; - drive-strength = <2>; - bias-disable; - }; - }; - - qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep { - mux { - pins = "gpio34", "gpio35"; - function = "gpio"; - }; - - config { - pins = "gpio34", "gpio35"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - nfc { - nfc_int_active: nfc_int_active { - /* active state */ - mux { - /* GPIO 37 NFC Read Interrupt */ - pins = "gpio37"; - function = "gpio"; - }; - - config { - pins = "gpio37"; - drive-strength = <2>; /* 2 MA */ - bias-pull-up; - }; - }; - - nfc_int_suspend: nfc_int_suspend { - /* sleep state */ - mux { - /* GPIO 37 NFC Read Interrupt */ - pins = "gpio37"; - function = "gpio"; - }; - - config { - pins = "gpio37"; - drive-strength = <2>; /* 2 MA */ - bias-pull-up; - }; - }; - - nfc_enable_active: nfc_enable_active { - /* active state */ - mux { - /* 12: Enable 36: Firmware */ - pins = "gpio12", "gpio36"; - function = "gpio"; - }; - - config { - pins = "gpio12", "gpio36"; - drive-strength = <2>; /* 2 MA */ - bias-pull-up; - }; - }; - - nfc_enable_suspend: nfc_enable_suspend { - /* sleep state */ - mux { - /* 12: Enable 36: Firmware */ - pins = "gpio12", "gpio36"; - function = "gpio"; - }; - - config { - pins = "gpio12", "gpio36"; - drive-strength = <2>; /* 2 MA */ - bias-disable; - }; - }; - - nfc_clk_req_active: nfc_clk_req_active { - /* active state */ - mux { - /* GPIO 31: NFC CLOCK REQUEST */ - pins = "gpio31"; - function = "gpio"; - }; - - config { - pins = "gpio31"; - drive-strength = <2>; /* 2 MA */ - bias-pull-up; - }; - }; - - nfc_clk_req_suspend: nfc_clk_req_suspend { - /* sleep state */ - mux { - /* GPIO 31: NFC CLOCK REQUEST */ - pins = "gpio31"; - function = "gpio"; - }; - - config { - pins = "gpio31"; - drive-strength = <2>; /* 2 MA */ - bias-disable; - }; - }; - }; - - qupv3_se1_i2c_pins: qupv3_se1_i2c_pins { - qupv3_se1_i2c_active: qupv3_se1_i2c_active { - mux { - pins = "gpio0", "gpio1"; - function = "qup01"; - }; - - config { - pins = "gpio0", "gpio1"; - drive-strength = <2>; - bias-disable; - }; - }; - - qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep { - mux { - pins = "gpio0", "gpio1"; - function = "gpio"; - }; - - config { - pins = "gpio0", "gpio1"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - qupv3_se2_i2c_pins: qupv3_se2_i2c_pins { - qupv3_se2_i2c_active: qupv3_se2_i2c_active { - mux { - pins = "gpio15", "gpio16"; - function = "qup02"; - }; - - config { - pins = "gpio15", "gpio16"; - drive-strength = <2>; - bias-disable; - }; - }; - - qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep { - mux { - pins = "gpio15", "gpio16"; - function = "gpio"; - }; - - config { - pins = "gpio15", "gpio16"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - qupv3_se3_i2c_pins: qupv3_se3_i2c_pins { - qupv3_se3_i2c_active: qupv3_se3_i2c_active { - mux { - pins = "gpio38", "gpio39"; - function = "qup03"; - }; - - config { - pins = "gpio38", "gpio39"; - drive-strength = <2>; - bias-disable; - }; - }; - - qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep { - mux { - pins = "gpio38", "gpio39"; - function = "gpio"; - }; - - config { - pins = "gpio38", "gpio39"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - qupv3_se4_i2c_pins: qupv3_se4_i2c_pins { - qupv3_se4_i2c_active: qupv3_se4_i2c_active { - mux { - pins = "gpio115", "gpio116"; - function = "qup04"; - }; - - config { - pins = "gpio115", "gpio116"; - drive-strength = <2>; - bias-disable; - }; - }; - - qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep { - mux { - pins = "gpio115", "gpio116"; - function = "gpio"; - }; - - config { - pins = "gpio115", "gpio116"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - qupv3_se5_i2c_pins: qupv3_se5_i2c_pins { - qupv3_se5_i2c_active: qupv3_se5_i2c_active { - mux { - pins = "gpio25", "gpio26"; - function = "qup05"; - }; - - config { - pins = "gpio25", "gpio26"; - drive-strength = <2>; - bias-disable; - }; - }; - - qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep { - mux { - pins = "gpio25", "gpio26"; - function = "gpio"; - }; - - config { - pins = "gpio25", "gpio26"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - qupv3_se3_4uart_pins: qupv3_se3_4uart_pins { - qupv3_se3_default_ctsrtsrx: - qupv3_se3_default_ctsrtsrx { - mux { - pins = "gpio38", "gpio39", - "gpio41"; - function = "gpio"; - }; - - config { - pins = "gpio38", "gpio39", - "gpio41"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - qupv3_se3_default_tx: qupv3_se3_default_tx { - mux { - pins = "gpio40"; - function = "gpio"; - }; - - config { - pins = "gpio40"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - qupv3_se3_ctsrx: qupv3_se3_ctsrx { - mux { - pins = "gpio38", "gpio41"; - function = "qup03"; - }; - - config { - pins = "gpio38", "gpio41"; - drive-strength = <2>; - bias-disable; - }; - }; - - qupv3_se3_rts: qupv3_se3_rts { - mux { - pins = "gpio39"; - function = "qup03"; - }; - - config { - pins = "gpio39"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - qupv3_se3_tx: qupv3_se3_tx { - mux { - pins = "gpio40"; - function = "qup03"; - }; - - config { - pins = "gpio40"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - qupv3_se6_spi_pins: qupv3_se6_spi_pins { - qupv3_se6_spi_active: qupv3_se6_spi_active { - mux { - pins = "gpio59", "gpio60", - "gpio61", "gpio62"; - function = "qup10"; - }; - - config { - pins = "gpio59", "gpio60", - "gpio61", "gpio62"; - drive-strength = <6>; - bias-disable; - }; - }; - - qupv3_se6_spi_sleep: qupv3_se6_spi_sleep { - mux { - pins = "gpio59", "gpio60", - "gpio61", "gpio62"; - function = "gpio"; - }; - - config { - pins = "gpio59", "gpio60", - "gpio61", "gpio62"; - drive-strength = <6>; - bias-disable; - }; - }; - }; - - qupv3_se8_spi_pins: qupv3_se8_spi_pins { - qupv3_se8_spi_active: qupv3_se8_spi_active { - mux { - pins = "gpio42", "gpio43", - "gpio44", "gpio45"; - function = "qup12"; - }; - - config { - pins = "gpio42", "gpio43", - "gpio44", "gpio45"; - drive-strength = <6>; - bias-disable; - }; - }; - - qupv3_se8_spi_sleep: qupv3_se8_spi_sleep { - mux { - pins = "gpio42", "gpio43", - "gpio44", "gpio45"; - function = "gpio"; - }; - - config { - pins = "gpio42", "gpio43", - "gpio44", "gpio45"; - drive-strength = <6>; - bias-disable; - }; - }; - }; - - qupv3_se10_spi_pins: qupv3_se10_spi_pins { - qupv3_se10_spi_active: qupv3_se10_spi_active { - mux { - pins = "gpio86", "gpio87", - "gpio88 ", "gpio89"; - function = "qup14"; - }; - - config { - pins = "gpio86", "gpio87", - "gpio88 ", "gpio89"; - drive-strength = <6>; - bias-disable; - }; - }; - - qupv3_se10_spi_sleep: qupv3_se10_spi_sleep { - mux { - pins = "gpio86", "gpio87", - "gpio88 ", "gpio89"; - function = "gpio"; - }; - - config { - pins = "gpio86", "gpio87", - "gpio88 ", "gpio89"; - drive-strength = <6>; - bias-disable; - }; - }; - }; - - qupv3_se11_spi_pins: qupv3_se11_spi_pins { - qupv3_se11_spi_active: qupv3_se11_spi_active { - mux { - pins = "gpio53", "gpio54", - "gpio55", "gpio56"; - function = "qup15"; - }; - - config { - pins = "gpio53", "gpio54", - "gpio55", "gpio56"; - drive-strength = <6>; - bias-disable; - }; - }; - - qupv3_se11_spi_sleep: qupv3_se11_spi_sleep { - mux { - pins = "gpio53", "gpio54", - "gpio55", "gpio56"; - function = "gpio"; - }; - - config { - pins = "gpio53", "gpio54", - "gpio55", "gpio56"; - drive-strength = <6>; - bias-disable; - }; - }; - }; - - qupv3_se6_i2c_pins: qupv3_se6_i2c_pins { - qupv3_se6_i2c_active: qupv3_se6_i2c_active { - mux { - pins = "gpio59", "gpio60"; - function = "qup10"; - }; - - config { - pins = "gpio59", "gpio60"; - drive-strength = <2>; - bias-disable; - }; - }; - - qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep { - mux { - pins = "gpio59", "gpio60"; - function = "gpio"; - }; - - config { - pins = "gpio59", "gpio60"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - qupv3_se7_i2c_pins: qupv3_se7_i2c_pins { - qupv3_se7_i2c_active: qupv3_se7_i2c_active { - mux { - pins = "gpio6", "gpio7"; - function = "qup11"; - }; - - config { - pins = "gpio6", "gpio7"; - drive-strength = <2>; - bias-disable; - }; - }; - - qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep { - mux { - pins = "gpio6", "gpio7"; - function = "gpio"; - }; - - config { - pins = "gpio6", "gpio7"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - qupv3_se8_i2c_pins: qupv3_se8_i2c_pins { - qupv3_se8_i2c_active: qupv3_se8_i2c_active { - mux { - pins = "gpio42", "gpio43"; - function = "qup12"; - }; - - config { - pins = "gpio42", "gpio43"; - drive-strength = <2>; - bias-disable; - }; - }; - - qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep { - mux { - pins = "gpio42", "gpio43"; - function = "gpio"; - }; - - config { - pins = "gpio42", "gpio43"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - qupv3_se9_i2c_pins: qupv3_se9_i2c_pins { - qupv3_se9_i2c_active: qupv3_se9_i2c_active { - mux { - pins = "gpio46", "gpio47"; - function = "qup13"; - }; - - config { - pins = "gpio46", "gpio47"; - drive-strength = <2>; - bias-disable; - }; - }; - - qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep { - mux { - pins = "gpio46", "gpio47"; - function = "gpio"; - }; - - config { - pins = "gpio46", "gpio47"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - qupv3_se10_i2c_pins: qupv3_se10_i2c_pins { - qupv3_se10_i2c_active: qupv3_se10_i2c_active { - mux { - pins = "gpio86", "gpio87"; - function = "qup14"; - }; - - config { - pins = "gpio86", "gpio87"; - drive-strength = <2>; - bias-disable; - }; - }; - - qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep { - mux { - pins = "gpio86", "gpio87"; - function = "gpio"; - }; - - config { - pins = "gpio86", "gpio87"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - qupv3_se11_i2c_pins: qupv3_se11_i2c_pins { - qupv3_se11_i2c_active: qupv3_se11_i2c_active { - mux { - pins = "gpio53", "gpio54"; - function = "qup15"; - }; - - config { - pins = "gpio53", "gpio54"; - drive-strength = <2>; - bias-disable; - }; - }; - - qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep { - mux { - pins = "gpio53", "gpio54"; - function = "gpio"; - }; - - config { - pins = "gpio53", "gpio54"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - fsa_usbc_ana_en_n@33 { - fsa_usbc_ana_en: fsa_usbc_ana_en { - mux { - pins = "gpio33"; - function = "gpio"; - }; - - config { - pins = "gpio33"; - drive-strength = <2>; - bias-disable; - output-low; - }; - }; - }; - - /* WSA speaker reset pins */ - spkr_1_sd_n { - spkr_1_sd_n_sleep: spkr_1_sd_n_sleep { - mux { - pins = "gpio51"; - function = "gpio"; - }; - - config { - pins = "gpio51"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; - input-enable; - }; - }; - - spkr_1_sd_n_active: spkr_1_sd_n_active { - mux { - pins = "gpio51"; - function = "gpio"; - }; - - config { - pins = "gpio51"; - drive-strength = <16>; /* 16 mA */ - bias-disable; - output-high; - }; - }; - }; - - spkr_2_sd_n { - spkr_2_sd_n_sleep: spkr_2_sd_n_sleep { - mux { - pins = "gpio52"; - function = "gpio"; - }; - - config { - pins = "gpio52"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; - input-enable; - }; - }; - - spkr_2_sd_n_active: spkr_2_sd_n_active { - mux { - pins = "gpio52"; - function = "gpio"; - }; - - config { - pins = "gpio52"; - drive-strength = <16>; /* 16 mA */ - bias-disable; - output-high; - }; - }; - }; - - wcd_reset_active: wcd_reset_active { - mux { - pins = "gpio58"; - function = "gpio"; - }; - - config { - pins = "gpio58"; - drive-strength = <16>; - output-high; - }; - }; - - wcd_reset_sleep: wcd_reset_sleep { - mux { - pins = "gpio58"; - function = "gpio"; - }; - - config { - pins = "gpio58"; - drive-strength = <16>; - bias-disable; - output-low; - }; - }; - qupv3_se8_2uart_pins: qupv3_se8_2uart_pins { qupv3_se8_2uart_active: qupv3_se8_2uart_active { mux { @@ -1104,445 +246,5 @@ }; }; - cci0_active: cci0_active { - mux { - /* CLK, DATA */ - pins = "gpio17", "gpio18"; - function = "cci_i2c"; - }; - - config { - pins = "gpio17", "gpio18"; - bias-pull-up; /* PULL UP*/ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cci0_suspend: cci0_suspend { - mux { - /* CLK, DATA */ - pins = "gpio17", "gpio18"; - function = "cci_i2c"; - }; - - config { - pins = "gpio17", "gpio18"; - bias-pull-down; /* PULL DOWN */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cci1_active: cci1_active { - mux { - /* CLK, DATA */ - pins = "gpio19", "gpio20"; - function = "cci_i2c"; - }; - - config { - pins = "gpio19", "gpio20"; - bias-pull-up; /* PULL UP*/ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cci1_suspend: cci1_suspend { - mux { - /* CLK, DATA */ - pins = "gpio19", "gpio20"; - function = "cci_i2c"; - }; - - config { - pins = "gpio19", "gpio20"; - bias-pull-down; /* PULL DOWN */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cci2_active: cci2_active { - mux { - /* CLK, DATA */ - pins = "gpio27", "gpio28"; - function = "cci_i2c"; - }; - - config { - pins = "gpio27", "gpio28"; - bias-pull-up; /* PULL UP*/ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cci2_suspend: cci2_suspend { - mux { - /* CLK, DATA */ - pins = "gpio27", "gpio28"; - function = "cci_i2c"; - }; - - config { - pins = "gpio27", "gpio28"; - bias-pull-down; /* PULL DOWN */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cam_sensor_mclk0_active: cam_sensor_mclk0_active { - /* MCLK0 */ - mux { - pins = "gpio13"; - function = "cam_mclk"; - }; - - config { - pins = "gpio13"; - bias-disable; /* No PULL */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend { - /* MCLK0 */ - mux { - pins = "gpio13"; - function = "cam_mclk"; - }; - - config { - pins = "gpio13"; - bias-pull-down; /* PULL DOWN */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cam_sensor_rear_active: cam_sensor_rear_active { - /* RESET */ - mux { - pins = "gpio30"; - function = "gpio"; - }; - - config { - pins = "gpio30"; - bias-disable; /* No PULL */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cam_sensor_rear_suspend: cam_sensor_rear_suspend { - /* RESET */ - mux { - pins = "gpio30"; - function = "gpio"; - }; - - config { - pins = "gpio30"; - bias-pull-down; /* PULL DOWN */ - drive-strength = <2>; /* 2 MA */ - output-low; - }; - }; - - cam_sensor_front_active: cam_sensor_front_active { - /* RESET */ - mux { - pins = "gpio29"; - function = "gpio"; - }; - - config { - pins = "gpio29"; - bias-disable; /* No PULL */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cam_sensor_front_suspend: cam_sensor_front_suspend { - /* RESET */ - mux { - pins = "gpio29"; - function = "gpio"; - }; - - config { - pins = "gpio29"; - bias-pull-down; /* PULL DOWN */ - drive-strength = <2>; /* 2 MA */ - output-low; - }; - }; - - cam_sensor_rear2_active: cam_sensor_rear2_active { - /* RESET */ - mux { - pins = "gpio25"; - function = "gpio"; - }; - - config { - pins = "gpio25"; - bias-disable; /* No PULL */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cam_sensor_rear2_suspend: cam_sensor_rear2_suspend { - /* RESET */ - mux { - pins = "gpioi25"; - function = "gpio"; - }; - - config { - pins = "gpio25"; - bias-pull-down; /* PULL DOWN */ - drive-strength = <2>; /* 2 MA */ - output-low; - }; - }; - - cam_sensor_tof_active: cam_sensor_tof_active { - /* RESET */ - mux { - pins = "gpio24"; - function = "gpio"; - }; - - config { - pins = "gpio24"; - bias-disable; /* No PULL */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cam_sensor_tof_suspend: cam_sensor_tof_suspend { - /* RESET */ - mux { - pins = "gpio24"; - function = "gpio"; - }; - - config { - pins = "gpio24"; - bias-pull-down; /* PULL DOWN */ - drive-strength = <2>; /* 2 MA */ - output-low; - }; - }; - - cam_sensor_mclk1_active: cam_sensor_mclk1_active { - /* MCLK1 */ - mux { - pins = "gpio14"; - function = "cam_mclk"; - }; - - config { - pins = "gpio14"; - bias-disable; /* No PULL */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend { - /* MCLK1 */ - mux { - pins = "gpio14"; - function = "cam_mclk"; - }; - - config { - pins = "gpio14"; - bias-pull-down; /* PULL DOWN */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cam_sensor_mclk2_active: cam_sensor_mclk2_active { - /* MCLK2 */ - mux { - pins = "gpio15"; - function = "cam_mclk"; - }; - - config { - pins = "gpio15"; - bias-disable; /* No PULL */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend { - /* MCLK2 */ - mux { - pins = "gpio15"; - function = "cam_mclk"; - }; - - config { - pins = "gpio15"; - bias-pull-down; /* PULL DOWN */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cam_sensor_mclk3_active: cam_sensor_mclk3_active { - /* MCLK3 */ - mux { - pins = "gpio16"; - function = "cam_mclk"; - }; - - config { - pins = "gpio16"; - bias-disable; /* No PULL */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cam_sensor_mclk3_suspend: cam_sensor_mclk3_suspend { - /* MCLK3 */ - mux { - pins = "gpio16"; - function = "cam_mclk"; - }; - - config { - pins = "gpio16"; - bias-pull-down; /* PULL DOWN */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cam_sensor_mclk4_active: cam_sensor_mclk4_active { - /* MCLK4 */ - mux { - pins = "gpio23"; - function = "cam_mclk"; - }; - - config { - pins = "gpio23"; - bias-disable; /* No PULL */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cam_sensor_mclk4_suspend: cam_sensor_mclk4_suspend { - /* MCLK4 */ - mux { - pins = "gpio23"; - function = "cam_mclk"; - }; - - config { - pins = "gpio23"; - bias-pull-down; /* PULL DOWN */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - pmx_sde_te { - sde_te_active: sde_te_active { - mux { - pins = "gpio10"; - function = "mdp_vsync"; - }; - - config { - pins = "gpio10"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - }; - }; - - sde_te_suspend: sde_te_suspend { - mux { - pins = "gpio10"; - function = "mdp_vsync"; - }; - - config { - pins = "gpio10"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - }; - }; - }; - - pmx_ts_active { - ts_active: ts_active { - mux { - pins = "gpio8", "gpio9"; - function = "gpio"; - }; - - config { - pins = "gpio8", "gpio9"; - drive-strength = <8>; - bias-pull-up; - }; - }; - }; - - pmx_ts_int_suspend { - ts_int_suspend: ts_int_suspend { - mux { - pins = "gpio9"; - function = "gpio"; - }; - - config { - pins = "gpio9"; - drive-strength = <2>; - bias-disable; - }; - }; - }; - - pmx_ts_reset_suspend { - ts_reset_suspend: ts_reset_suspend { - mux { - pins = "gpio8"; - function = "gpio"; - }; - - config { - pins = "gpio8"; - drive-strength = <2>; - bias-disable; - }; - }; - }; - - pmx_ts_release { - ts_release: ts_release { - mux { - pins = "gpio9", "gpio8"; - function = "gpio"; - }; - - config { - pins = "gpio9", "gpio8"; - drive-strength = <2>; - bias-disable; - }; - }; - }; - }; -}; - -&pm6150l_gpios { - disp_pins { - disp_pins_default: disp_pins_default{ - pins = "gpio3"; - function = "func1"; - qcom,drive-strength = <2>; - power-source = <0>; - bias-disable; - output-low; - }; }; }; diff --git a/arch/arm64/boot/dts/qcom/atoll-qrd.dtsi b/arch/arm64/boot/dts/qcom/atoll-qrd.dtsi index 1f92d08e239ab9176e09c772abdae60f7e9fc639..9132ac26e6354461fb6b3f91561bdbc18d50fbf6 100644 --- a/arch/arm64/boot/dts/qcom/atoll-qrd.dtsi +++ b/arch/arm64/boot/dts/qcom/atoll-qrd.dtsi @@ -10,291 +10,5 @@ * GNU General Public License for more details. */ -#include -#include -#include -#include -#include "atoll-audio-overlay.dtsi" - -#include "atoll-camera-sensor-qrd.dtsi" - &soc { - qrd_batterydata: qcom,battery-data { - qcom,batt-id-range-pct = <15>; - #include "qg-batterydata-atl466271_3300mAh.dtsi" - }; -}; - -&pm6150a_amoled { - status = "ok"; -}; - -&pm6150_qg { - qcom,battery-data = <&qrd_batterydata>; - qcom,qg-iterm-ma = <100>; - qcom,hold-soc-while-full; - qcom,linearize-soc; - qcom,cl-feedback-on; -}; - -&pm6150_charger { - io-channels = <&pm6150_vadc ADC_USB_IN_V_16>, - <&pm6150_vadc ADC_USB_IN_I>, - <&pm6150_vadc ADC_CHG_TEMP>, - <&pm6150_vadc ADC_DIE_TEMP>, - <&pm6150_vadc ADC_AMUX_THM3_PU2>, - <&pm6150_vadc ADC_SBUx>, - <&pm6150_vadc ADC_VPH_PWR>; - io-channel-names = "usb_in_voltage", - "usb_in_current", - "chg_temp", - "die_temp", - "conn_temp", - "sbux_res", - "vph_voltage"; - qcom,battery-data = <&qrd_batterydata>; - qcom,auto-recharge-soc = <98>; - qcom,step-charging-enable; - qcom,sw-jeita-enable; - qcom,fcc-stepping-enable; - qcom,suspend-input-on-debug-batt; - qcom,sec-charger-config = <3>; - qcom,thermal-mitigation = <4200000 3500000 3000000 - 2500000 2000000 1500000 1000000 500000>; - dpdm-supply = <&qusb_phy0>; - qcom,charger-temp-max = <800>; - qcom,smb-temp-max = <800>; -}; - -&pm6150l_gpios { - key_vol_up { - key_vol_up_default: key_vol_up_default { - pins = "gpio2"; - function = "normal"; - input-enable; - bias-pull-up; - power-source = <0>; - }; - }; -}; - -&soc { - gpio_keys { - compatible = "gpio-keys"; - label = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&key_vol_up_default>; - - vol_up { - label = "volume_up"; - gpios = <&pm6150l_gpios 2 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - linux,can-disable; - debounce-interval = <15>; - gpio-key,wakeup; - }; - - }; -}; - -&qupv3_se7_i2c { - status = "ok"; - - synaptics_tcm@20 { - compatible = "synaptics,tcm-i2c"; - reg = <0x20>; - interrupt-parent = <&tlmm>; - interrupts = <9 0x2008>; - pinctrl-names = "pmx_ts_active","pmx_ts_suspend", - "pmx_ts_release"; - pinctrl-0 = <&ts_active>; - pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; - pinctrl-2 = <&ts_release>; - vdd-supply = <&pm6150_l10>; - avdd-supply = <&pm6150l_l7>; - synaptics,pwr-reg-name = "avdd"; - synaptics,bus-reg-name = "vdd"; - synaptics,irq-gpio = <&tlmm 9 0x2008>; - synaptics,irq-on-state = <0>; - synaptics,reset-gpio = <&tlmm 8 0x00>; - synaptics,reset-on-state = <0>; - synaptics,reset-active-ms = <20>; - synaptics,reset-delay-ms = <200>; - synaptics,power-delay-ms = <200>; - synaptics,ubl-i2c-addr = <0x20>; - }; -}; - -&ufsphy_mem { - compatible = "qcom,ufs-phy-qmp-v3"; - - vdda-phy-supply = <&pm6150_l4>; /* 0.9v */ - vdda-pll-supply = <&pm6150l_l3>; /* 1.2v */ - vdda-phy-max-microamp = <62900>; - vdda-pll-max-microamp = <18300>; - - status = "ok"; -}; - -&ufshc_mem { - vdd-hba-supply = <&ufs_phy_gdsc>; - vdd-hba-fixed-regulator; - vcc-supply = <&pm6150_l19>; - vcc-voltage-level = <2960000 2960000>; - vcc-max-microamp = <600000>; - vccq2-supply = <&pm6150_l12>; - vccq2-voltage-level = <1750000 1950000>; - vccq2-max-microamp = <600000>; - - qcom,vddp-ref-clk-supply = <&pm6150l_l3>; /* PX10 */ - qcom,vddp-ref-clk-max-microamp = <100>; - - status = "ok"; -}; - -&sdhc_1 { - vdd-supply = <&pm6150_l19>; - qcom,vdd-voltage-level = <2960000 2960000>; - qcom,vdd-current-level = <0 570000>; - - vdd-io-supply = <&pm6150_l12>; - qcom,vdd-io-always-on; - qcom,vdd-io-lpm-sup; - qcom,vdd-io-voltage-level = <1800000 1800000>; - qcom,vdd-io-current-level = <0 325000>; - - pinctrl-names = "active", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; - - status = "ok"; -}; - -&sdhc_2 { - vdd-supply = <&pm6150l_l9>; - qcom,vdd-voltage-level = <2960000 2960000>; - qcom,vdd-current-level = <0 800000>; - - vdd-io-supply = <&pm6150l_l6>; - qcom,vdd-io-voltage-level = <1800000 2950000>; - qcom,vdd-io-current-level = <0 22000>; - - pinctrl-names = "active", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; - - cd-gpios = <&tlmm 69 GPIO_ACTIVE_HIGH>; - - status = "ok"; -}; - -&atoll_snd { - qcom,model = "atoll-qrd-snd-card"; - qcom,audio-routing = - "AMIC1", "MIC BIAS1", - "MIC BIAS1", "Analog Mic1", - "AMIC2", "MIC BIAS2", - "MIC BIAS2", "Analog Mic2", - "AMIC3", "MIC BIAS3", - "MIC BIAS3", "Analog Mic3", - "AMIC4", "MIC BIAS1", - "MIC BIAS1", "Analog Mic4", - "TX DMIC0", "MIC BIAS1", - "MIC BIAS1", "Digital Mic0", - "TX DMIC1", "MIC BIAS1", - "MIC BIAS1", "Digital Mic1", - "TX DMIC2", "MIC BIAS3", - "MIC BIAS3", "Digital Mic2", - "TX DMIC3", "MIC BIAS3", - "MIC BIAS3", "Digital Mic3", - "TX DMIC4", "MIC BIAS4", - "MIC BIAS4", "Digital Mic4", - "IN1_HPHL", "HPHL_OUT", - "IN2_HPHR", "HPHR_OUT", - "IN3_AUX", "AUX_OUT", - "TX SWR_ADC0", "ADC1_OUTPUT", - "TX SWR_ADC1", "ADC2_OUTPUT", - "TX SWR_ADC2", "ADC3_OUTPUT", - "TX SWR_ADC3", "ADC4_OUTPUT", - "TX SWR_DMIC0", "DMIC1_OUTPUT", - "TX SWR_DMIC1", "DMIC2_OUTPUT", - "TX SWR_DMIC2", "DMIC3_OUTPUT", - "TX SWR_DMIC3", "DMIC4_OUTPUT", - "TX SWR_DMIC4", "DMIC5_OUTPUT", - "TX SWR_DMIC5", "DMIC6_OUTPUT", - "TX SWR_DMIC6", "DMIC7_OUTPUT", - "TX SWR_DMIC7", "DMIC8_OUTPUT", - "WSA SRC0_INP", "SRC0", - "WSA_TX DEC0_INP", "TX DEC0 MUX", - "WSA_TX DEC1_INP", "TX DEC1 MUX", - "RX_TX DEC0_INP", "TX DEC0 MUX", - "RX_TX DEC1_INP", "TX DEC1 MUX", - "RX_TX DEC2_INP", "TX DEC2 MUX", - "RX_TX DEC3_INP", "TX DEC3 MUX", - "SpkrLeft IN", "WSA_SPK1 OUT", - "SpkrRight IN", "WSA_SPK2 OUT", - "VA MIC BIAS3", "Digital Mic0", - "VA MIC BIAS3", "Digital Mic1", - "VA MIC BIAS1", "Digital Mic2", - "VA MIC BIAS1", "Digital Mic3", - "VA MIC BIAS4", "Digital Mic4", - "VA MIC BIAS4", "Digital Mic5", - "VA DMIC0", "VA MIC BIAS3", - "VA DMIC1", "VA MIC BIAS3", - "VA DMIC2", "VA MIC BIAS1", - "VA DMIC3", "VA MIC BIAS1", - "VA DMIC4", "VA MIC BIAS4", - "VA DMIC5", "VA MIC BIAS4", - "VA SWR_ADC0", "VA_SWR_CLK", - "VA SWR_ADC1", "VA_SWR_CLK", - "VA SWR_ADC2", "VA_SWR_CLK", - "VA SWR_ADC3", "VA_SWR_CLK", - "VA SWR_MIC0", "VA_SWR_CLK", - "VA SWR_MIC1", "VA_SWR_CLK", - "VA SWR_MIC2", "VA_SWR_CLK", - "VA SWR_MIC3", "VA_SWR_CLK", - "VA SWR_MIC4", "VA_SWR_CLK", - "VA SWR_MIC5", "VA_SWR_CLK", - "VA SWR_MIC6", "VA_SWR_CLK", - "VA SWR_MIC7", "VA_SWR_CLK", - "VA SWR_ADC0", "ADC1_OUTPUT", - "VA SWR_ADC1", "ADC2_OUTPUT", - "VA SWR_ADC2", "ADC3_OUTPUT", - "VA SWR_ADC3", "ADC4_OUTPUT", - "VA SWR_MIC0", "DMIC1_OUTPUT", - "VA SWR_MIC1", "DMIC2_OUTPUT", - "VA SWR_MIC2", "DMIC3_OUTPUT", - "VA SWR_MIC3", "DMIC4_OUTPUT", - "VA SWR_MIC4", "DMIC5_OUTPUT", - "VA SWR_MIC5", "DMIC6_OUTPUT", - "VA SWR_MIC6", "DMIC7_OUTPUT", - "VA SWR_MIC7", "DMIC8_OUTPUT"; - qcom,wsa-max-devs = <1>; - qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0213>; - qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrLeft"; -}; - -&qupv3_se0_i2c { - status = "ok"; - qcom,clk-freq-out = <1000000>; - #address-cells = <1>; - #size-cells = <0>; - nq@28 { - compatible = "qcom,nq-nci"; - reg = <0x28>; - qcom,nq-irq = <&tlmm 37 0x00>; - qcom,nq-ven = <&tlmm 12 0x00>; - qcom,nq-firm = <&tlmm 36 0x00>; - qcom,nq-clkreq = <&tlmm 31 0x00>; - interrupt-parent = <&tlmm>; - interrupts = <37 0>; - interrupt-names = "nfc_irq"; - pinctrl-names = "nfc_active", "nfc_suspend"; - pinctrl-0 = <&nfc_int_active &nfc_enable_active - &nfc_clk_req_active>; - pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend - &nfc_clk_req_suspend>; - }; }; diff --git a/arch/arm64/boot/dts/qcom/atoll-qupv3.dtsi b/arch/arm64/boot/dts/qcom/atoll-qupv3.dtsi index a5075a5bc40b3528b805a40e77efb18a2ea56072..a79cdac7c492babc6573b7a98fcbac8ee85a043f 100644 --- a/arch/arm64/boot/dts/qcom/atoll-qupv3.dtsi +++ b/arch/arm64/boot/dts/qcom/atoll-qupv3.dtsi @@ -13,298 +13,27 @@ #include &soc { - /* QUPv3 North Instances - * North 0 : SE 0 - * North 1 : SE 1 - * North 2 : SE 2 - * North 3 : SE 3 - * North 4 : SE 4 - * North 5 : SE 5 - */ - qupv3_0: qcom,qupv3_0_geni_se@8c0000 { + /* QUPv3 North instances */ + qupv3_0: qcom,qupv3_0_geni_se@0x8c0000 { compatible = "qcom,qupv3-geni-se"; reg = <0x8c0000 0x2000>; - qcom,msm-bus,num-paths = <2>; - qcom,msm-bus,vectors-bus-ids = - , - ; + qcom,bus-mas-id = ; + qcom,bus-slv-id = ; qcom,iommu-s1-bypass; iommu_qupv3_0_geni_se_cb: qcom,iommu_qupv3_0_geni_se_cb { compatible = "qcom,qupv3-geni-se-cb"; - iommus = <&apps_smmu 0x43 0x0>; + iommus = <&apps_smmu 0x043 0x0>; }; }; - /* GPI */ - gpi_dma0: qcom,gpi-dma@800000 { - #dma-cells = <5>; - compatible = "qcom,gpi-dma"; - reg = <0x800000 0x60000>; - reg-names = "gpi-top"; - interrupts = <0 244 0>, <0 245 0>, <0 246 0>, <0 247 0>, - <0 248 0>, <0 249 0>, <0 250 0>, <0 251 0>, - <0 252 0>, <0 253 0>; - qcom,max-num-gpii = <10>; - qcom,gpii-mask = <0x1f>; - qcom,ev-factor = <2>; - iommus = <&apps_smmu 0x56 0x0>; - qcom,smmu-cfg = <0x1>; - qcom,gpi-ee-offset = <0x10000>; - qcom,iova-range = <0x0 0x100000 0x0 0x100000>; - status = "ok"; - }; - - /* SPI */ - qupv3_se0_spi: spi@880000 { - compatible = "qcom,spi-geni"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x880000 0x4000>; - reg-names = "se_phys"; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se0_spi_active>; - pinctrl-1 = <&qupv3_se0_spi_sleep>; - interrupts = ; - spi-max-frequency = <50000000>; - qcom,wrapper-core = <&qupv3_0>; - dmas = <&gpi_dma0 0 0 1 64 0>, - <&gpi_dma0 1 0 1 64 0>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - qupv3_se1_spi: spi@884000 { - compatible = "qcom,spi-geni"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x884000 0x4000>; - reg-names = "se_phys"; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP0_S1_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se1_spi_active>; - pinctrl-1 = <&qupv3_se1_spi_sleep>; - interrupts = ; - spi-max-frequency = <50000000>; - qcom,wrapper-core = <&qupv3_0>; - dmas = <&gpi_dma0 0 1 1 64 0>, - <&gpi_dma0 1 1 1 64 0>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - qupv3_se3_spi: spi@88c000 { - compatible = "qcom,spi-geni"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x88c000 0x4000>; - reg-names = "se_phys"; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se3_spi_active>; - pinctrl-1 = <&qupv3_se3_spi_sleep>; - interrupts = ; - spi-max-frequency = <50000000>; - qcom,wrapper-core = <&qupv3_0>; - dmas = <&gpi_dma0 0 3 1 64 0>, - <&gpi_dma0 1 3 1 64 0>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - qupv3_se5_spi: spi@894000 { - compatible = "qcom,spi-geni"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x894000 0x4000>; - reg-names = "se_phys"; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se5_spi_active>; - pinctrl-1 = <&qupv3_se5_spi_sleep>; - interrupts = ; - spi-max-frequency = <50000000>; - qcom,wrapper-core = <&qupv3_0>; - dmas = <&gpi_dma0 0 5 1 64 0>, - <&gpi_dma0 1 5 1 64 0>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - /* I2C */ - qupv3_se0_i2c: i2c@880000 { - compatible = "qcom,i2c-geni"; - reg = <0x880000 0x4000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - dmas = <&gpi_dma0 0 0 3 64 0>, - <&gpi_dma0 1 0 3 64 0>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se0_i2c_active>; - pinctrl-1 = <&qupv3_se0_i2c_sleep>; - qcom,wrapper-core = <&qupv3_0>; - status = "disabled"; - }; - - qupv3_se1_i2c: i2c@884000 { - compatible = "qcom,i2c-geni"; - reg = <0x884000 0x4000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP0_S1_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - dmas = <&gpi_dma0 0 1 3 64 0>, - <&gpi_dma0 1 1 3 64 0>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se1_i2c_active>; - pinctrl-1 = <&qupv3_se1_i2c_sleep>; - qcom,wrapper-core = <&qupv3_0>; - status = "disabled"; - }; - - qupv3_se2_i2c: i2c@888000 { - compatible = "qcom,i2c-geni"; - reg = <0x888000 0x4000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP0_S2_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - dmas = <&gpi_dma0 0 2 3 64 0>, - <&gpi_dma0 1 2 3 64 0>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se2_i2c_active>; - pinctrl-1 = <&qupv3_se2_i2c_sleep>; - qcom,wrapper-core = <&qupv3_0>; - status = "disabled"; - }; - - qupv3_se3_i2c: i2c@88c000 { - compatible = "qcom,i2c-geni"; - reg = <0x88c000 0x4000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - dmas = <&gpi_dma0 0 3 3 64 0>, - <&gpi_dma0 1 3 3 64 0>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se3_i2c_active>; - pinctrl-1 = <&qupv3_se3_i2c_sleep>; - qcom,wrapper-core = <&qupv3_0>; - status = "disabled"; - }; - - qupv3_se4_i2c: i2c@890000 { - compatible = "qcom,i2c-geni"; - reg = <0x890000 0x4000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP0_S4_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - dmas = <&gpi_dma0 0 4 3 64 0>, - <&gpi_dma0 1 4 3 64 0>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se4_i2c_active>; - pinctrl-1 = <&qupv3_se4_i2c_sleep>; - qcom,wrapper-core = <&qupv3_0>; - status = "disabled"; - }; - - qupv3_se5_i2c: i2c@894000 { - compatible = "qcom,i2c-geni"; - reg = <0x894000 0x4000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - dmas = <&gpi_dma0 0 5 3 64 0>, - <&gpi_dma0 1 5 3 64 0>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se5_i2c_active>; - pinctrl-1 = <&qupv3_se5_i2c_sleep>; - qcom,wrapper-core = <&qupv3_0>; - status = "disabled"; - }; - - /* HSUART: BT used instance */ - qupv3_se3_4uart: qcom,qup_uart@88c000 { - compatible = "qcom,msm-geni-serial-hs"; - reg = <0x88c000 0x4000>; - reg-names = "se_phys"; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - pinctrl-names = "default", "active", "sleep"; - pinctrl-0 = <&qupv3_se3_default_ctsrtsrx>, - <&qupv3_se3_default_tx>; - pinctrl-1 = <&qupv3_se3_ctsrx>, <&qupv3_se3_rts>, - <&qupv3_se3_tx>; - pinctrl-2 = <&qupv3_se3_ctsrx>, <&qupv3_se3_rts>, - <&qupv3_se3_tx>; - interrupts-extended = <&intc GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, - <&tlmm 41 IRQ_TYPE_LEVEL_HIGH>; - qcom,wrapper-core = <&qupv3_0>; - qcom,wakeup-byte = <0xFD>; - status = "disabled"; - }; - - /* QUPv3 South Instances - * South 0 : SE 6 - * South 1 : SE 7 - * South 2 : SE 8 - * South 3 : SE 9 - * South 4 : SE 10 - * South 5 : SE 11 - */ - - qupv3_1: qcom,qupv3_1_geni_se@ac0000 { + /* QUPv3 South Instances */ + qupv3_1: qcom,qupv3_1_geni_se@0xac0000 { compatible = "qcom,qupv3-geni-se"; reg = <0xac0000 0x2000>; - qcom,msm-bus,num-paths = <2>; - qcom,msm-bus,vectors-bus-ids = - , - ; + qcom,bus-mas-id = ; + qcom,bus-slv-id = ; qcom,iommu-s1-bypass; iommu_qupv3_1_geni_se_cb: qcom,iommu_qupv3_1_geni_se_cb { @@ -313,236 +42,8 @@ }; }; - /* GPI */ - gpi_dma1: qcom,gpi-dma@a00000 { - #dma-cells = <5>; - compatible = "qcom,gpi-dma"; - reg = <0xa00000 0x60000>; - reg-names = "gpi-top"; - interrupts = <0 646 0>, <0 647 0>, <0 648 0>, <0 649 0>, - <0 650 0>, <0 651 0>, <0 652 0>, <0 653 0>, - <0 654 0>, <0 655 0>; - qcom,max-num-gpii = <10>; - qcom,gpii-mask = <0x3f>; - qcom,ev-factor = <2>; - iommus = <&apps_smmu 0x4d6 0x0>; - qcom,smmu-cfg = <0x1>; - qcom,gpi-ee-offset = <0x10000>; - qcom,iova-range = <0x0 0x100000 0x0 0x100000>; - status = "ok"; - }; - - /* SPI */ - qupv3_se6_spi: spi@a80000 { - compatible = "qcom,spi-geni"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xa80000 0x4000>; - reg-names = "se_phys"; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se6_spi_active>; - pinctrl-1 = <&qupv3_se6_spi_sleep>; - interrupts = ; - spi-max-frequency = <50000000>; - qcom,wrapper-core = <&qupv3_1>; - dmas = <&gpi_dma1 0 0 1 64 0>, - <&gpi_dma1 1 0 1 64 0>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - qupv3_se8_spi: spi@a88000 { - compatible = "qcom,spi-geni"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xa88000 0x4000>; - reg-names = "se_phys"; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se8_spi_active>; - pinctrl-1 = <&qupv3_se8_spi_sleep>; - interrupts = ; - spi-max-frequency = <50000000>; - qcom,wrapper-core = <&qupv3_1>; - dmas = <&gpi_dma1 0 2 1 64 0>, - <&gpi_dma1 1 2 1 64 0>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - qupv3_se10_spi: spi@a90000 { - compatible = "qcom,spi-geni"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xa90000 0x4000>; - reg-names = "se_phys"; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se10_spi_active>; - pinctrl-1 = <&qupv3_se10_spi_sleep>; - interrupts = ; - spi-max-frequency = <50000000>; - qcom,wrapper-core = <&qupv3_1>; - dmas = <&gpi_dma1 0 4 1 64 0>, - <&gpi_dma1 1 4 1 64 0>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - qupv3_se11_spi: spi@a94000 { - compatible = "qcom,spi-geni"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xa94000 0x4000>; - reg-names = "se_phys"; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP1_S5_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se11_spi_active>; - pinctrl-1 = <&qupv3_se11_spi_sleep>; - interrupts = ; - spi-max-frequency = <50000000>; - qcom,wrapper-core = <&qupv3_1>; - dmas = <&gpi_dma1 0 5 1 64 0>, - <&gpi_dma1 1 5 1 64 0>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - /* I2C */ - qupv3_se6_i2c: i2c@a80000 { - compatible = "qcom,i2c-geni"; - reg = <0xa80000 0x4000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - dmas = <&gpi_dma1 0 0 3 64 0>, - <&gpi_dma1 1 0 3 64 0>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se6_i2c_active>; - pinctrl-1 = <&qupv3_se6_i2c_sleep>; - qcom,wrapper-core = <&qupv3_1>; - status = "disabled"; - }; - - qupv3_se7_i2c: i2c@a84000 { - compatible = "qcom,i2c-geni"; - reg = <0xa84000 0x4000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - dmas = <&gpi_dma1 0 1 3 64 0>, - <&gpi_dma1 1 1 3 64 0>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se7_i2c_active>; - pinctrl-1 = <&qupv3_se7_i2c_sleep>; - qcom,wrapper-core = <&qupv3_1>; - status = "disabled"; - }; - - qupv3_se8_i2c: i2c@a88000 { - compatible = "qcom,i2c-geni"; - reg = <0xa88000 0x4000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - dmas = <&gpi_dma1 0 2 3 64 0>, - <&gpi_dma1 1 2 3 64 0>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se8_i2c_active>; - pinctrl-1 = <&qupv3_se8_i2c_sleep>; - qcom,wrapper-core = <&qupv3_1>; - status = "disabled"; - }; - - qupv3_se9_i2c: i2c@a8c000 { - compatible = "qcom,i2c-geni"; - reg = <0xa8c000 0x4000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP1_S3_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - dmas = <&gpi_dma1 0 3 3 64 0>, - <&gpi_dma1 1 3 3 64 0>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se9_i2c_active>; - pinctrl-1 = <&qupv3_se9_i2c_sleep>; - qcom,wrapper-core = <&qupv3_1>; - status = "disabled"; - }; - - qupv3_se10_i2c: i2c@a90000 { - compatible = "qcom,i2c-geni"; - reg = <0xa90000 0x4000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - dmas = <&gpi_dma1 0 4 3 64 0>, - <&gpi_dma1 1 4 3 64 0>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se10_i2c_active>; - pinctrl-1 = <&qupv3_se10_i2c_sleep>; - qcom,wrapper-core = <&qupv3_1>; - status = "disabled"; - }; - - qupv3_se11_i2c: i2c@a94000 { - compatible = "qcom,i2c-geni"; - reg = <0xa94000 0x4000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP1_S5_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - dmas = <&gpi_dma1 0 5 3 64 0>, - <&gpi_dma1 1 5 3 64 0>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se11_i2c_active>; - pinctrl-1 = <&qupv3_se11_i2c_sleep>; - qcom,wrapper-core = <&qupv3_1>; - status = "disabled"; - }; - - qupv3_se8_2uart: qcom,qup_uart@a88000 { + /* Debug UART Instance for CDP/MTP/RUMI platform: QUPV3_1_SE2 */ + qupv3_se8_2uart: qcom,qup_uart@0xa88000 { compatible = "qcom,msm-geni-console"; reg = <0xa88000 0x4000>; reg-names = "se_phys"; @@ -553,9 +54,9 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se8_2uart_active>; pinctrl-1 = <&qupv3_se8_2uart_sleep>; - interrupts = ; + interrupts = ; qcom,wrapper-core = <&qupv3_1>; status = "disabled"; }; - }; + diff --git a/arch/arm64/boot/dts/qcom/atoll-rumi.dtsi b/arch/arm64/boot/dts/qcom/atoll-rumi.dtsi index 4ac010263b7213ae0966d356bdc6e5d1a88b2a2f..1d0c58235836a5aac7e32cf48369c3df59a3a94f 100644 --- a/arch/arm64/boot/dts/qcom/atoll-rumi.dtsi +++ b/arch/arm64/boot/dts/qcom/atoll-rumi.dtsi @@ -53,6 +53,8 @@ }; }; +#include "atoll-stub-regulator.dtsi" + &sdhc_1 { vdd-supply = <&pm6150_l19>; qcom,vdd-voltage-level = <2950000 2950000>; @@ -134,32 +136,9 @@ status = "ok"; }; -&thermal_zones { - /delete-node/ aoss-0-lowf; -}; - &usb0 { dwc3@a600000 { usb-phy = <&usb_emu_phy>, <&usb_nop_phy>; maximum-speed = "high-speed"; }; - qcom,usbbam@a704000 { - status = "disabled"; - }; -}; - -&qusb_phy0 { - status = "disabled"; -}; - -&usb_qmp_dp_phy { - status = "disabled"; -}; - -&pm6150_pdphy { - status = "disabled"; -}; - -&qupv3_se9_i2c { - status = "disabled"; }; diff --git a/arch/arm64/boot/dts/qcom/atoll-thermal.dtsi b/arch/arm64/boot/dts/qcom/atoll-thermal.dtsi index fdd8d09839fb8da2529601cb7099762dd176d982..3397ad51b4b27cdeabfb37daa38e7dcba63d5fb5 100644 --- a/arch/arm64/boot/dts/qcom/atoll-thermal.dtsi +++ b/arch/arm64/boot/dts/qcom/atoll-thermal.dtsi @@ -13,81 +13,6 @@ #include -&clock_cpucc { - #address-cells = <1>; - #size-cells = <1>; - lmh_dcvs0: qcom,limits-dcvs@18358800 { - compatible = "qcom,msm-hw-limits"; - interrupts = ; - qcom,affinity = <0>; - reg = <0x18358800 0x1000>, - <0x18323000 0x1000>; - #thermal-sensor-cells = <0>; - }; - - lmh_dcvs1: qcom,limits-dcvs@18350800 { - compatible = "qcom,msm-hw-limits"; - interrupts = ; - qcom,affinity = <1>; - reg = <0x18350800 0x1000>, - <0x18325800 0x1000>; - #thermal-sensor-cells = <0>; - }; -}; - -&soc { - qmi-tmd-devices { - compatible = "qcom,qmi-cooling-devices"; - - modem { - qcom,instance-id = <0x0>; - - modem_pa: modem_pa { - qcom,qmi-dev-name = "pa"; - #cooling-cells = <2>; - }; - - modem_proc: modem_proc { - qcom,qmi-dev-name = "modem"; - #cooling-cells = <2>; - }; - - modem_current: modem_current { - qcom,qmi-dev-name = "modem_current"; - #cooling-cells = <2>; - }; - - modem_skin: modem_skin { - qcom,qmi-dev-name = "modem_skin"; - #cooling-cells = <2>; - }; - - modem_vdd: modem_vdd { - qcom,qmi-dev-name = "cpuv_restriction_cold"; - #cooling-cells = <2>; - }; - }; - - adsp { - qcom,instance-id = <0x1>; - - adsp_vdd: adsp_vdd { - qcom,qmi-dev-name = "cpuv_restriction_cold"; - #cooling-cells = <2>; - }; - }; - - cdsp { - qcom,instance-id = <0x43>; - - cdsp_vdd: cdsp_vdd { - qcom,qmi-dev-name = "cpuv_restriction_cold"; - #cooling-cells = <2>; - }; - }; - }; -}; - &thermal_zones { aoss-0-usr { polling-delay-passive = <0>; @@ -693,335 +618,4 @@ }; }; }; - - gpuss-max-step { - polling-delay-passive = <10>; - polling-delay = <100>; - thermal-governor = "step_wise"; - wake-capable-sensor; - trips { - gpu_trip: gpu-trip { - temperature = <95000>; - hysteresis = <0>; - type = "passive"; - }; - }; - - cooling-maps { - gpu_cdev { - trip = <&gpu_trip>; - cooling-device = <&msm_gpu THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu-0-max-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "step_wise"; - wake-capable-sensor; - trips { - silver-trip { - temperature = <120000>; - hysteresis = <0>; - type = "passive"; - }; - }; - }; - - cpu-1-max-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "step_wise"; - wake-capable-sensor; - trips { - gold-trip { - temperature = <120000>; - hysteresis = <0>; - type = "passive"; - }; - }; - }; - - cpu-0-0-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&tsens0 1>; - wake-capable-sensor; - trips { - cpu0_config: cpu0-config { - temperature = <110000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - cooling-maps { - cpu0_cdev { - trip = <&cpu0_config>; - cooling-device = - <&CPU0 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - }; - }; - - cpu-0-1-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&tsens0 2>; - wake-capable-sensor; - trips { - cpu1_config: cpu1-config { - temperature = <110000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - cooling-maps { - cpu1_cdev { - trip = <&cpu1_config>; - cooling-device = - <&CPU1 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - }; - }; - - cpu-0-2-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&tsens0 3>; - wake-capable-sensor; - trips { - cpu2_config: cpu2-config { - temperature = <110000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - cooling-maps { - cpu2_cdev { - trip = <&cpu2_config>; - cooling-device = - <&CPU2 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - }; - }; - - cpu-0-3-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&tsens0 4>; - wake-capable-sensor; - trips { - cpu3_config: cpu3-config { - temperature = <110000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - cooling-maps { - cpu3_cdev { - trip = <&cpu3_config>; - cooling-device = - <&CPU3 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - }; - }; - - cpu-0-4-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&tsens0 5>; - wake-capable-sensor; - trips { - cpu4_config: cpu4-config { - temperature = <110000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - cooling-maps { - cpu4_cdev { - trip = <&cpu4_config>; - cooling-device = - <&CPU4 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - }; - }; - - cpu-0-5-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&tsens0 6>; - wake-capable-sensor; - trips { - cpu5_config: cpu5-config { - temperature = <110000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - cooling-maps { - cpu5_cdev { - trip = <&cpu5_config>; - cooling-device = - <&CPU5 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - }; - }; - - cpu-1-0-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&tsens0 9>; - wake-capable-sensor; - trips { - cpu6_0_config: cpu6-0-config { - temperature = <110000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - cooling-maps { - cpu6_cdev { - trip = <&cpu6_0_config>; - cooling-device = - <&CPU6 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - }; - }; - - cpu-1-1-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&tsens0 10>; - wake-capable-sensor; - trips { - cpu6_1_config: cpu6-1-config { - temperature = <110000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - cooling-maps { - cpu6_cdev { - trip = <&cpu6_1_config>; - cooling-device = - <&CPU6 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - }; - }; - - cpu-1-2-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&tsens0 11>; - wake-capable-sensor; - trips { - cpu7_0_config: cpu7-0-config { - temperature = <110000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - cooling-maps { - cpu7_cdev { - trip = <&cpu7_0_config>; - cooling-device = - <&CPU7 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - }; - }; - - cpu-1-3-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&tsens0 12>; - wake-capable-sensor; - trips { - cpu7_1_config: cpu7-1-config { - temperature = <110000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - cooling-maps { - cpu7_cdev { - trip = <&cpu7_1_config>; - cooling-device = - <&CPU7 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - }; - }; - - aoss-0-lowf { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "low_limits_floor"; - thermal-sensors = <&tsens0 0>; - wake-capable-sensor; - tracks-low; - trips { - aoss0_trip: aoss0-trip { - temperature = <5000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - cooling-maps { - cpu0_cdev { - trip = <&aoss0_trip>; - cooling-device = <&CPU0 2 2>; - }; - cpu1_cdev { - trip = <&aoss0_trip>; - cooling-device = <&CPU6 4 4>; - }; - gpu_vdd_cdev { - trip = <&aoss0_trip>; - cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) - (THERMAL_MAX_LIMIT-3)>; - }; - cx_vdd_cdev { - trip = <&aoss0_trip>; - cooling-device = <&cx_cdev 0 0>; - }; - mx_vdd_cdev { - trip = <&aoss0_trip>; - cooling-device = <&mx_cdev 0 0>; - }; - modem_vdd_cdev { - trip = <&aoss0_trip>; - cooling-device = <&modem_vdd 0 0>; - }; - adsp_vdd_cdev { - trip = <&aoss0_trip>; - cooling-device = <&adsp_vdd 0 0>; - }; - cdsp_vdd_cdev { - trip = <&aoss0_trip>; - cooling-device = <&cdsp_vdd 0 0>; - }; - }; - }; }; diff --git a/arch/arm64/boot/dts/qcom/atoll-usb.dtsi b/arch/arm64/boot/dts/qcom/atoll-usb.dtsi index 61d831a7509066c31c52cb810134c38df4919497..90b79a03bf55673fa9b1c4a7fdfbba9d5c41153c 100644 --- a/arch/arm64/boot/dts/qcom/atoll-usb.dtsi +++ b/arch/arm64/boot/dts/qcom/atoll-usb.dtsi @@ -54,8 +54,8 @@ 0x130 /* GSI_RING_BASE_ADDR_L */ 0x144 /* GSI_RING_BASE_ADDR_H */ 0x1a4>; /* GSI_IF_STS */ - qcom,gsi-disable-io-coherency; qcom,dwc-usb3-msm-tx-fifo-size = <21288>; + qcom,pm-qos-latency = <62>; qcom,msm-bus,name = "usb0"; qcom,msm-bus,num-cases = <4>; @@ -133,10 +133,10 @@ }; /* Primary USB port related QUSB2 PHY */ - qusb_phy0: qusb@88e3000 { + qusb_phy0: qusb@88e2000 { compatible = "qcom,qusb2phy-v2"; - reg = <0x088e3000 0x400>, - <0x00780258 0x4>, + reg = <0x088e2000 0x400>, + <0x00780200 0x4>, <0x088e7014 0x4>; reg-names = "qusb_phy_base", "efuse_addr", "refgen_north_bg_reg_addr"; @@ -365,7 +365,7 @@ usb_audio_qmi_dev { compatible = "qcom,usb-audio-qmi-dev"; - iommus = <&apps_smmu 0x100f 0x0>; + iommus = <&apps_smmu 0x1b2f 0x0>; qcom,usb-audio-stream-id = <0xf>; qcom,usb-audio-intr-num = <2>; }; diff --git a/arch/arm64/boot/dts/qcom/atoll-vidc.dtsi b/arch/arm64/boot/dts/qcom/atoll-vidc.dtsi index ec3b77ba77f218a661d49d5481c29fc5dfaaf168..24e21d0080ca38ebb5fdc8caa2e92b75c9a6fc9d 100644 --- a/arch/arm64/boot/dts/qcom/atoll-vidc.dtsi +++ b/arch/arm64/boot/dts/qcom/atoll-vidc.dtsi @@ -16,7 +16,7 @@ &soc { msm_vidc: qcom,vidc@aa00000 { - compatible = "qcom,msm-vidc", "qcom,atoll-vidc"; + compatible = "qcom,msm-vidc", "qcom,atoll"; status = "ok"; reg = <0xaa00000 0x200000>; interrupts = ; diff --git a/arch/arm64/boot/dts/qcom/atoll.dtsi b/arch/arm64/boot/dts/qcom/atoll.dtsi index e47e22d70f779be2d8be7295da879fb55a1eadcb..ef8f9ebafa090330fc7c7f7cc6c981f6f7e05903 100644 --- a/arch/arm64/boot/dts/qcom/atoll.dtsi +++ b/arch/arm64/boot/dts/qcom/atoll.dtsi @@ -13,22 +13,16 @@ #include "skeleton64.dtsi" #include #include -#include #include #include -#include +#include #include #include -#include #include -#include #include #include -#include #include -#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024)) -#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 ;} / { model = "Qualcomm Technologies, Inc. ATOLL"; compatible = "qcom,atoll"; @@ -57,8 +51,6 @@ d-cache-size = <0x8000>; i-cache-size = <0x8000>; next-level-cache = <&L2_0>; - qcom,lmh-dcvs = <&lmh_dcvs0>; - #cooling-cells = <2>; L2_0: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x10000>; @@ -74,7 +66,7 @@ L1_I_0: l1-icache { compatible = "arm,arch-cache"; - qcom,dump-size = <0x10800>; + qcom,dump-size = <0x8800>; }; L1_D_0: l1-dcache { @@ -83,7 +75,7 @@ }; L2_TLB_0: l2-tlb { - qcom,dump-size = <0x5a00>; + qcom,dump-size = <0x5000>; }; }; @@ -97,8 +89,6 @@ d-cache-size = <0x8000>; i-cache-size = <0x8000>; next-level-cache = <&L2_100>; - qcom,lmh-dcvs = <&lmh_dcvs0>; - #cooling-cells = <2>; L2_100: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x10000>; @@ -108,7 +98,7 @@ L1_I_100: l1-icache { compatible = "arm,arch-cache"; - qcom,dump-size = <0x10800>; + qcom,dump-size = <0x8800>; }; L1_D_100: l1-dcache { @@ -117,7 +107,7 @@ }; L2_TLB_100: l2-tlb { - qcom,dump-size = <0x5a00>; + qcom,dump-size = <0x5000>; }; }; @@ -132,8 +122,6 @@ d-cache-size = <0x8000>; i-cache-size = <0x8000>; next-level-cache = <&L2_200>; - qcom,lmh-dcvs = <&lmh_dcvs0>; - #cooling-cells = <2>; L2_200: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x10000>; @@ -143,7 +131,7 @@ L1_I_200: l1-icache { compatible = "arm,arch-cache"; - qcom,dump-size = <0x10800>; + qcom,dump-size = <0x8800>; }; L1_D_200: l1-dcache { @@ -152,7 +140,7 @@ }; L2_TLB_200: l2-tlb { - qcom,dump-size = <0x5a00>; + qcom,dump-size = <0x5000>; }; }; @@ -166,8 +154,6 @@ d-cache-size = <0x8000>; i-cache-size = <0x8000>; next-level-cache = <&L2_300>; - qcom,lmh-dcvs = <&lmh_dcvs0>; - #cooling-cells = <2>; L2_300: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x10000>; @@ -177,7 +163,7 @@ L1_I_300: l1-icache { compatible = "arm,arch-cache"; - qcom,dump-size = <0x10800>; + qcom,dump-size = <0x8800>; }; L1_D_300: l1-dcache { @@ -186,7 +172,7 @@ }; L2_TLB_300: l2-tlb { - qcom,dump-size = <0x5a00>; + qcom,dump-size = <0x5000>; }; }; @@ -200,8 +186,6 @@ d-cache-size = <0x8000>; i-cache-size = <0x8000>; next-level-cache = <&L2_400>; - qcom,lmh-dcvs = <&lmh_dcvs0>; - #cooling-cells = <2>; L2_400: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x10000>; @@ -211,7 +195,7 @@ L1_I_400: l1-icache { compatible = "arm,arch-cache"; - qcom,dump-size = <0x10800>; + qcom,dump-size = <0x8800>; }; L1_D_400: l1-dcache { @@ -220,7 +204,7 @@ }; L2_TLB_400: l2-tlb { - qcom,dump-size = <0x5a00>; + qcom,dump-size = <0x5000>; }; }; @@ -234,8 +218,6 @@ d-cache-size = <0x8000>; i-cache-size = <0x8000>; next-level-cache = <&L2_500>; - qcom,lmh-dcvs = <&lmh_dcvs0>; - #cooling-cells = <2>; L2_500: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x10000>; @@ -245,7 +227,7 @@ L1_I_500: l1-icache { compatible = "arm,arch-cache"; - qcom,dump-size = <0x10800>; + qcom,dump-size = <0x8800>; }; L1_D_500: l1-dcache { @@ -254,7 +236,7 @@ }; L2_TLB_500: l2-tlb { - qcom,dump-size = <0x5a00>; + qcom,dump-size = <0x5000>; }; }; @@ -268,8 +250,6 @@ d-cache-size = <0x10000>; i-cache-size = <0x10000>; next-level-cache = <&L2_600>; - qcom,lmh-dcvs = <&lmh_dcvs1>; - #cooling-cells = <2>; L2_600: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x40000>; @@ -280,7 +260,7 @@ L1_I_600: l1-icache { compatible = "arm,arch-cache"; - qcom,dump-size = <0x22000>; + qcom,dump-size = <0x11000>; }; L1_D_600: l1-dcache { @@ -311,8 +291,6 @@ d-cache-size = <0x10000>; i-cache-size = <0x10000>; next-level-cache = <&L2_700>; - qcom,lmh-dcvs = <&lmh_dcvs1>; - #cooling-cells = <2>; L2_700: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x40000>; @@ -323,7 +301,7 @@ L1_I_700: l1-icache { compatible = "arm,arch-cache"; - qcom,dump-size = <0x22000>; + qcom,dump-size = <0x11000>; }; L1_D_700: l1-dcache { @@ -484,7 +462,7 @@ compatible = "android,fstab"; vendor { compatible = "android,vendor"; - dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor"; + dev = "/dev/block/platform/soc/7c4000.sdhci/by-name/vendor"; type = "ext4"; mnt_flags = "ro,barrier=1,discard"; fsmgr_flags = "wait,slotselect,avb"; @@ -532,61 +510,61 @@ pil_camera_mem: camera_region@8e000000 { compatible = "removed-dma-pool"; no-map; - reg = <0 0x8e400000 0 0x500000>; + reg = <0 0x8e000000 0 0x500000>; }; pil_modem_mem: modem_region@86000000 { compatible = "removed-dma-pool"; no-map; - reg = <0 0x86000000 0 0x8400000>; + reg = <0 0x86000000 0 0x8000000>; }; pil_video_mem: pil_video_region@8ea00000 { compatible = "removed-dma-pool"; no-map; - reg = <0 0x8ee00000 0 0x500000>; + reg = <0 0x8ea00000 0 0x500000>; }; pil_cdsp_mem: cdsp_regions@8ef00000 { compatible = "removed-dma-pool"; no-map; - reg = <0 0x8f300000 0 0x1e00000>; + reg = <0 0x8ef00000 0 0x1e00000>; }; pil_adsp_mem: pil_adsp_region@90d00000 { compatible = "removed-dma-pool"; no-map; - reg = <0 0x91100000 0 0x2800000>; + reg = <0 0x90d00000 0 0x2800000>; }; wlan_fw_mem: wlan_fw_region@93500000 { compatible = "removed-dma-pool"; no-map; - reg = <0 0x93900000 0 0x200000>; + reg = <0 0x93500000 0 0x200000>; }; npu_mem: npu_region@8e500000 { compatible = "removed-dma-pool"; no-map; - reg = <0 0x8e900000 0 0x500000>; + reg = <0 0x8e500000 0 0x500000>; }; pil_ipa_fw_mem: ipa_fw_region@93700000 { compatible = "removed-dma-pool"; no-map; - reg = <0 0x93b00000 0 0x10000>; + reg = <0 0x93700000 0 0x10000>; }; pil_ipa_gsi_mem: ipa_gsi_region@93710000 { compatible = "removed-dma-pool"; no-map; - reg = <0 0x93b10000 0 0x5000>; + reg = <0 0x93710000 0 0x5000>; }; pil_gpu_mem: gpu_region@93715000 { compatible = "removed-dma-pool"; no-map; - reg = <0 0x93b15000 0 0x2000>; + reg = <0 0x93715000 0 0x2000>; }; qseecom_mem: qseecom_region@9e000000 { @@ -595,18 +573,10 @@ reg = <0 0x9e000000 0 0x1400000>; }; - qseecom_ta_mem: qseecom_ta_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0 0x00000000 0 0xffffffff>; - reusable; - alignment = <0 0x400000>; - size = <0 0x1000000>; - }; - cdsp_sec_mem: cdsp_sec_regions@0x9f400000 { compatible = "removed-dma-pool"; no-map; - reg = <0 0x9f400000 0 0x1e00000>; + reg = <0 0x9f400000 0 0xc00000>; }; secure_display_memory: secure_display_region { @@ -897,167 +867,17 @@ reg-names = "pshold-base", "tcsr-boot-misc-detect"; }; - qcom,mpm2-sleep-counter@0xc221000 { - compatible = "qcom,mpm2-sleep-counter"; - reg = <0xc221000 0x1000>; - clock-frequency = <32768>; - }; - - qcom_seecom: qseecom@82200000 { - compatible = "qcom,qseecom"; - reg = <0x82200000 0x2200000>; - reg-names = "secapp-region"; - memory-region = <&qseecom_mem>; - qcom,hlos-num-ce-hw-instances = <1>; - qcom,hlos-ce-hw-instance = <0>; - qcom,qsee-ce-hw-instance = <0>; - qcom,disk-encrypt-pipe-pair = <2>; - qcom,support-fde; - qcom,no-clock-support; - qcom,fde-key-size; - qcom,appsbl-qseecom-support; - qcom,commonlib64-loaded-by-uefi; - qcom,qsee-reentrancy-support = <2>; - }; - - qcom_smcinvoke: smcinvoke@82200000 { - compatible = "qcom,smcinvoke"; - reg = <0x82200000 0x2200000>; - reg-names = "secapp-region"; - }; - aop-msg-client { compatible = "qcom,debugfs-qmp-client"; mboxes = <&qmp_aop 0>; mbox-names = "aop"; }; - qcom_tzlog: tz-log@146aa720 { - compatible = "qcom,tz-log"; - reg = <0x146aa720 0x3000>; - qcom,hyplog-enabled; - hyplog-address-offset = <0x410>; - hyplog-size-offset = <0x414>; - }; - - qcom_rng: qrng@793000 { - compatible = "qcom,msm-rng"; - reg = <0x793000 0x1000>; - qcom,msm-rng-iface-clk; - qcom,no-qrng-config; - qcom,msm-bus,name = "msm-rng-noc"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <1 618 0 0>, /* No vote */ - <1 618 0 300000>; /* 75 MHz */ - clocks = <&clock_gcc GCC_PRNG_AHB_CLK>; - clock-names = "iface_clk"; - }; - - qcom_crypto: qcrypto@1de0000 { - compatible = "qcom,qcrypto"; - reg = <0x1de0000 0x20000>, - <0x1dc4000 0x24000>; - reg-names = "crypto-base","crypto-bam-base"; - interrupts = ; - qcom,bam-pipe-pair = <2>; - qcom,ce-hw-instance = <0>; - qcom,ce-device = <0>; - qcom,bam-ee = <0>; - qcom,ce-hw-shared; - qcom,clk-mgmt-sus-res; - qcom,msm-bus,name = "qcrypto-noc"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <125 512 0 0>, - <125 512 393600 393600>; - qcom,use-sw-aes-cbc-ecb-ctr-algo; - qcom,use-sw-aes-xts-algo; - qcom,use-sw-aes-ccm-algo; - qcom,use-sw-ahash-algo; - qcom,use-sw-aead-algo; - qcom,use-sw-hmac-algo; - qcom,smmu-s1-enable; - qcom,no-clock-support; - iommus = <&apps_smmu 0x0424 0x0011>, - <&apps_smmu 0x0434 0x0011>; - }; - - qcom_cedev: qcedev@1de0000 { - compatible = "qcom,qcedev"; - reg = <0x1de0000 0x20000>, - <0x1dc4000 0x24000>; - reg-names = "crypto-base","crypto-bam-base"; - interrupts = ; - qcom,bam-pipe-pair = <3>; - qcom,ce-hw-instance = <0>; - qcom,ce-device = <0>; - qcom,ce-hw-shared; - qcom,bam-ee = <0>; - qcom,msm-bus,name = "qcedev-noc"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <125 512 0 0>, - <125 512 393600 393600>; - qcom,smmu-s1-enable; - qcom,no-clock-support; - iommus = <&apps_smmu 0x0426 0x0011>, - <&apps_smmu 0x0436 0x0011>; - }; - qcom,msm-rtb { compatible = "qcom,msm-rtb"; qcom,rtb-size = <0x100000>; }; - ufs_ice: ufsice@1d90000 { - compatible = "qcom,ice"; - reg = <0x1d90000 0x8000>; - qcom,enable-ice-clk; - clock-names = "ufs_core_clk", "bus_clk", - "iface_clk", "ice_core_clk"; - clocks = <&clock_gcc GCC_UFS_PHY_AXI_CLK>, - <&clock_gcc GCC_UFS_MEM_CLKREF_CLK>, - <&clock_gcc GCC_UFS_PHY_AHB_CLK>, - <&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>; - qcom,op-freq-hz = <0>, <0>, <0>, <300000000>; - vdd-hba-supply = <&ufs_phy_gdsc>; - qcom,msm-bus,name = "ufs_ice_noc"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <1 757 0 0>, /* No vote */ - <1 757 1000 0>; /* Max. bandwidth */ - qcom,bus-vector-names = "MIN", - "MAX"; - qcom,instance-type = "ufs"; - }; - - sdcc1_ice: sdcc1ice@7c8000{ - compatible = "qcom,ice"; - reg = <0x7c8000 0x8000>; - qcom,enable-ice-clk; - clock-names = "ice_core_clk_src", "ice_core_clk", - "bus_clk", "iface_clk"; - clocks = <&clock_gcc GCC_SDCC1_ICE_CORE_CLK_SRC>, - <&clock_gcc GCC_SDCC1_ICE_CORE_CLK>, - <&clock_gcc GCC_SDCC1_AHB_CLK>, - <&clock_gcc GCC_SDCC1_APPS_CLK>; - qcom,op-freq-hz = <300000000>, <0>, <0>, <0>; - qcom,msm-bus,name = "sdcc_ice_noc"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <1 608 0 0>, /* No vote */ - <1 608 1000 0>; /* Max. bandwidth */ - qcom,bus-vector-names = "MIN", - "MAX"; - qcom,instance-type = "sdcc"; - }; - wdog: qcom,wdt@17c10000{ compatible = "qcom,msm-watchdog"; reg = <0x17c10000 0x1000>; @@ -1072,20 +892,6 @@ 0x10100 0x10100 0x25900 0x25900>; }; - eud: qcom,msm-eud@88e0000 { - compatible = "qcom,msm-eud"; - interrupt-names = "eud_irq"; - interrupts = ; - reg = <0x88e0000 0x2000>, - <0x88e2000 0x1000>; - reg-names = "eud_base", "eud_mode_mgr2"; - qcom,secure-eud-en; - qcom,eud-clock-vote-req; - clocks = <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; - clock-names = "eud_ahb2phy_clk"; - status = "ok"; - }; - qcom,chd_sliver { compatible = "qcom,core-hang-detect"; label = "silver"; @@ -1131,16 +937,6 @@ compatible = "qcom,pil-tz-generic"; reg = <0x4080000 0x100>; - clocks = <&clock_rpmh RPMH_CXO_CLK>; - clock-names = "xo"; - qcom,proxy-clock-names = "xo"; - - vdd_cx-supply = <&VDD_CX_LEVEL>; - qcom,vdd_cx-uV-uA = ; - vdd_mss-supply = <&VDD_MSS_LEVEL>; - qcom,vdd_mss-uV-uA = ; - qcom,proxy-reg-names = "vdd_cx", "vdd_mss"; - qcom,firmware-name = "modem"; memory-region = <&pil_modem_mem>; qcom,proxy-timeout-ms = <10000>; @@ -1178,16 +974,6 @@ compatible = "qcom,pil-tz-generic"; reg = <0x8300000 0x100000>; - vdd_cx-supply = <&VDD_CX_LEVEL>; - qcom,vdd_cx-uV-uA = ; - vdd_mx-supply = <&VDD_MX_LEVEL>; - qcom,vdd_mx-uV-uA = ; - qcom,proxy-reg-names = "vdd_cx", "vdd_mx"; - - clocks = <&clock_rpmh RPMH_CXO_CLK>; - clock-names = "xo"; - qcom,proxy-clock-names = "xo"; - qcom,pas-id = <18>; qcom,proxy-timeout-ms = <10000>; qcom,smem-id = <601>; @@ -1328,16 +1114,6 @@ compatible = "qcom,pil-tz-generic"; reg = <0x62400000 0x00100>; - vdd_lpi_cx-supply = <&L8A_LEVEL>; - qcom,vdd_cx-uV-uA = ; - vdd_lpi_mx-supply = <&L7A_LEVEL>; - qcom,vdd_mx-uV-uA = ; - qcom,proxy-reg-names = "vdd_lpi_cx", "vdd_lpi_mx"; - - clocks = <&clock_rpmh RPMH_CXO_CLK>; - clock-names = "xo"; - qcom,proxy-clock-names = "xo"; - qcom,pas-id = <1>; qcom,proxy-timeout-ms = <10000>; qcom,smem-id = <423>; @@ -1383,12 +1159,6 @@ cap-based-alloc-and-pwr-collapse; }; - qcom,llcc-perfmon { - compatible = "qcom,llcc-perfmon"; - clocks = <&clock_aop QDSS_CLK>; - clock-names = "qdss_clk"; - }; - qcom,llcc-erp { compatible = "qcom,llcc-erp"; }; @@ -1554,11 +1324,6 @@ qcom,dump-node = <&L2_TLB_700>; qcom,dump-id = <0x127>; }; - - qcom,llcc1_d_cache { - qcom,dump-node = <&LLCC_1>; - qcom,dump-id = <0x140>; - }; }; mem_dump { @@ -1616,129 +1381,60 @@ }; }; - clocks { - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - clock-frequency = <32000>; - clock-output-names = "chip_sleep_clk"; - #clock-cells = <1>; - }; - }; - clock_rpmh: qcom,rpmh { - compatible = "qcom,rpmh-clk-atoll"; - mboxes = <&apps_rsc 0>; - mbox-names = "apps"; + compatible = "qcom,dummycc"; + clock-output-names = "rpm_clocks"; #clock-cells = <1>; }; clock_aop: qcom,aopclk { - compatible = "qcom,aop-qmp-clk"; + compatible = "qcom,dummycc"; + clock-output-names = "aop_clocks"; #clock-cells = <1>; - mboxes = <&qmp_aop 0>; - mbox-names = "qdss_clk"; }; - clock_gcc: qcom,gcc@100000 { - compatible = "qcom,atoll-gcc", "syscon"; - reg = <0x100000 0x1f0000>; - reg-names = "cc_base"; - vdd_cx-supply = <&VDD_CX_LEVEL>; - vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>; + clock_gcc: qcom,gcc { + compatible = "qcom,dummycc"; + clock-output-names = "gcc_clocks"; #clock-cells = <1>; #reset-cells = <1>; }; - clock_camcc: qcom,camcc@ad00000 { - compatible = "qcom,atoll-camcc", "syscon"; - reg = <0xad00000 0x10000>; - reg-names = "cc_base"; - vdd_cx-supply = <&VDD_CX_LEVEL>; - vdd_mx-supply = <&VDD_MX_LEVEL>; + clock_camcc: qcom,camcc { + compatible = "qcom,dummycc"; + clock-output-names = "camcc_clocks"; #clock-cells = <1>; #reset-cells = <1>; }; - clock_dispcc: qcom,dispcc@af00000 { - compatible = "qcom,atoll-dispcc", "syscon"; - reg = <0xaf00000 0x20000>; - reg-names = "cc_base"; - vdd_cx-supply = <&VDD_CX_LEVEL>; + clock_dispcc: qcom,dispcc { + compatible = "qcom,dummycc"; + clock-output-names = "dispcc_clocks"; #clock-cells = <1>; #reset-cells = <1>; }; - clock_gpucc: qcom,gpucc@5090000 { - compatible = "qcom,atoll-gpucc", "syscon"; - reg = <0x5090000 0x9000>; - reg-names = "cc_base"; - vdd_cx-supply = <&VDD_CX_LEVEL>; - vdd_mx-supply = <&VDD_MX_LEVEL>; - vdd_gfx-supply = <&VDD_GFX_LEVEL>; - qcom,gpu_cc_gx_gfx3d_clk_src-opp-handle = <&msm_gpu>; - qcom,gpu_cc_gmu_clk_src-opp-handle = <&gmu>; + clock_gpucc: qcom,gpucc { + compatible = "qcom,dummycc"; + clock-output-names = "gpucc_clocks"; #clock-cells = <1>; #reset-cells = <1>; }; - clock_npucc: qcom,npucc@9980000 { - compatible = "qcom,atoll-npucc", "syscon"; - reg = <0x9980000 0x10000>, - <0x9800000 0x10000>, - <0x9810000 0x10000>; - reg-names = "cc", "qdsp6ss", "qdsp6ss_pll"; - npu_gdsc-supply = <&npu_core_gdsc>; - vdd_cx-supply = <&VDD_CX_LEVEL>; + clock_npucc: qcom,npucc { + compatible = "qcom,dummycc"; + clock-output-names = "npucc_clocks"; #clock-cells = <1>; #reset-cells = <1>; }; - clock_videocc: qcom,videocc@ab00000 { - compatible = "qcom,atoll-videocc", "syscon"; - reg = <0xab00000 0x10000>; - reg-names = "cc_base"; - vdd_cx-supply = <&VDD_CX_LEVEL>; + clock_videocc: qcom,videocc { + compatible = "qcom,dummycc"; + clock-output-names = "videocc_clocks"; #clock-cells = <1>; #reset-cells = <1>; }; - clock_cpucc: qcom,cpucc@18321000 { - compatible = "qcom,clk-cpu-osm-atoll"; - reg = <0x18321000 0x1400>, - <0x18323000 0x1400>, - <0x18325800 0x1400>; - reg-names = "osm_l3_base", "osm_pwrcl_base", - "osm_perfcl_base"; - #clock-cells = <1>; - status = "disabled"; - }; - - cpucc_debug: syscon@182a0018 { - compatible = "syscon"; - reg = <0x182a0018 0x4>; - }; - - mccc_debug: syscon@90b0000 { - compatible = "syscon"; - reg = <0x090b0000 0x100>; - }; - - clock_debug: qcom,cc-debug { - compatible = "qcom,atoll-debugcc"; - qcom,cc-count = <8>; - qcom,gcc = <&clock_gcc>; - qcom,gpucc = <&clock_gpucc>; - qcom,camcc = <&clock_camcc>; - qcom,videocc = <&clock_videocc>; - qcom,dispcc = <&clock_dispcc>; - qcom,npucc = <&clock_npucc>; - qcom,cpucc = <&cpucc_debug>; - qcom,mccc = <&mccc_debug>; - clocks = <&clock_rpmh RPMH_CXO_CLK>; - clock-names = "xo_clk_src"; - #clock-cells = <1>; - }; - tcsr_mutex_block: syscon@01F40000 { compatible = "syscon"; reg = <0x01F40000 0x20000>; @@ -2264,6 +1960,7 @@ ipa_smmu_ap: ipa_smmu_ap { compatible = "qcom,ipa-smmu-ap-cb"; + qcom,smmu-s1-bypass; iommus = <&apps_smmu 0x0440 0x0>; qcom,iova-mapping = <0x20000000 0x40000000>; /* modem tables in IMEM */ @@ -2272,6 +1969,7 @@ ipa_smmu_wlan: ipa_smmu_wlan { compatible = "qcom,ipa-smmu-wlan-cb"; + qcom,smmu-s1-bypass; iommus = <&apps_smmu 0x0441 0x0>; /* ipa-uc ram */ qcom,additional-mapping = <0x1e60000 0x1e60000 0x80000>; @@ -2279,6 +1977,7 @@ ipa_smmu_uc: ipa_smmu_uc { compatible = "qcom,ipa-smmu-uc-cb"; + qcom,smmu-s1-bypass; iommus = <&apps_smmu 0x0442 0x0>; qcom,iova-mapping = <0x40400000 0x1fc00000>; }; @@ -2312,7 +2011,6 @@ interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; - sdhc-msm-crypto = <&sdcc1_ice>; qcom,bus-width = <8>; qcom,large-address-bus; @@ -2323,45 +2021,6 @@ qcom,devfreq,freq-table = <50000000 200000000>; - qcom,msm-bus,name = "sdhc1"; - qcom,msm-bus,num-cases = <9>; - qcom,msm-bus,num-paths = <2>; - qcom,msm-bus,vectors-KBps = - /* No vote */ - <150 512 0 0>, <1 806 0 0>, - /* 400 KB/s*/ - <150 512 1000 2000>, - <1 806 2000 4000>, - /* 20 MB/s */ - <150 512 25000 50000>, - <1 806 20000 40000>, - /* 25 MB/s */ - <150 512 50000 100000>, - <1 806 30000 60000>, - /* 50 MB/s */ - <150 512 80000 150000>, - <1 806 40000 80000>, - /* 100 MB/s */ - <150 512 100000 200000>, - <1 806 50000 100000>, - /* 200 MB/s */ - <150 512 150000 250000>, - <1 806 80000 120000>, - /* 400 MB/s */ - <150 512 261438 2718822>, - <1 806 300000 1359411>, - /* Max. bandwidth */ - <150 512 1338562 4096000>, - <1 806 1338562 4096000>; - qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 - 100750000 200000000 400000000 4294967295>; - - /* PM QoS */ - qcom,pm-qos-irq-type = "affine_irq"; - qcom,pm-qos-irq-latency = <67 67>; - qcom,pm-qos-cpu-groups = <0x3f 0xc0>; - qcom,pm-qos-cmdq-latency-us = <67 67>, <67 67>; - qcom,pm-qos-legacy-latency-us = <67 67>, <67 67>; clocks = <&clock_gcc GCC_SDCC1_AHB_CLK>, <&clock_gcc GCC_SDCC1_APPS_CLK>, <&clock_gcc GCC_SDCC1_ICE_CORE_CLK>; @@ -2397,42 +2056,6 @@ qcom,devfreq,freq-table = <50000000 202000000>; - qcom,msm-bus,name = "sdhc2"; - qcom,msm-bus,num-cases = <8>; - qcom,msm-bus,num-paths = <2>; - qcom,msm-bus,vectors-KBps = - /* No vote */ - <81 512 0 0>, <1 608 0 0>, - /* 400 KB/s*/ - <81 512 1000 2000>, - <1 608 1600 20000>, - /* 20 MB/s */ - <81 512 20000 40000>, - <1 608 20000 40000>, - /* 25 MB/s */ - <81 512 40000 80000>, - <1 608 30000 60000>, - /* 50 MB/s */ - <81 512 60000 120000>, - <1 608 40000 80000>, - /* 100 MB/s */ - <81 512 80000 160000>, - <1 608 50000 100000>, - /* 200 MB/s */ - <81 512 100000 200000>, - <1 608 60000 120000>, - /* Max. bandwidth */ - <81 512 1338562 4096000>, - <1 608 1338562 4096000>; - qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 - 100750000 200000000 4294967295>; - - /* PM QoS */ - qcom,pm-qos-irq-type = "affine_irq"; - qcom,pm-qos-irq-latency = <67 67>; - qcom,pm-qos-cpu-groups = <0x3f 0xc0>; - qcom,pm-qos-legacy-latency-us = <67 67>, <67 67>; - clocks = <&clock_gcc GCC_SDCC2_AHB_CLK>, <&clock_gcc GCC_SDCC2_APPS_CLK>; clock-names = "iface_clk", "core_clk"; @@ -2466,7 +2089,6 @@ interrupts = <0 265 0>; phys = <&ufsphy_mem>; phy-names = "ufsphy"; - ufs-qcom-crypto = <&ufs_ice>; lanes-per-direction = <1>; dev-ref-clk-freq = <0>; /* 19.2 MHz */ @@ -2596,39 +2218,6 @@ #thermal-sensor-cells = <1>; }; - icnss: qcom,icnss@18800000 { - compatible = "qcom,icnss"; - reg = <0x18800000 0x800000>, - <0xa0000000 0x10000000>, - <0xb0000000 0x10000>; - reg-names = "membase", "smmu_iova_base", "smmu_iova_ipa"; - iommus = <&apps_smmu 0xC0 0x1>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - ; - qcom,wlan-msa-fixed-region = <&wlan_fw_mem>; - vdd-cx-mx-supply = <&L9A>; - vdd-1.8-xo-supply = <&L1C>; - vdd-1.3-rfa-supply = <&L2C>; - vdd-3.3-ch0-supply = <&L10C>; - qcom,vdd-cx-mx-config = <640000 640000>; - qcom,smp2p_map_wlan_1_in { - interrupts-extended = <&smp2p_wlan_1_in 0 0>, - <&smp2p_wlan_1_in 1 0>; - interrupt-names = "qcom,smp2p-force-fatal-error", - "qcom,smp2p-early-crash-ind"; - }; - }; - qcom,venus@aae0000 { compatible = "qcom,pil-tz-generic"; reg = <0xaae0000 0x4000>; @@ -2653,412 +2242,6 @@ qcom,firmware-name = "venus"; memory-region = <&pil_video_mem>; }; - - qfprom: qfprom@780000 { - compatible = "qcom,qfprom"; - reg = <0x00786018 0x4>; - #address-cells = <1>; - #size-cells = <1>; - read-only; - ranges; - }; - - slim_aud: slim@62ec0000 { - cell-index = <1>; - compatible = "qcom,slim-ngd"; - reg = <0x62ec0000 0x2c000>, - <0x62e84000 0x2a000>; - reg-names = "slimbus_physical", "slimbus_bam_physical"; - interrupts = , - ; - interrupt-names = "slimbus_irq", "slimbus_bam_irq"; - qcom,apps-ch-pipes = <0x700000>; - qcom,ea-pc = <0x340>; - qcom,iommu-s1-bypass; - status = "ok"; - - iommu_slim_aud_ctrl_cb: qcom,iommu_slim_ctrl_cb { - compatible = "qcom,iommu-slim-ctrl-cb"; - iommus = <&apps_smmu 0x1026 0x0>, - <&apps_smmu 0x102f 0x0>, - <&apps_smmu 0x1030 0x1>; - }; - - btfmslim_codec: wcn3990 { - compatible = "qcom,btfmslim_slave"; - elemental-addr = [00 01 20 02 17 02]; - qcom,btfm-slim-ifd = "btfmslim_slave_ifd"; - qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02]; - }; - }; - - bluetooth: bt_wcn3990 { - compatible = "qca,wcn3990"; - qca,bt-vdd-io-supply = <&pm6150_l10>; /* IO */ - qca,bt-vdd-core-supply = <&pm6150l_l2>; /* RFA */ - qca,bt-vdd-pa-supply = <&pm6150l_l10>; /* CH0 */ - qca,bt-vdd-xtal-supply = <&pm6150l_l1>;/* X0 */ - - qca,bt-vdd-io-voltage-level = <1721000 1829000>; - qca,bt-vdd-core-voltage-level = <1200000 1350000>; - qca,bt-vdd-pa-voltage-level = <3300000 3400000>; - qca,bt-vdd-xtal-voltage-level = <1620000 1980000>; - - qca,bt-vdd-io-current-level = <1>; /* LPM/PFM */ - qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */ - qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */ - qca,bt-vdd-xtal-current-level = <1>; /* LPM/PFM */ - }; - - keepalive_opp_table: keepalive-opp-table { - compatible = "operating-points-v2"; - opp-1 { - opp-hz = /bits/ 64 < 1 >; - }; - }; - - snoc_cnoc_keepalive: qcom,snoc_cnoc_keepalive { - compatible = "qcom,devbw"; - governor = "powersave"; - qcom,src-dst-ports = <1 627>; - qcom,active-only; - status = "ok"; - operating-points-v2 = <&keepalive_opp_table>; - }; - - bus_proxy_client: qcom,bus_proxy_client { - compatible = "qcom,bus-proxy-client"; - qcom,msm-bus,name = "bus-proxy-client"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - , - ; - qcom,msm-bus,active-only; - status = "ok"; - }; - - llcc_bw_opp_table: llcc-bw-opp-table { - compatible = "operating-points-v2"; - BW_OPP_ENTRY( 150, 16); /* 2288 MB/s */ - BW_OPP_ENTRY( 300, 16); /* 4577 MB/s */ - BW_OPP_ENTRY( 466, 16); /* 7110 MB/s */ - BW_OPP_ENTRY( 600, 16); /* 9155 MB/s */ - BW_OPP_ENTRY( 806, 16); /* 12298 MB/s */ - BW_OPP_ENTRY( 933, 16); /* 14236 MB/s */ - }; - - cpu_cpu_llcc_bw: qcom,cpu-cpu-llcc-bw { - compatible = "qcom,devbw"; - governor = "performance"; - qcom,src-dst-ports = - ; - qcom,active-only; - operating-points-v2 = <&llcc_bw_opp_table>; - }; - - cpu_cpu_llcc_bwmon: qcom,cpu-cpu-llcc-bwmon@90b6300 { - compatible = "qcom,bimc-bwmon4"; - reg = <0x90b6300 0x300>, <0x90b6200 0x200>; - reg-names = "base", "global_base"; - interrupts = ; - qcom,mport = <0>; - qcom,hw-timer-hz = <19200000>; - qcom,target-dev = <&cpu_cpu_llcc_bw>; - qcom,count-unit = <0x10000>; - }; - - ddr_bw_opp_table: ddr-bw-opp-table { - compatible = "operating-points-v2"; - BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */ - BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */ - BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */ - BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */ - BW_OPP_ENTRY(1017, 4); /* 3879 MB/s */ - BW_OPP_ENTRY(1555, 4); /* 5931 MB/s */ - BW_OPP_ENTRY(1804, 4); /* 6881 MB/s */ - BW_OPP_ENTRY(2133, 4); /* 8137 MB/s */ - }; - - cpu_llcc_ddr_bw: qcom,cpu-llcc-ddr-bw { - compatible = "qcom,devbw"; - governor = "performance"; - qcom,src-dst-ports = - ; - qcom,active-only; - operating-points-v2 = <&ddr_bw_opp_table>; - }; - - cpu_llcc_ddr_bwmon: qcom,cpu-llcc-ddr-bwmon@90cd000 { - compatible = "qcom,bimc-bwmon5"; - reg = <0x90cd000 0x1000>; - reg-names = "base"; - interrupts = ; - qcom,hw-timer-hz = <19200000>; - qcom,target-dev = <&cpu_llcc_ddr_bw>; - qcom,count-unit = <0x10000>; - }; - - cpu0_cpu_l3_lat: qcom,cpu0-cpu-l3-lat { - compatible = "devfreq-simple-dev"; - clock-names = "devfreq_clk"; - clocks = <&clock_cpucc L3_CLUSTER0_VOTE_CLK>; - governor = "performance"; - }; - - cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; - qcom,target-dev = <&cpu0_cpu_l3_lat>; - qcom,cachemiss-ev = <0x17>; - qcom,core-dev-table = - < 768000 300000000 >, - < 1017600 556800000 >, - < 1248000 806400000 >, - < 1516800 940800000 >, - < 1804800 1401000000 >; - }; - - cpu6_cpu_l3_lat: qcom,cpu6-cpu-l3-lat { - compatible = "devfreq-simple-dev"; - clock-names = "devfreq_clk"; - clocks = <&clock_cpucc L3_CLUSTER1_VOTE_CLK>; - governor = "performance"; - }; - - cpu6_cpu_l3_latmon: qcom,cpu6-cpu-l3-latmon { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU6 &CPU7>; - qcom,target-dev = <&cpu6_cpu_l3_lat>; - qcom,cachemiss-ev = <0x17>; - qcom,core-dev-table = - < 1113600 556800000 >, - < 1267200 806400000 >, - < 1555200 940800000 >, - < 1708800 1209600000 >, - < 1900800 1401000000 >, - < 2400000 1459000000 >; - }; - - cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat { - compatible = "qcom,devbw"; - governor = "performance"; - qcom,src-dst-ports = - ; - qcom,active-only; - operating-points-v2 = <&llcc_bw_opp_table>; - }; - - cpu0_cpu_llcc_latmon: qcom,cpu0-cpu-llcc-latmon { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; - qcom,target-dev = <&cpu0_cpu_llcc_lat>; - qcom,cachemiss-ev = <0x2A>; - qcom,core-dev-table = - < 1248000 MHZ_TO_MBPS(300, 16) >, - < 1516800 MHZ_TO_MBPS(466, 16) >, - < 1804800 MHZ_TO_MBPS(600, 16) >; - }; - - cpu6_cpu_llcc_lat: qcom,cpu6-cpu-llcc-lat { - compatible = "qcom,devbw"; - governor = "performance"; - qcom,src-dst-ports = - ; - qcom,active-only; - operating-points-v2 = <&llcc_bw_opp_table>; - }; - - cpu6_cpu_llcc_latmon: qcom,cpu6-cpu-llcc-latmon { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU6 &CPU7>; - qcom,target-dev = <&cpu6_cpu_llcc_lat>; - qcom,cachemiss-ev = <0x2A>; - qcom,core-dev-table = - < 825600 MHZ_TO_MBPS(300, 16) >, - < 1113600 MHZ_TO_MBPS(466, 16) >, - < 1267200 MHZ_TO_MBPS(600, 16) >, - < 1708800 MHZ_TO_MBPS(806, 16) >, - < 2400000 MHZ_TO_MBPS(933, 16) >; - }; - - cpu0_llcc_ddr_lat: qcom,cpu0-llcc-ddr-lat { - compatible = "qcom,devbw"; - governor = "performance"; - qcom,src-dst-ports = - ; - qcom,active-only; - operating-points-v2 = <&ddr_bw_opp_table>; - }; - - cpu0_llcc_ddr_latmon: qcom,cpu0-llcc-ddr-latmon { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; - qcom,target-dev = <&cpu0_llcc_ddr_lat>; - qcom,cachemiss-ev = <0x1000>; - qcom,core-dev-table = - < 768000 MHZ_TO_MBPS( 300, 4) >, - < 1017600 MHZ_TO_MBPS( 451, 4) >, - < 1248000 MHZ_TO_MBPS( 547, 4) >, - < 1516800 MHZ_TO_MBPS( 768, 4) >, - < 1804800 MHZ_TO_MBPS(1017, 4) >; - }; - - cpu6_llcc_ddr_lat: qcom,cpu6-llcc-ddr-lat { - compatible = "qcom,devbw"; - governor = "performance"; - qcom,src-dst-ports = - ; - qcom,active-only; - operating-points-v2 = <&ddr_bw_opp_table>; - }; - - cpu6_llcc_ddr_latmon: qcom,cpu6-llcc-ddr-latmon { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU6 &CPU7>; - qcom,target-dev = <&cpu6_llcc_ddr_lat>; - qcom,cachemiss-ev = <0x1000>; - qcom,core-dev-table = - < 1113600 MHZ_TO_MBPS( 547, 4) >, - < 1267200 MHZ_TO_MBPS(1017, 4) >, - < 1708800 MHZ_TO_MBPS(1555, 4) >, - < 2400000 MHZ_TO_MBPS(1804, 4) >; - }; - - cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor { - compatible = "qcom,devbw"; - governor = "performance"; - qcom,src-dst-ports = - ; - qcom,active-only; - operating-points-v2 = <&ddr_bw_opp_table>; - }; - - cpu0_computemon: qcom,cpu0-computemon { - compatible = "qcom,arm-cpu-mon"; - qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; - qcom,target-dev = <&cpu0_cpu_ddr_latfloor>; - qcom,core-dev-table = - < 768000 MHZ_TO_MBPS( 300, 4) >, - < 1248000 MHZ_TO_MBPS( 451, 4) >, - < 1516800 MHZ_TO_MBPS( 547, 4) >, - < 1804800 MHZ_TO_MBPS( 768, 4) >; - }; - - cpu6_cpu_ddr_latfloor: qcom,cpu6-cpu-ddr-latfloor { - compatible = "qcom,devbw"; - governor = "performance"; - qcom,src-dst-ports = - ; - qcom,active-only; - operating-points-v2 = <&ddr_bw_opp_table>; - }; - - cpu6_computemon: qcom,cpu6-computemon { - compatible = "qcom,arm-cpu-mon"; - qcom,cpulist = <&CPU6 &CPU7>; - qcom,target-dev = <&cpu6_cpu_ddr_latfloor>; - qcom,core-dev-table = - < 1267200 MHZ_TO_MBPS( 547, 4) >, - < 1555200 MHZ_TO_MBPS( 768, 4) >, - < 1708800 MHZ_TO_MBPS(1017, 4) >, - < 1900800 MHZ_TO_MBPS(1555, 4) >, - < 2208000 MHZ_TO_MBPS(1804, 4) >, - < 2400000 MHZ_TO_MBPS(2133, 4) >; - }; - - suspendable_ddr_bw_opp_table: suspendable-ddr-bw-opp-table { - compatible = "operating-points-v2"; - BW_OPP_ENTRY( 0, 4); /* 0 MB/s */ - BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */ - BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */ - BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */ - BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */ - BW_OPP_ENTRY(1017, 4); /* 3879 MB/s */ - BW_OPP_ENTRY(1555, 4); /* 5931 MB/s */ - BW_OPP_ENTRY(1804, 4); /* 6881 MB/s */ - BW_OPP_ENTRY(2133, 4); /* 8137 MB/s */ - }; - - npu_npu_ddr_bw: qcom,npu-npu-ddr-bw { - compatible = "qcom,devbw"; - governor = "performance"; - qcom,src-dst-ports = ; - operating-points-v2 = <&suspendable_ddr_bw_opp_table>; - status = "disabled"; - }; - - npu_npu_ddr_bwmon: qcom,npu-npu-ddr-bwmon@00060300 { - compatible = "qcom,bimc-bwmon4"; - reg = <0x00060300 0x300>, <0x00060200 0x200>; - reg-names = "base", "global_base"; - clocks = <&clock_gcc GCC_NPU_BWMON_DMA_CFG_AHB_CLK>, - <&clock_gcc GCC_NPU_BWMON_AXI_CLK>; - clock-names = "gcc_npu_bwmon_dma_cfg_ahb_clk", - "gcc_npu_bwmon_axi_clk"; - qcom,bwmon_clks = "gcc_npu_bwmon_dma_cfg_ahb_clk", - "gcc_npu_bwmon_axi_clk"; - interrupts = ; - qcom,mport = <0>; - qcom,hw-timer-hz = <19200000>; - qcom,target-dev = <&npu_npu_ddr_bw>; - qcom,count-unit = <0x10000>; - status = "disabled"; - }; - - npudsp_npu_ddr_bw: qcom,npudsp-npu-ddr-bw { - compatible = "qcom,devbw"; - governor = "performance"; - qcom,src-dst-ports = ; - operating-points-v2 = <&suspendable_ddr_bw_opp_table>; - status = "disabled"; - }; - - npudsp_npu_ddr_bwmon: qcom,npudsp-npu-ddr-bwmon@70200 { - compatible = "qcom,bimc-bwmon4"; - reg = <0x00070200 0x300>, <0x00070000 0x200>; - reg-names = "base", "global_base"; - clocks = <&clock_gcc GCC_NPU_BWMON_DSP_CFG_AHB_CLK>, - <&clock_gcc GCC_NPU_BWMON_AXI_CLK>; - clock-names = "gcc_npu_bwmon_dsp_cfg_ahb_clk", - "gcc_npu_bwmon_axi_clk"; - qcom,bwmon_clks = "gcc_npu_bwmon_dsp_cfg_ahb_clk", - "gcc_npu_bwmon_axi_clk"; - interrupts = ; - qcom,mport = <0>; - qcom,hw-timer-hz = <19200000>; - qcom,target-dev = <&npudsp_npu_ddr_bw>; - qcom,count-unit = <0x10000>; - status = "disabled"; - }; - - /delete-node/gpu-bw-tbl; - /delete-node/qcom,gpubw; - - gpu_bw_tbl: gpu-bw-tbl { - compatible = "operating-points-v2"; - opp-0 { opp-hz = /bits/ 64 < 0 >; }; /* OFF */ - opp-100 { opp-hz = /bits/ 64 < 381 >; }; /* 1.DDR:100 MHz */ - opp-200 { opp-hz = /bits/ 64 < 762 >; }; /* 2.DDR:200 MHz */ - opp-300 { opp-hz = /bits/ 64 < 1144 >; }; /* 3.DDR:300 MHz */ - opp-451 { opp-hz = /bits/ 64 < 1720 >; }; /* 4.DDR:451 MHz */ - opp-547 { opp-hz = /bits/ 64 < 2086 >; }; /* 5.DDR:547 MHz */ - opp-681 { opp-hz = /bits/ 64 < 2597 >; }; /* 6.DDR:681 MHz */ - opp-825 { opp-hz = /bits/ 64 < 3147 >; }; /* 7.DDR:825 MHz */ - opp-1017 { opp-hz = /bits/ 64 < 3879 >; }; /* 8.DDR:1017 MHz */ - opp-1353 { opp-hz = /bits/ 64 < 5161 >; }; /* 9.DDR:1353 MHz */ - opp-1555 { opp-hz = /bits/ 64 < 5931 >; }; /* 10.DDR:1555 MHz */ - opp-1804 { opp-hz = /bits/ 64 < 6881 >; }; /* 11.DDR:1804 MHz */ - opp-2133 { opp-hz = /bits/ 64 < 8137 >; }; /* 12.DDR:2133 MHz */ - }; - - gpubw: qcom,gpubw { - compatible = "qcom,devbw"; - governor = "bw_vbif"; - qcom,src-dst-ports = <26 512>; - operating-points-v2 = <&gpu_bw_tbl>; - }; }; #include "atoll-gdsc.dtsi" @@ -3066,123 +2249,9 @@ #include "msm-arm-smmu-atoll.dtsi" #include "atoll-qupv3.dtsi" #include "sdmmagpie-gpu.dtsi" -#include "atoll-bus.dtsi" &msm_gpu { - /delete-property/ qcom,gpu-speed-bin; - /delete-property/ qcom,msm-bus,num-cases; - /delete-property/ qcom,msm-bus,vectors-KBps; - /delete-property/ qcom,initial-pwrlevel; - /delete-property/ qcom,ca-target-pwrlevel; - - qcom,msm-bus,num-cases = <13>; - qcom,msm-bus,vectors-KBps = - <26 512 0 0>, - <26 512 0 400000>, /* 1 bus=100 */ - <26 512 0 800000>, /* 2 bus=200 */ - <26 512 0 1200000>, /* 3 bus=300 */ - <26 512 0 1804000>, /* 4 bus=451 */ - <26 512 0 2188000>, /* 5 bus=547 */ - <26 512 0 2724000>, /* 6 bus=681 */ - <26 512 0 3300000>, /* 7 bus=825 */ - <26 512 0 4068000>, /* 8 bus=1017 */ - <26 512 0 5412000>, /* 9 bus=1353 */ - <26 512 0 6220000>, /* 10 bus=1555 */ - <26 512 0 7216000>, /* 11 bus=1804 */ - <26 512 0 8532000>; /* 12 bus=2133 */ - - qcom,initial-pwrlevel = <7>; - qcom,ca-target-pwrlevel = <5>; - - /delete-node/ qcom,gpu-pwrlevel-bins; - - qcom,gpu-pwrlevels { - #address-cells = <1>; - #size-cells = <0>; - - compatible = "qcom,gpu-pwrlevels"; - - /* TURBO_L1 */ - qcom,gpu-pwrlevel@0 { - reg = <0>; - qcom,gpu-freq = <825000000>; - qcom,bus-freq = <11>; - qcom,bus-min = <10>; - qcom,bus-max = <12>; - }; - - /* TURBO */ - qcom,gpu-pwrlevel@1 { - reg = <1>; - qcom,gpu-freq = <800000000>; - qcom,bus-freq = <11>; - qcom,bus-min = <10>; - qcom,bus-max = <11>; - }; - - /* NOM_L1 */ - qcom,gpu-pwrlevel@2 { - reg = <2>; - qcom,gpu-freq = <650000000>; - qcom,bus-freq = <10>; - qcom,bus-min = <8>; - qcom,bus-max = <11>; - }; - - /* NOM */ - qcom,gpu-pwrlevel@3 { - reg = <3>; - qcom,gpu-freq = <565000000>; - qcom,bus-freq = <9>; - qcom,bus-min = <8>; - qcom,bus-max = <10>; - }; - - /* SVS_L1 */ - qcom,gpu-pwrlevel@4 { - reg = <4>; - qcom,gpu-freq = <430000000>; - qcom,bus-freq = <8>; - qcom,bus-min = <7>; - qcom,bus-max = <10>; - }; - - /* SVS */ - qcom,gpu-pwrlevel@5 { - reg = <5>; - qcom,gpu-freq = <355000000>; - qcom,bus-freq = <7>; - qcom,bus-min = <5>; - qcom,bus-max = <8>; - }; - - /* LOW SVS */ - qcom,gpu-pwrlevel@6 { - reg = <6>; - qcom,gpu-freq = <267000000>; - qcom,bus-freq = <6>; - qcom,bus-min = <4>; - qcom,bus-max = <7>; - }; - - /* LOW SVS */ - qcom,gpu-pwrlevel@7 { - reg = <7>; - qcom,gpu-freq = <180000000>; - qcom,bus-freq = <4>; - qcom,bus-min = <3>; - qcom,bus-max = <4>; - }; - - /* XO */ - qcom,gpu-pwrlevel@8 { - reg = <8>; - qcom,gpu-freq = <0>; - qcom,bus-freq = <0>; - qcom,bus-min = <0>; - qcom,bus-max = <0>; - }; - }; + /delete-property/qcom,gpu-speed-bin; }; &ufs_phy_gdsc { @@ -3249,19 +2318,23 @@ status = "ok"; }; -&qupv3_se3_4uart { - status = "ok"; -}; - #include "pm6150.dtsi" #include "pm6150l.dtsi" #include "atoll-pinctrl.dtsi" #include "atoll-pm.dtsi" #include "atoll-coresight.dtsi" -#include "atoll-regulator.dtsi" +#include "atoll-stub-regulator.dtsi" #include "atoll-usb.dtsi" #include "atoll-vidc.dtsi" +&usb0 { + extcon = <&pm6150_pdphy>, <&pm6150_charger>; +}; + +&usb_qmp_dp_phy { + extcon = <&pm6150_pdphy>; +}; + &pm6150_vadc { pinctrl-names = "default"; pinctrl-0 = <&nvm_therm_default &sdm_skin_therm_default>; @@ -3410,92 +2483,4 @@ }; }; -#include "atoll-audio.dtsi" #include "atoll-thermal.dtsi" -#include "atoll-camera.dtsi" -#include "atoll-sde-pll.dtsi" -#include "atoll-sde.dtsi" - -&qupv3_se9_i2c { - status = "ok"; - #include "pm8008.dtsi" -}; - -&tlmm { - pm8008_active: pm8008_active { - mux { - pins = "gpio42"; - function = "gpio"; - }; - - config { - pins = "gpio42"; - bias-pull-up; - output-high; - drive-strength = <2>; - }; - }; -}; - -&pm8008_gpios { - gpio1_active { - pm8008_gpio1_active: pm8008_gpio1_active { - pins = "gpio1"; - function = "normal"; - power-source = <1>; - bias-disable; - input-enable; - }; - }; -}; - -&pm8008_chip { - pinctrl-names = "default"; - pinctrl-0 = <&pm8008_active>; -}; - -&pm8008_regulators { - vdd_l1_l2-supply = <&S8C>; - vdd_l3_l4-supply = <&BOB>; - vdd_l5-supply = <&S5A>; - vdd_l6-supply = <&BOB>; - vdd_l7-supply = <&BOB>; -}; - -&pm8008_9 { - /* GPIO1 pinctrl config */ - pinctrl-names = "default"; - pinctrl-0 = <&pm8008_gpio1_active>; -}; - -&L1P { - regulator-max-microvolt = <1104000>; - qcom,min-dropout-voltage = <225000>; -}; - -&L2P { - regulator-max-microvolt = <1200000>; - qcom,min-dropout-voltage = <75000>; -}; - -&L3P { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - qcom,min-dropout-voltage = <200000>; -}; - -&L4P { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - qcom,min-dropout-voltage = <200000>; -}; - -&L5P { - regulator-max-microvolt = <1800000>; - qcom,min-dropout-voltage = <200000>; -}; - -&L6P { - regulator-max-microvolt = <2800000>; - qcom,min-dropout-voltage = <300000>; -}; diff --git a/arch/arm64/boot/dts/qcom/dsi-panel-samsung_oneplus_dsc.dtsi b/arch/arm64/boot/dts/qcom/dsi-panel-samsung_oneplus_dsc.dtsi new file mode 100755 index 0000000000000000000000000000000000000000..d52ead622a0efa0406056d746dc3ae2af6a38cd4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/dsi-panel-samsung_oneplus_dsc.dtsi @@ -0,0 +1,2665 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_samsung_oneplus_dsc_cmd: qcom,mdss_dsi_samsung_oneplus_dsc_cmd { + qcom,mdss-dsi-panel-name = "samsung dsc cmd mode oneplus dsi panel"; + qcom,mdss-dsi-panel-manufacture = "SAMSUNG"; + qcom,mdss-dsi-panel-version = "DSC"; + qcom,mdss-dsi-backlight-version = "SAMSUNG"; + qcom,mdss-dsi-backlight-manufacture = "SAMSUNG"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-reset-sequence = <1 8>, <0 1>, <1 5>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-default-val = <200>; + qcom,mdss-brightness-max-level = <1023>; + qcom,mdss-pan-physical-width-dimension = <71>; + qcom,mdss-pan-physical-height-dimension = <154>; + qcom,mdss-dsi-init-delay-us = <1000>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-high-brightness-panel; + qcom,mdss-dsi-acl-cmd-index = <0>; + qcom,mdss-dsi-acl-mode-index = <1>; + qcom,mdss-bl-high2bit; + qcom,mdss-loading-effect; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,dynamic-mode-switch-enabled; + qcom,dynamic-mode-switch-type = "dynamic-resolution-switch-immediate"; + qcom,mdss-dsi-panel-clockrate = <1100000000>; + /* HDR Setting */ + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15635 16450 34000 16000 13250 34500 7500 3000>; + qcom,mdss-dsi-panel-peak-brightness = <5400000>; + qcom,mdss-dsi-panel-average-brightness = <2000000>; + qcom,mdss-dsi-panel-blackness-level = <2000>; + qcom,mdss-dsi-panel-seria-num-year-index = <12>; + qcom,mdss-dsi-panel-seria-num-mon-index = <12>; + qcom,mdss-dsi-panel-seria-num-day-index = <13>; + qcom,mdss-dsi-panel-seria-num-hour-index = <14>; + qcom,mdss-dsi-panel-seria-num-min-index = <15>; + qcom,mdss-dsi-panel-seria-num-sec-index = <16>; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0A 00]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9F>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-panel-id1-command = [06 01 00 00 00 00 02 0A 00]; + qcom,mdss-dsi-panel-id2-command = [06 01 00 00 00 00 02 0E 00]; + qcom,mdss-dsi-panel-id3-command = [06 01 00 00 00 00 02 0F 00]; + qcom,mdss-dsi-panel-id4-command = [06 01 00 00 00 00 02 C4 00]; + qcom,mdss-dsi-panel-id5-command = [06 01 00 00 00 00 02 E7 00]; + qcom,mdss-dsi-panel-id6-command = [06 01 00 00 00 00 02 EA 00]; + qcom,mdss-dsi-panel-id7-command = [06 01 00 00 00 00 02 FB 00]; + qcom,mdss-dsi-panel-read-register-open-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + ]; + qcom,mdss-dsi-panel-read-register-close-command = [ + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-read-esd-registed-longread-command = [ + 37 01 00 00 05 00 02 22 00 + ]; + qcom,mdss-dsi-panel-id1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id4-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id5-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id6-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id7-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-open-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-close-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-esd-registed-longread-command-state = "dsi_lp_mode"; + + /* + * ************************************************************************************************************************ + * DMS (Dynamic Mode Switch) + * ************************************************************************************************************************ + */ + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,display-topology = <1 1 1>,<2 2 1>; + qcom,default-topology-index = <1>; + qcom,mdss-mdp-transfer-time-us = <8000>; //for 60fps + qcom,mdss-dsi-timing-default; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-clockrate = <1100000000>; + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 25 09 0A 06 02 04 00 1E 1A]; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3120>; + qcom,mdss-dsi-h-front-porch = <16>; + qcom,mdss-dsi-h-back-porch = <8>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <1156>; + qcom,mdss-dsi-v-front-porch = <400>; + qcom,mdss-dsi-v-pulse-width = <28>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0A 00]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9F>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-panel-id1-command = [06 01 00 00 00 00 02 0A 00]; + qcom,mdss-dsi-panel-id2-command = [06 01 00 00 00 00 02 0E 00]; + qcom,mdss-dsi-panel-id3-command = [06 01 00 00 00 00 02 0F 00]; + qcom,mdss-dsi-panel-id4-command = [06 01 00 00 00 00 02 C4 00]; + qcom,mdss-dsi-panel-id5-command = [06 01 00 00 00 00 02 E7 00]; + qcom,mdss-dsi-panel-id6-command = [06 01 00 00 00 00 02 EA 00]; + qcom,mdss-dsi-panel-id7-command = [06 01 00 00 00 00 02 FB 00]; + qcom,mdss-dsi-panel-read-register-open-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + ]; + qcom,mdss-dsi-panel-read-register-close-command = [ + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-read-esd-registed-longread-command = [ + 37 01 00 00 05 00 02 22 00 + ]; + qcom,mdss-dsi-panel-id1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id4-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id5-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id6-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id7-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-open-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-close-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-esd-registed-longread-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-timing-switch-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + //29 01 00 00 00 00 03 9F A5 A5 + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 00 /* Scaler disable */ + 29 01 00 00 00 00 05 2A 00 00 05 9F /* CASET */ + 29 01 00 00 00 00 05 2B 00 00 0C 2F /* PASET */ + 39 01 00 00 00 00 5A 0A /* PPS Setting (1440 x 3120) (initial value) */ + 10 00 00 89 30 80 0C 30 + 05 A0 00 41 02 D0 02 D0 + 02 00 02 C2 00 20 06 58 + 00 0A 00 0F 01 E0 01 2D + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A B6 + 2A F4 2A F4 4B 34 63 74 + 00 + 15 01 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + //29 01 00 00 00 00 03 9F 5A 5A + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-t-clk-pre = <0x1E>; + qcom,mdss-dsi-t-clk-post = <0x1A>; + qcom,mdss-dsi-on-command = [ + /* DSC Setting */ + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 00 /* Scaler disable */ + 39 01 00 00 00 00 5A 0A /* PPS Setting (1440 x 3120) (initial value) */ + 10 00 00 89 30 80 0C 30 + 05 A0 00 41 02 D0 02 D0 + 02 00 02 C2 00 20 06 58 + 00 0A 00 0F 01 E0 01 2D + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A B6 + 2A F4 2A F4 4B 34 63 74 + 00 + /* Sleep Out(11h) */ + 05 01 00 00 0A 00 01 11 + /* Common Setting */ + 15 00 00 00 00 00 02 35 00 /* TE On(Vsync) */ + /* CASET/PASET Setting */ + 39 01 00 00 00 00 05 2A 00 00 05 9F /* CASET */ + 39 01 00 00 00 00 05 2B 00 00 0C 2F /* PASET */ + /* TSP SYNC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 0A B9 01 C0 3C 0B 00 00 00 11 03 /* SYNC ENABLE */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* FD(Fast Discharge) Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 45 /* FD setting (Normal mode) */ + 15 01 00 00 00 00 02 B5 48 + 39 01 00 00 00 00 03 F0 A5 A5 + /* FFC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 1E + 39 01 00 00 00 00 06 C5 09 10 B4 24 FB /* FFC Setting; 0x09 : Enable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* OSC Spread Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 37 + 39 01 00 00 00 00 06 C5 04 FF 00 01 64 /* FFC Setting; 0x04 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 86 /* Global para */ + 15 01 00 00 00 00 02 EB 01 /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC A5 A5 + /* Brightness Control */ + 39 01 00 00 00 00 03 F0 5A 5A /* Dimming Setting */ + 15 01 00 00 00 00 02 B0 05 + 15 01 00 00 00 00 02 B1 01 /* Dimming Speed Setting : 0x01 : 1Frame*/ + 15 01 00 00 00 00 02 B0 02 + 15 01 00 00 00 00 02 B5 D3 /* 0xD3 : ELVSS DIM ON */ + 15 01 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* Display On */ + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-113mhz-osc-dsi-on-command = [ + /* DSC Setting */ + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 00 /* Scaler disable */ + 39 01 00 00 00 00 5A 0A /* PPS Setting (1440 x 3120) (initial value) */ + 10 00 00 89 30 80 0C 30 + 05 A0 00 41 02 D0 02 D0 + 02 00 02 C2 00 20 06 58 + 00 0A 00 0F 01 E0 01 2D + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A B6 + 2A F4 2A F4 4B 34 63 74 + 00 + /* Sleep Out(11h) */ + 05 01 00 00 0A 00 01 11 + /* Common Setting */ + 15 00 00 00 00 00 02 35 00 /* TE On(Vsync) */ + /* CASET/PASET Setting */ + 39 01 00 00 00 00 05 2A 00 00 05 9F /* CASET */ + 39 01 00 00 00 00 05 2B 00 00 0C 2F /* PASET */ + /* TSP SYNC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 0A B9 01 C0 3C 0B 00 00 00 11 03 /* SYNC ENABLE */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* FD(Fast Discharge) Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 45 /* FD setting (Normal mode) */ + 15 01 00 00 00 00 02 B5 48 + 39 01 00 00 00 00 03 F0 A5 A5 + /* FFC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 1E + 39 01 00 00 00 00 06 C5 08 10 B4 24 FB /* FFC Setting; 0x08 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* OSC Spread Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 37 + 39 01 00 00 00 00 06 C5 04 FF 00 01 64 /* FFC Setting; 0x04 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 86 /* Global para */ + 15 01 00 00 00 00 02 EB 01 /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC A5 A5 + /* Brightness Control */ + 39 01 00 00 00 00 03 F0 5A 5A /* Dimming Setting */ + 15 01 00 00 00 00 02 B0 05 + 15 01 00 00 00 00 02 B1 01 /* Dimming Speed Setting : 0x01 : 1Frame*/ + 15 01 00 00 00 00 02 B0 02 + 15 01 00 00 00 00 02 B5 D3 /* 0xD3 : ELVSS DIM ON */ + 15 01 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* Display On */ + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-dsi-timing-switch-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-113mhz-osc-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-off-command=[ + 05 01 00 00 0A 00 02 28 00 + 05 01 00 00 78 00 02 10 00 + ]; + qcom,mdss-dsi-panel-hbm-brightness-on-command = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 53 /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 00 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM Mode ON */ + 15 01 00 00 11 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + ]; + qcom,mdss-dsi-panel-hbm-brightness-off-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 53 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 01 00 00 11 00 03 F0 A5 A5 /* Level2 key Access Disable */ + ]; + qcom,mdss-dsi-panel-hbm-on-command-1 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-2 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-3 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-4 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-5 = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 93 /* 0x93 : ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 01 00 00 14 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM MODE ON */ + 15 00 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + 29 01 00 00 0D 00 03 51 0F FF /* 600nit */ + /* HBM 670 ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 00 /* HBM_670 ON */ + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-hbm-off-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 13 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* 90Hz Setting */ + 15 01 00 00 11 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + /* HBM 670 OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 02 /* HBM_670 OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF /* 430nit */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 00 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + 15 01 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + ]; + qcom,mdss-dsi-panel-serial-num-pre-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + 37 01 00 00 05 00 02 10 00 + ]; + qcom,mdss-dsi-panel-serial-num-command = [ + 06 01 00 00 00 00 01 A1 00 + ]; + qcom,mdss-dsi-panel-code-info-command = [ + 06 01 00 00 00 00 01 DA 00 + ]; + qcom,mdss-dsi-panel-stage-info-command = [ + 06 01 00 00 00 00 01 DB 00 + ]; + qcom,mdss-dsi-panel-production-info-command = [ + 06 01 00 00 00 00 01 DC 00 + ]; + qcom,mdss-dsi-panel-serial-num-post-command = [ + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-aod-on-command-1 = [ + ]; + qcom,mdss-dsi-panel-aod-on-command-2 = [ + ]; + qcom,mdss-dsi-panel-aod-off-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-samsung-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-new-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-hbm-on-command = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 93 /* 0x93 : ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 01 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM MODE ON */ + 15 00 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + 29 01 00 00 00 00 03 51 0F FF /* 600nit */ + /* HBM 670 ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 00 /* HBM_670 ON */ + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-hbm-off-aod-on-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 13 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM 670 OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 02 /* HBM_670 OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF /* 430nit */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 01 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + ]; + qcom,mdss-dsi-panel-gamma-flash-pre-read-1-command = [ + /*Level2 key Enable*/ + 29 01 00 00 00 00 03 F0 5A 5A + //07 01 00 00 00 00 01 01 + //29 00 00 00 00 00 05 2A 00 00 05 9F + //29 00 00 00 00 00 05 2B 00 00 0C 2F + /*OTP key Enable*/ + 29 01 00 00 00 00 03 F1 F1 A2 + 29 01 00 00 00 00 0D C1 00 00 00 06 00 00 00 00 00 00 00 05 + 15 01 00 00 00 00 02 C0 03 + 29 01 00 00 00 00 0C C1 00 00 00 01 40 02 00 00 00 00 10 + 15 01 00 00 00 00 02 C0 03 + 29 01 00 00 00 00 0E C1 00 00 00 6B 00 00 00 0A 00 00 00 05 01 + 15 01 00 00 00 00 02 B0 07 + ]; + qcom,mdss-dsi-panel-gamma-flash-pre-read-2-command = [ + 15 01 00 00 00 00 02 C0 03 + 15 01 00 00 00 00 02 B0 08 + ]; + qcom,mdss-dsi-panel-gamma-flash-read-fb-command = [ + /*13th Parameter : 1byte Read value*/ + 06 01 00 00 00 00 02 FB 00 + ]; + qcom,mdss-dsi-panel-level2-key-enable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c8-smrps-command = [ + 37 01 00 00 05 00 02 87 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c8-command = [ + 06 01 00 00 00 00 02 C8 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c9-smrps-command = [ + 37 01 00 00 00 00 02 B4 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c9-command = [ + 06 01 00 00 00 00 02 C9 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-b3-smrps-command = [ + 37 01 00 00 00 00 02 2F 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-b3-command = [ + 06 01 00 00 00 00 02 B3 00 + ]; + qcom,mdss-dsi-panel-level2-key-disable-command = [ + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-night-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 39 01 00 0A 00 00 16 67 BB 0E 04 3E D8 12 09 05 EA 41 E2 D0 E5 09 F6 D0 D0 11 F8 FE DC + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-p3-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 E0 03 00 11 E2 01 0D 08 E5 1A FA FC E5 09 F6 EA F3 01 FE FF F7 + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 FF 00 00 00 FF 00 00 00 FF 00 FF FF FF 00 FF FF FF 00 FF FF FF + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-dci-p3-off-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 03 67 00 01 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-loading-effect-enable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 01 + 29 01 00 00 00 00 02 95 81 + 29 01 00 00 00 00 02 B0 14 + 29 01 00 00 00 00 03 95 FF 6D + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-loading-effect-disable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 01 + 29 01 00 00 00 00 02 95 A1 + 29 01 00 00 00 00 02 B0 14 + 29 01 00 00 00 00 03 95 28 28 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-customer-srgb-enable-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 10 00 02 B0 02 + 29 01 00 00 00 00 16 67 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-customer-p3-enable-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 10 00 02 B0 02 + 29 01 00 00 00 00 16 67 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-command = [ + 15 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 0A 00 02 B0 02 + 29 01 00 00 0A 00 16 67 FF 05 00 0B EB 00 07 00 FF 14 F8 EA F0 03 F5 DE F5 00 FF FF FF + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-seed-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 D3 03 00 11 E4 01 0B 06 F0 1A FA FC E5 09 F6 EA F3 01 FC FF EA + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-seed-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-customer-p3-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-customer-srgb-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-loading-effect-enable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-loading-effect-disable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-p3-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-night-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-dci-p3-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-new-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-samsung-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-hbm-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-off-aod-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-aod-on-command-1-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-on-command-2-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-pre-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-code-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-state-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-production-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-post-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-brightness-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-brightness-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-on-command-1-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-2-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-3-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-4-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-5-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-gamma-flash-pre-read-1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-flash-pre-read-2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-flash-read-fb-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-level2-key-enable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c8-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c8-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c9-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c9-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-b3-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-b3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-level2-key-disable-command-state = "dsi_lp_mode"; + qcom,panel-roi-alignment=<720 65 720 65 720 65>; + qcom,compression-mode = "dsc"; + qcom,lm-split = <720 720>; + qcom,mdss-dsc-encoders = <2>; + qcom,mdss-dsc-slice-height = <65>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@1{ + qcom,display-topology = <1 1 1>,<2 2 1>; + qcom,default-topology-index = <1>; + qcom,mdss-mdp-transfer-time-us = <8000>; //for 90fps + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-clockrate = <1100000000>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <16>; + qcom,mdss-dsi-h-back-porch = <8>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <4>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0A 00]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9F>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-panel-id1-command = [06 01 00 00 00 00 02 0A 00]; + qcom,mdss-dsi-panel-id2-command = [06 01 00 00 00 00 02 0E 00]; + qcom,mdss-dsi-panel-id3-command = [06 01 00 00 00 00 02 0F 00]; + qcom,mdss-dsi-panel-id4-command = [06 01 00 00 00 00 02 C4 00]; + qcom,mdss-dsi-panel-id5-command = [06 01 00 00 00 00 02 E7 00]; + qcom,mdss-dsi-panel-id6-command = [06 01 00 00 00 00 02 EA 00]; + qcom,mdss-dsi-panel-id7-command = [06 01 00 00 00 00 02 FB 00]; + qcom,mdss-dsi-panel-read-register-open-command = [ + 39 01 00 00 00 00 03 F0 5A 5A]; + qcom,mdss-dsi-panel-read-register-close-command = [ + 39 01 00 00 00 00 03 F0 A5 A5]; + qcom,mdss-dsi-panel-read-esd-registed-longread-command = [ + 37 01 00 00 05 00 02 22 00 + ]; + qcom,mdss-dsi-panel-id1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id4-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id5-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id6-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id7-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-open-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-close-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-esd-registed-longread-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-timing-switch-command = [ + 29 01 00 00 00 00 03 F0 5A 5A /* Level2 key Access Enable */ + //29 01 00 00 00 00 03 9F A5 A5 /* Level1 key Access Enable */ + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 01 /* Scaler enable(x1.78) */ + 29 01 00 00 00 00 05 2A 00 00 04 37 /* CASET */ + 29 01 00 00 00 00 05 2B 00 00 09 23 /* PASET */ + 39 01 00 00 00 00 59 0A /* PPS Setting (1080 x 2340) */ + 11 00 00 89 30 80 09 24 + 04 38 00 1E 02 1C 02 1C + 02 00 02 0E 00 20 02 E3 + 00 07 00 0C 03 50 03 64 + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A F6 + 2B 34 2B 74 3B 74 6B F4 + 15 01 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + //29 01 00 00 00 00 03 9F 5A 5A + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 25 09 0A 06 02 04 00 1E 1A]; + qcom,mdss-dsi-t-clk-pre = <0x1E>; + qcom,mdss-dsi-t-clk-post = <0x1A>; + qcom,mdss-dsi-on-command = [ + /* DSC Setting */ + 29 01 00 00 00 00 03 F0 5A 5A + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 01 /* Scaler enable(x1.78) */ + 39 01 00 00 00 00 59 0A /* PPS Setting (1080 x 2340) */ + 11 00 00 89 30 80 09 24 + 04 38 00 1E 02 1C 02 1C + 02 00 02 0E 00 20 02 E3 + 00 07 00 0C 03 50 03 64 + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A F6 + 2B 34 2B 74 3B 74 6B F4 + 29 01 00 00 00 00 03 F0 A5 A5 + /* Sleep Out(11h) */ + 05 01 00 00 0A 00 01 11 + /* Common Setting */ + 15 00 00 00 00 00 02 35 00 /* TE On(Vsync) */ + /* CASET/PASET Setting */ + 29 01 00 00 00 00 05 2A 00 00 04 37 /* CASET */ + 29 01 00 00 00 00 05 2B 00 00 09 23 /* PASET */ + /* TSP SYNC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 0A B9 01 C0 3C 0B 00 00 00 11 03 /* SYNC ENABLE */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* FD(Fast Discharge) Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 45 /* FD setting (Normal mode) */ + 15 01 00 00 00 00 02 B5 48 + 39 01 00 00 00 00 03 F0 A5 A5 + /* FFC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 1E + 39 01 00 00 00 00 06 C5 09 10 B4 24 FB /* FFC Setting; 0x09 : Enable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* OSC Spread Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 37 + 39 01 00 00 00 00 06 C5 04 FF 00 01 64 /* FFC Setting; 0x04 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 86 /* Global para */ + 15 01 00 00 00 00 02 EB 01 /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC A5 A5 + /* Brightness Control */ + 39 01 00 00 00 00 03 F0 5A 5A /* Dimming Setting */ + 15 01 00 00 00 00 02 B0 05 + 15 01 00 00 00 00 02 B1 01 /* Dimming Speed Setting : 0x01 : 1Frame */ + 15 01 00 00 00 00 02 B0 02 + 15 01 00 00 00 00 02 B5 D3 /* 0xD3 : ELVSS DIM ON */ + 15 01 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* Display On */ + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-113mhz-osc-dsi-on-command = [ + /* DSC Setting */ + 29 01 00 00 00 00 03 F0 5A 5A + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 01 /* Scaler enable(x1.78) */ + 39 01 00 00 00 00 59 0A /* PPS Setting (1080 x 2340) */ + 11 00 00 89 30 80 09 24 + 04 38 00 1E 02 1C 02 1C + 02 00 02 0E 00 20 02 E3 + 00 07 00 0C 03 50 03 64 + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A F6 + 2B 34 2B 74 3B 74 6B F4 + 29 01 00 00 00 00 03 F0 A5 A5 + /* Sleep Out(11h) */ + 05 01 00 00 0A 00 01 11 + /* Common Setting */ + 15 00 00 00 00 00 02 35 00 /* TE On(Vsync) */ + /* CASET/PASET Setting */ + 29 01 00 00 00 00 05 2A 00 00 04 37 /* CASET */ + 29 01 00 00 00 00 05 2B 00 00 09 23 /* PASET */ + /* TSP SYNC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 0A B9 01 C0 3C 0B 00 00 00 11 03 /* SYNC ENABLE */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* FD(Fast Discharge) Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 45 /* FD setting (Normal mode) */ + 15 01 00 00 00 00 02 B5 48 + 39 01 00 00 00 00 03 F0 A5 A5 + /* FFC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 1E + 39 01 00 00 00 00 06 C5 08 10 B4 24 FB /* FFC Setting; 0x08 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* OSC Spread Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 37 + 39 01 00 00 00 00 06 C5 04 FF 00 01 64 /* FFC Setting; 0x04 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 86 /* Global para */ + 15 01 00 00 00 00 02 EB 01 /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC A5 A5 + /* Brightness Control */ + 39 01 00 00 00 00 03 F0 5A 5A /* Dimming Setting */ + 15 01 00 00 00 00 02 B0 05 + 15 01 00 00 00 00 02 B1 01 /* Dimming Speed Setting : 0x01 : 1Frame */ + 15 01 00 00 00 00 02 B0 02 + 15 01 00 00 00 00 02 B5 D3 /* 0xD3 : ELVSS DIM ON */ + 15 01 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* Display On */ + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-113mhz-osc-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-off-command=[ + 05 01 00 00 0A 00 02 28 00 + 05 01 00 00 78 00 02 10 00 + ]; + qcom,mdss-dsi-panel-hbm-brightness-on-command = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 53 /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 00 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM Mode ON */ + 15 01 00 00 0C 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + ]; + qcom,mdss-dsi-panel-hbm-brightness-off-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 53 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 01 00 00 0C 00 03 F0 A5 A5 /* Level2 key Access Disable */ + ]; + qcom,mdss-dsi-panel-hbm-on-command-1 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-2 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-3 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-4 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-5 = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 93 /* 0x93 : ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 01 00 00 10 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM MODE ON */ + 15 00 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + 29 01 00 00 0C 00 03 51 0F FF /* 600nit */ + /* HBM 670 ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 00 /* HBM_670 ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* 90Hz Setting */ + 15 01 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + ]; + qcom,mdss-dsi-panel-hbm-off-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 13 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM 670 OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 02 /* HBM_670 OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF /* 430nit */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 01 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + ]; + qcom,mdss-dsi-panel-serial-num-pre-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + 37 01 00 00 05 00 02 10 00 + ]; + qcom,mdss-dsi-panel-serial-num-command = [ + 06 01 00 00 00 00 01 A1 00 + ]; + qcom,mdss-dsi-panel-code-info-command = [ + 06 01 00 00 00 00 01 DA 00 + ]; + qcom,mdss-dsi-panel-stage-info-command = [ + 06 01 00 00 00 00 01 DB 00 + ]; + qcom,mdss-dsi-panel-production-info-command = [ + 06 01 00 00 00 00 01 DC 00 + ]; + qcom,mdss-dsi-panel-serial-num-post-command = [ + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-aod-on-command-1 = [ + ]; + qcom,mdss-dsi-panel-aod-on-command-2 = [ + ]; + qcom,mdss-dsi-panel-aod-off-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-samsung-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-new-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-hbm-on-command = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 93 /* 0x93 : ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 01 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM MODE ON */ + 15 00 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + 29 01 00 00 00 00 03 51 0F FF /* 600nit */ + /* HBM 670 ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 00 /* HBM_670 ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* 90Hz Setting */ + 15 01 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + ]; + qcom,mdss-dsi-panel-hbm-off-aod-on-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 13 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM 670 OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 02 /* HBM_670 OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF /* 430nit */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 01 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + ]; + qcom,mdss-dsi-panel-gamma-flash-pre-read-1-command = [ + /*Level2 key Enable*/ + 29 01 00 00 00 00 03 F0 5A 5A + //07 01 00 00 00 00 01 01 + //29 00 00 00 00 00 05 2A 00 00 05 9F + //29 00 00 00 00 00 05 2B 00 00 0C 2F + /*OTP key Enable*/ + 29 01 00 00 00 00 03 F1 F1 A2 + 29 01 00 00 00 00 0D C1 00 00 00 06 00 00 00 00 00 00 00 05 + 15 01 00 00 00 00 02 C0 03 + 29 01 00 00 00 00 0C C1 00 00 00 01 40 02 00 00 00 00 10 + 15 01 00 00 00 00 02 C0 03 + 29 01 00 00 00 00 0E C1 00 00 00 6B 00 00 00 0A 00 00 00 05 01 + 15 01 00 00 00 00 02 B0 07 + ]; + qcom,mdss-dsi-panel-gamma-flash-pre-read-2-command = [ + 15 01 00 00 00 00 02 C0 03 + 15 01 00 00 00 00 02 B0 08 + ]; + qcom,mdss-dsi-panel-gamma-flash-read-fb-command = [ + /*13th Parameter : 1byte Read value*/ + 06 01 00 00 00 00 02 FB 00 + ]; + qcom,mdss-dsi-panel-level2-key-enable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c8-smrps-command = [ + 37 01 00 00 00 00 02 87 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c8-command = [ + 06 01 00 00 00 00 02 C8 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c9-smrps-command = [ + 37 01 00 00 00 00 02 B4 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c9-command = [ + 06 01 00 00 00 00 02 C9 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-b3-smrps-command = [ + 37 01 00 00 00 00 02 2F 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-b3-command = [ + 06 01 00 00 00 00 02 B3 00 + ]; + qcom,mdss-dsi-panel-level2-key-disable-command = [ + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-night-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 39 01 00 0A 00 00 16 67 BB 0E 04 3E D8 12 09 05 EA 41 E2 D0 E5 09 F6 D0 D0 11 F8 FE DC + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-p3-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 E0 03 00 11 E2 01 0D 08 E5 1A FA FC E5 09 F6 EA F3 01 FE FF F7 + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 FF 00 00 00 FF 00 00 00 FF 00 FF FF FF 00 FF FF FF 00 FF FF FF + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-dci-p3-off-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 03 67 00 01 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-loading-effect-enable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 01 + 29 01 00 00 00 00 02 95 81 + 29 01 00 00 00 00 02 B0 14 + 29 01 00 00 00 00 03 95 FF 6D + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-loading-effect-disable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 01 + 29 01 00 00 00 00 02 95 A1 + 29 01 00 00 00 00 02 B0 14 + 29 01 00 00 00 00 03 95 28 28 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-customer-srgb-enable-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 10 00 02 B0 02 + 29 01 00 00 00 00 16 67 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-customer-p3-enable-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 10 00 02 B0 02 + 29 01 00 00 00 00 16 67 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-command = [ + 15 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 0A 00 02 B0 02 + 29 01 00 00 0A 00 16 67 FF 05 00 0B EB 00 07 00 FF 14 F8 EA F0 03 F5 DE F5 00 FF FF FF + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-seed-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 D3 03 00 11 E4 01 0B 06 F0 1A FA FC E5 09 F6 EA F3 01 FC FF EA + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-seed-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-customer-p3-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-customer-srgb-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-loading-effect-enable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-loading-effect-disable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-p3-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-night-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-dci-p3-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-new-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-samsung-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-hbm-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-off-aod-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-aod-on-command-1-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-on-command-2-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-pre-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-code-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-state-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-production-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-post-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-brightness-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-brightness-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-on-command-1-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-2-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-3-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-4-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-5-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-gamma-flash-pre-read-1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-flash-pre-read-2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-flash-read-fb-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-level2-key-enable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c8-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c8-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c9-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c9-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-b3-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-b3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-level2-key-disable-command-state = "dsi_lp_mode"; + qcom,panel-roi-alignment=<540 60 540 60 540 60>; + qcom,compression-mode = "dsc"; + qcom,lm-split = <540 540>; + qcom,mdss-dsc-encoders = <2>; + qcom,mdss-dsc-slice-height = <60>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@2{ + qcom,display-topology = <1 1 1>,<2 2 1>; + qcom,default-topology-index = <1>; + qcom,mdss-mdp-transfer-time-us = <8000>; //for 60fps + qcom,mdss-dsi-timing-default; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-clockrate = <1100000000>; + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 25 09 0A 06 02 04 00 1E 1A]; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <16>; + qcom,mdss-dsi-h-back-porch = <8>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <1156>; + qcom,mdss-dsi-v-front-porch = <400>; + qcom,mdss-dsi-v-pulse-width = <28>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0A 00]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9F>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-panel-id1-command = [06 01 00 00 00 00 02 0A 00]; + qcom,mdss-dsi-panel-id2-command = [06 01 00 00 00 00 02 0E 00]; + qcom,mdss-dsi-panel-id3-command = [06 01 00 00 00 00 02 0F 00]; + qcom,mdss-dsi-panel-id4-command = [06 01 00 00 00 00 02 C4 00]; + qcom,mdss-dsi-panel-id5-command = [06 01 00 00 00 00 02 E7 00]; + qcom,mdss-dsi-panel-id6-command = [06 01 00 00 00 00 02 EA 00]; + qcom,mdss-dsi-panel-id7-command = [06 01 00 00 00 00 02 FB 00]; + qcom,mdss-dsi-panel-read-register-open-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + ]; + qcom,mdss-dsi-panel-read-register-close-command = [ + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-read-esd-registed-longread-command = [ + 37 01 00 00 05 00 02 22 00 + ]; + qcom,mdss-dsi-panel-id1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id4-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id5-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id6-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id7-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-open-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-close-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-esd-registed-longread-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-timing-switch-command = [ + 29 01 00 00 00 00 03 F0 5A 5A /* Level2 key Access Enable */ + //29 01 00 00 00 00 03 9F A5 A5 /* Level1 key Access Enable */ + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 01 /* Scaler enable(x1.78) */ + 29 01 00 00 00 00 05 2A 00 00 04 37 /* CASET */ + 29 01 00 00 00 00 05 2B 00 00 09 23 /* PASET */ + 39 01 00 00 00 00 59 0A /* PPS Setting (1080 x 2340) */ + 11 00 00 89 30 80 09 24 + 04 38 00 1E 02 1C 02 1C + 02 00 02 0E 00 20 02 E3 + 00 07 00 0C 03 50 03 64 + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A F6 + 2B 34 2B 74 3B 74 6B F4 + 15 01 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + //29 01 00 00 00 00 03 9F 5A 5A + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-t-clk-pre = <0x1E>; + qcom,mdss-dsi-t-clk-post = <0x1A>; + qcom,mdss-dsi-on-command = [ + /* DSC Setting */ + 29 01 00 00 00 00 03 F0 5A 5A + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 01 /* Scaler enable(x1.78) */ + 39 01 00 00 00 00 59 0A /* PPS Setting (1080 x 2340) */ + 11 00 00 89 30 80 09 24 + 04 38 00 1E 02 1C 02 1C + 02 00 02 0E 00 20 02 E3 + 00 07 00 0C 03 50 03 64 + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A F6 + 2B 34 2B 74 3B 74 6B F4 + 29 01 00 00 00 00 03 F0 A5 A5 + /* Sleep Out(11h) */ + 05 01 00 00 0A 00 01 11 + /* Common Setting */ + 15 00 00 00 00 00 02 35 00 /* TE On(Vsync) */ + /* CASET/PASET Setting */ + 29 01 00 00 00 00 05 2A 00 00 04 37 /* CASET */ + 29 01 00 00 00 00 05 2B 00 00 09 23 /* PASET */ + /* TSP SYNC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 0A B9 01 C0 3C 0B 00 00 00 11 03 /* SYNC ENABLE */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* FD(Fast Discharge) Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 45 /* FD setting (Normal mode) */ + 15 01 00 00 00 00 02 B5 48 + 39 01 00 00 00 00 03 F0 A5 A5 + /* FFC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 1E + 39 01 00 00 00 00 06 C5 09 10 B4 24 FB /* FFC Setting; 0x09 : Enable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* OSC Spread Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 37 + 39 01 00 00 00 00 06 C5 04 FF 00 01 64 /* FFC Setting; 0x04 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 86 /* Global para */ + 15 01 00 00 00 00 02 EB 01 /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC A5 A5 + /* Brightness Control */ + 39 01 00 00 00 00 03 F0 5A 5A /* Dimming Setting */ + 15 01 00 00 00 00 02 B0 05 + 15 01 00 00 00 00 02 B1 01 /* Dimming Speed Setting : 0x01 : 1Frame */ + 15 01 00 00 00 00 02 B0 02 + 15 01 00 00 00 00 02 B5 D3 /* 0xD3 : ELVSS DIM ON */ + 15 01 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* Display On */ + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-113mhz-osc-dsi-on-command = [ + /* DSC Setting */ + 29 01 00 00 00 00 03 F0 5A 5A + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 01 /* Scaler enable(x1.78) */ + 39 01 00 00 00 00 59 0A /* PPS Setting (1080 x 2340) */ + 11 00 00 89 30 80 09 24 + 04 38 00 1E 02 1C 02 1C + 02 00 02 0E 00 20 02 E3 + 00 07 00 0C 03 50 03 64 + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A F6 + 2B 34 2B 74 3B 74 6B F4 + 29 01 00 00 00 00 03 F0 A5 A5 + /* Sleep Out(11h) */ + 05 01 00 00 0A 00 01 11 + /* Common Setting */ + 15 00 00 00 00 00 02 35 00 /* TE On(Vsync) */ + /* CASET/PASET Setting */ + 29 01 00 00 00 00 05 2A 00 00 04 37 /* CASET */ + 29 01 00 00 00 00 05 2B 00 00 09 23 /* PASET */ + /* TSP SYNC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 0A B9 01 C0 3C 0B 00 00 00 11 03 /* SYNC ENABLE */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* FD(Fast Discharge) Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 45 /* FD setting (Normal mode) */ + 15 01 00 00 00 00 02 B5 48 + 39 01 00 00 00 00 03 F0 A5 A5 + /* FFC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 1E + 39 01 00 00 00 00 06 C5 08 10 B4 24 FB /* FFC Setting; 0x08 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* OSC Spread Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 37 + 39 01 00 00 00 00 06 C5 04 FF 00 01 64 /* FFC Setting; 0x04 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 86 /* Global para */ + 15 01 00 00 00 00 02 EB 01 /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC A5 A5 + /* Brightness Control */ + 39 01 00 00 00 00 03 F0 5A 5A /* Dimming Setting */ + 15 01 00 00 00 00 02 B0 05 + 15 01 00 00 00 00 02 B1 01 /* Dimming Speed Setting : 0x01 : 1Frame */ + 15 01 00 00 00 00 02 B0 02 + 15 01 00 00 00 00 02 B5 D3 /* 0xD3 : ELVSS DIM ON */ + 15 01 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* Display On */ + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-dsi-timing-switch-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-113mhz-osc-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-off-command=[ + 05 01 00 00 0A 00 02 28 00 + 05 01 00 00 78 00 02 10 00 + ]; + qcom,mdss-dsi-panel-hbm-brightness-on-command = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 53 /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 00 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM Mode ON */ + 15 01 00 00 11 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + ]; + qcom,mdss-dsi-panel-hbm-brightness-off-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 53 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 01 00 00 11 00 03 F0 A5 A5 /* Level2 key Access Disable */ + ]; + qcom,mdss-dsi-panel-hbm-on-command-1 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-2 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-3 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-4 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-5 = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 93 /* 0x93 : ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 01 00 00 14 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM MODE ON */ + 15 00 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + 29 01 00 00 0D 00 03 51 0F FF /* 600nit */ + /* HBM 670 ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 00 /* HBM_670 ON */ + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-hbm-off-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 13 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* 90Hz Setting */ + 15 01 00 00 11 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + /* HBM 670 OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 02 /* HBM_670 OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF /* 430nit */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 00 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + 15 01 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + ]; + qcom,mdss-dsi-panel-serial-num-pre-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + 37 01 00 00 05 00 02 10 00 + ]; + qcom,mdss-dsi-panel-serial-num-command = [ + 06 01 00 00 00 00 01 A1 00 + ]; + qcom,mdss-dsi-panel-code-info-command = [ + 06 01 00 00 00 00 01 DA 00 + ]; + qcom,mdss-dsi-panel-stage-info-command = [ + 06 01 00 00 00 00 01 DB 00 + ]; + qcom,mdss-dsi-panel-production-info-command = [ + 06 01 00 00 00 00 01 DC 00 + ]; + qcom,mdss-dsi-panel-serial-num-post-command = [ + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-aod-on-command-1 = [ + ]; + qcom,mdss-dsi-panel-aod-on-command-2 = [ + ]; + qcom,mdss-dsi-panel-aod-off-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-samsung-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-new-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-hbm-on-command = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 93 /* 0x93 : ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 01 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM MODE ON */ + 15 00 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + 29 01 00 00 00 00 03 51 0F FF /* 600nit */ + /* HBM 670 ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 00 /* HBM_670 ON */ + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-hbm-off-aod-on-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 13 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM 670 OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 02 /* HBM_670 OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF /* 430nit */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 01 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + ]; + qcom,mdss-dsi-panel-gamma-flash-pre-read-1-command = [ + /*Level2 key Enable*/ + 29 01 00 00 00 00 03 F0 5A 5A + //07 01 00 00 00 00 01 01 + //29 00 00 00 00 00 05 2A 00 00 05 9F + //29 00 00 00 00 00 05 2B 00 00 0C 2F + /*OTP key Enable*/ + 29 01 00 00 00 00 03 F1 F1 A2 + 29 01 00 00 00 00 0D C1 00 00 00 06 00 00 00 00 00 00 00 05 + 15 01 00 00 00 00 02 C0 03 + 29 01 00 00 00 00 0C C1 00 00 00 01 40 02 00 00 00 00 10 + 15 01 00 00 00 00 02 C0 03 + 29 01 00 00 00 00 0E C1 00 00 00 6B 00 00 00 0A 00 00 00 05 01 + 15 01 00 00 00 00 02 B0 07 + ]; + qcom,mdss-dsi-panel-gamma-flash-pre-read-2-command = [ + 15 01 00 00 00 00 02 C0 03 + 15 01 00 00 00 00 02 B0 08 + ]; + qcom,mdss-dsi-panel-gamma-flash-read-fb-command = [ + /*13th Parameter : 1byte Read value*/ + 06 01 00 00 00 00 02 FB 00 + ]; + qcom,mdss-dsi-panel-level2-key-enable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c8-smrps-command = [ + 37 01 00 00 05 00 02 87 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c8-command = [ + 06 01 00 00 00 00 02 C8 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c9-smrps-command = [ + 37 01 00 00 00 00 02 B4 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c9-command = [ + 06 01 00 00 00 00 02 C9 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-b3-smrps-command = [ + 37 01 00 00 00 00 02 2F 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-b3-command = [ + 06 01 00 00 00 00 02 B3 00 + ]; + qcom,mdss-dsi-panel-level2-key-disable-command = [ + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-night-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 39 01 00 0A 00 00 16 67 BB 0E 04 3E D8 12 09 05 EA 41 E2 D0 E5 09 F6 D0 D0 11 F8 FE DC + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-p3-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 E0 03 00 11 E2 01 0D 08 E5 1A FA FC E5 09 F6 EA F3 01 FE FF F7 + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 FF 00 00 00 FF 00 00 00 FF 00 FF FF FF 00 FF FF FF 00 FF FF FF + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-dci-p3-off-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 03 67 00 01 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-loading-effect-enable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 01 + 29 01 00 00 00 00 02 95 81 + 29 01 00 00 00 00 02 B0 14 + 29 01 00 00 00 00 03 95 FF 6D + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-loading-effect-disable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 01 + 29 01 00 00 00 00 02 95 A1 + 29 01 00 00 00 00 02 B0 14 + 29 01 00 00 00 00 03 95 28 28 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-customer-srgb-enable-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 10 00 02 B0 02 + 29 01 00 00 00 00 16 67 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-customer-p3-enable-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 10 00 02 B0 02 + 29 01 00 00 00 00 16 67 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-command = [ + 15 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 0A 00 02 B0 02 + 29 01 00 00 0A 00 16 67 FF 05 00 0B EB 00 07 00 FF 14 F8 EA F0 03 F5 DE F5 00 FF FF FF + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-seed-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 D3 03 00 11 E4 01 0B 06 F0 1A FA FC E5 09 F6 EA F3 01 FC FF EA + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-seed-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-customer-p3-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-customer-srgb-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-loading-effect-enable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-loading-effect-disable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-p3-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-night-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-dci-p3-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-new-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-samsung-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-hbm-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-off-aod-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-aod-on-command-1-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-on-command-2-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-pre-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-code-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-state-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-production-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-post-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-brightness-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-brightness-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-on-command-1-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-2-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-3-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-4-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-5-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-gamma-flash-pre-read-1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-flash-pre-read-2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-flash-read-fb-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-level2-key-enable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c8-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c8-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c9-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c9-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-b3-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-b3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-level2-key-disable-command-state = "dsi_lp_mode"; + qcom,panel-roi-alignment=<540 60 540 60 540 60>; + qcom,compression-mode = "dsc"; + qcom,lm-split = <540 540>; + qcom,mdss-dsc-encoders = <2>; + qcom,mdss-dsc-slice-height = <60>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@3{ + qcom,display-topology = <1 1 1>,<2 2 1>; + qcom,default-topology-index = <1>; + qcom,mdss-mdp-transfer-time-us = <8000>; //for 90fps + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-clockrate = <1100000000>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3120>; + qcom,mdss-dsi-h-front-porch = <16>; + qcom,mdss-dsi-h-back-porch = <8>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <4>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0A 00]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9F>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-panel-id1-command = [06 01 00 00 00 00 02 0A 00]; + qcom,mdss-dsi-panel-id2-command = [06 01 00 00 00 00 02 0E 00]; + qcom,mdss-dsi-panel-id3-command = [06 01 00 00 00 00 02 0F 00]; + qcom,mdss-dsi-panel-id4-command = [06 01 00 00 00 00 02 C4 00]; + qcom,mdss-dsi-panel-id5-command = [06 01 00 00 00 00 02 E7 00]; + qcom,mdss-dsi-panel-id6-command = [06 01 00 00 00 00 02 EA 00]; + qcom,mdss-dsi-panel-id7-command = [06 01 00 00 00 00 02 FB 00]; + qcom,mdss-dsi-panel-read-register-open-command = [ + 39 01 00 00 00 00 03 F0 5A 5A]; + qcom,mdss-dsi-panel-read-register-close-command = [ + 39 01 00 00 00 00 03 F0 A5 A5]; + qcom,mdss-dsi-panel-read-esd-registed-longread-command = [ + 37 01 00 00 05 00 02 22 00 + ]; + qcom,mdss-dsi-panel-id1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id4-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id5-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id6-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id7-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-open-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-close-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-esd-registed-longread-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-timing-switch-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + //29 01 00 00 00 00 03 9F A5 A5 + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 00 /* Scaler disable */ + 29 01 00 00 00 00 05 2A 00 00 05 9F /* CASET */ + 29 01 00 00 00 00 05 2B 00 00 0C 2F /* PASET */ + 39 01 00 00 00 00 5A 0A /* PPS Setting (1440 x 3120) (initial value) */ + 10 00 00 89 30 80 0C 30 + 05 A0 00 41 02 D0 02 D0 + 02 00 02 C2 00 20 06 58 + 00 0A 00 0F 01 E0 01 2D + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A B6 + 2A F4 2A F4 4B 34 63 74 + 00 + 15 01 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + //29 01 00 00 00 00 03 9F 5A 5A + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 25 09 0A 06 02 04 00 1E 1A]; + qcom,mdss-dsi-t-clk-pre = <0x1E>; + qcom,mdss-dsi-t-clk-post = <0x1A>; + qcom,mdss-dsi-on-command = [ + /* DSC Setting */ + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 00 /* Scaler disable */ + 39 01 00 00 00 00 5A 0A /* PPS Setting (1440 x 3120) (initial value) */ + 10 00 00 89 30 80 0C 30 + 05 A0 00 41 02 D0 02 D0 + 02 00 02 C2 00 20 06 58 + 00 0A 00 0F 01 E0 01 2D + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A B6 + 2A F4 2A F4 4B 34 63 74 + 00 + /* Sleep Out(11h) */ + 05 01 00 00 0A 00 01 11 + /* Common Setting */ + 15 00 00 00 00 00 02 35 00 /* TE On(Vsync) */ + /* CASET/PASET Setting */ + 39 01 00 00 00 00 05 2A 00 00 05 9F /* CASET */ + 39 01 00 00 00 00 05 2B 00 00 0C 2F /* PASET */ + /* TSP SYNC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 0A B9 01 C0 3C 0B 00 00 00 11 03 /* SYNC ENABLE */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* FD(Fast Discharge) Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 45 /* FD setting (Normal mode) */ + 15 01 00 00 00 00 02 B5 48 + 39 01 00 00 00 00 03 F0 A5 A5 + /* FFC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 1E + 39 01 00 00 00 00 06 C5 09 10 B4 24 FB /* FFC Setting; 0x09 : Enable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* OSC Spread Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 37 + 39 01 00 00 00 00 06 C5 04 FF 00 01 64 /* FFC Setting; 0x04 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 86 /* Global para */ + 15 01 00 00 00 00 02 EB 01 /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC A5 A5 + /* Brightness Control */ + 39 01 00 00 00 00 03 F0 5A 5A /* Dimming Setting */ + 15 01 00 00 00 00 02 B0 05 + 15 01 00 00 00 00 02 B1 01 /* Dimming Speed Setting : 0x01 : 1Frame*/ + 15 01 00 00 00 00 02 B0 02 + 15 01 00 00 00 00 02 B5 D3 /* 0xD3 : ELVSS DIM ON */ + 15 01 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* Display On */ + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-113mhz-osc-dsi-on-command = [ + /* DSC Setting */ + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 00 /* Scaler disable */ + 39 01 00 00 00 00 5A 0A /* PPS Setting (1440 x 3120) (initial value) */ + 10 00 00 89 30 80 0C 30 + 05 A0 00 41 02 D0 02 D0 + 02 00 02 C2 00 20 06 58 + 00 0A 00 0F 01 E0 01 2D + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A B6 + 2A F4 2A F4 4B 34 63 74 + 00 + /* Sleep Out(11h) */ + 05 01 00 00 0A 00 01 11 + /* Common Setting */ + 15 00 00 00 00 00 02 35 00 /* TE On(Vsync) */ + /* CASET/PASET Setting */ + 39 01 00 00 00 00 05 2A 00 00 05 9F /* CASET */ + 39 01 00 00 00 00 05 2B 00 00 0C 2F /* PASET */ + /* TSP SYNC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 0A B9 01 C0 3C 0B 00 00 00 11 03 /* SYNC ENABLE */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* FD(Fast Discharge) Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 45 /* FD setting (Normal mode) */ + 15 01 00 00 00 00 02 B5 48 + 39 01 00 00 00 00 03 F0 A5 A5 + /* FFC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 1E + 39 01 00 00 00 00 06 C5 08 10 B4 24 FB /* FFC Setting; 0x08 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* OSC Spread Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 37 + 39 01 00 00 00 00 06 C5 04 FF 00 01 64 /* FFC Setting; 0x04 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 86 /* Global para */ + 15 01 00 00 00 00 02 EB 01 /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC A5 A5 + /* Brightness Control */ + 39 01 00 00 00 00 03 F0 5A 5A /* Dimming Setting */ + 15 01 00 00 00 00 02 B0 05 + 15 01 00 00 00 00 02 B1 01 /* Dimming Speed Setting : 0x01 : 1Frame*/ + 15 01 00 00 00 00 02 B0 02 + 15 01 00 00 00 00 02 B5 D3 /* 0xD3 : ELVSS DIM ON */ + 15 01 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* Display On */ + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-113mhz-osc-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-off-command=[ + 05 01 00 00 0A 00 02 28 00 + 05 01 00 00 78 00 02 10 00 + ]; + qcom,mdss-dsi-panel-hbm-brightness-on-command = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 53 /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 00 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM Mode ON */ + 15 01 00 00 0C 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + ]; + qcom,mdss-dsi-panel-hbm-brightness-off-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 53 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 01 00 00 0C 00 03 F0 A5 A5 /* Level2 key Access Disable */ + ]; + qcom,mdss-dsi-panel-hbm-on-command-1 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-2 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-3 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-4 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-5 = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 93 /* 0x93 : ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 01 00 00 10 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM MODE ON */ + 15 00 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + 29 01 00 00 0C 00 03 51 0F FF /* 600nit */ + /* HBM 670 ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 00 /* HBM_670 ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* 90Hz Setting */ + 15 01 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + ]; + qcom,mdss-dsi-panel-hbm-off-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 13 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM 670 OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 02 /* HBM_670 OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF /* 430nit */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 01 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + ]; + qcom,mdss-dsi-panel-serial-num-pre-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + 37 01 00 00 05 00 02 10 00 + ]; + qcom,mdss-dsi-panel-serial-num-command = [ + 06 01 00 00 00 00 01 A1 00 + ]; + qcom,mdss-dsi-panel-code-info-command = [ + 06 01 00 00 00 00 01 DA 00 + ]; + qcom,mdss-dsi-panel-stage-info-command = [ + 06 01 00 00 00 00 01 DB 00 + ]; + qcom,mdss-dsi-panel-production-info-command = [ + 06 01 00 00 00 00 01 DC 00 + ]; + qcom,mdss-dsi-panel-serial-num-post-command = [ + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-aod-on-command-1 = [ + ]; + qcom,mdss-dsi-panel-aod-on-command-2 = [ + ]; + qcom,mdss-dsi-panel-aod-off-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-samsung-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-new-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-hbm-on-command = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 93 /* 0x93 : ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 01 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM MODE ON */ + 15 00 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + 29 01 00 00 00 00 03 51 0F FF /* 600nit */ + /* HBM 670 ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 00 /* HBM_670 ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* 90Hz Setting */ + 15 01 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + ]; + qcom,mdss-dsi-panel-hbm-off-aod-on-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 13 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM 670 OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 02 /* HBM_670 OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF /* 430nit */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 01 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + ]; + qcom,mdss-dsi-panel-gamma-flash-pre-read-1-command = [ + /*Level2 key Enable*/ + 29 01 00 00 00 00 03 F0 5A 5A + //07 01 00 00 00 00 01 01 + //29 00 00 00 00 00 05 2A 00 00 05 9F + //29 00 00 00 00 00 05 2B 00 00 0C 2F + /*OTP key Enable*/ + 29 01 00 00 00 00 03 F1 F1 A2 + 29 01 00 00 00 00 0D C1 00 00 00 06 00 00 00 00 00 00 00 05 + 15 01 00 00 00 00 02 C0 03 + 29 01 00 00 00 00 0C C1 00 00 00 01 40 02 00 00 00 00 10 + 15 01 00 00 00 00 02 C0 03 + 29 01 00 00 00 00 0E C1 00 00 00 6B 00 00 00 0A 00 00 00 05 01 + 15 01 00 00 00 00 02 B0 07 + ]; + qcom,mdss-dsi-panel-gamma-flash-pre-read-2-command = [ + 15 01 00 00 00 00 02 C0 03 + 15 01 00 00 00 00 02 B0 08 + ]; + qcom,mdss-dsi-panel-gamma-flash-read-fb-command = [ + /*13th Parameter : 1byte Read value*/ + 06 01 00 00 00 00 02 FB 00 + ]; + qcom,mdss-dsi-panel-level2-key-enable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c8-smrps-command = [ + 37 01 00 00 00 00 02 87 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c8-command = [ + 06 01 00 00 00 00 02 C8 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c9-smrps-command = [ + 37 01 00 00 00 00 02 B4 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c9-command = [ + 06 01 00 00 00 00 02 C9 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-b3-smrps-command = [ + 37 01 00 00 00 00 02 2F 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-b3-command = [ + 06 01 00 00 00 00 02 B3 00 + ]; + qcom,mdss-dsi-panel-level2-key-disable-command = [ + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-night-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 39 01 00 0A 00 00 16 67 BB 0E 04 3E D8 12 09 05 EA 41 E2 D0 E5 09 F6 D0 D0 11 F8 FE DC + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-p3-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 E0 03 00 11 E2 01 0D 08 E5 1A FA FC E5 09 F6 EA F3 01 FE FF F7 + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 FF 00 00 00 FF 00 00 00 FF 00 FF FF FF 00 FF FF FF 00 FF FF FF + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-dci-p3-off-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 03 67 00 01 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-loading-effect-enable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 01 + 29 01 00 00 00 00 02 95 81 + 29 01 00 00 00 00 02 B0 14 + 29 01 00 00 00 00 03 95 FF 6D + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-loading-effect-disable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 01 + 29 01 00 00 00 00 02 95 A1 + 29 01 00 00 00 00 02 B0 14 + 29 01 00 00 00 00 03 95 28 28 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-customer-srgb-enable-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 10 00 02 B0 02 + 29 01 00 00 00 00 16 67 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-customer-p3-enable-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 10 00 02 B0 02 + 29 01 00 00 00 00 16 67 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-command = [ + 15 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 0A 00 02 B0 02 + 29 01 00 00 0A 00 16 67 FF 05 00 0B EB 00 07 00 FF 14 F8 EA F0 03 F5 DE F5 00 FF FF FF + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-seed-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 D3 03 00 11 E4 01 0B 06 F0 1A FA FC E5 09 F6 EA F3 01 FC FF EA + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-seed-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-customer-p3-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-customer-srgb-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-loading-effect-enable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-loading-effect-disable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-p3-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-night-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-dci-p3-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-new-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-samsung-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-hbm-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-off-aod-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-aod-on-command-1-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-on-command-2-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-pre-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-code-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-state-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-production-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-post-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-brightness-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-brightness-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-on-command-1-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-2-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-3-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-4-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-5-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-gamma-flash-pre-read-1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-flash-pre-read-2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-flash-read-fb-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-level2-key-enable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c8-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c8-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c9-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c9-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-b3-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-b3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-level2-key-disable-command-state = "dsi_lp_mode"; + qcom,panel-roi-alignment=<720 65 720 65 720 65>; + qcom,compression-mode = "dsc"; + qcom,lm-split = <720 720>; + qcom,mdss-dsc-encoders = <2>; + qcom,mdss-dsc-slice-height = <65>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + }; + }; +}; + +&dsi_samsung_oneplus_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; + qcom,platform-reset-gpio-tmo = <&tlmm 78 0>; + qcom,platform-poc-gpio = <&tlmm 130 0>; + qcom,tp1v8-gpio = <&tlmm 119 0>; +}; + +&soc { + dsi_samsung_oneplus_dsc_cmd_display { + qcom,dsi-display-active; + }; +}; + +&dsi_samsung_oneplus_dsc_cmd { + qcom,mdss-dsi-display-timings { + timing@0 { /* wqhd 60hz */ + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 25 09 0A 06 02 04 00 1E 1A]; + qcom,display-topology = <1 1 1>,<2 2 1>; + qcom,default-topology-index = <1>; + qcom,panel-roi-alignment=<720 65 720 65 720 65>; + }; + timing@1 { /* fhd 90hz */ + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 25 09 0A 06 02 04 00 1E 1A]; + qcom,display-topology = <1 1 1>,<2 2 1>; + qcom,default-topology-index = <1>; + qcom,panel-roi-alignment=<540 60 540 60 540 60>; + }; + timing@2 { /* fhd 60hz */ + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 25 09 0A 06 02 04 00 1E 1A]; + qcom,display-topology = <1 1 1>,<2 2 1>; + qcom,default-topology-index = <1>; + qcom,panel-roi-alignment=<540 60 540 60 540 60>; + }; + timing@3 { /* wqhd 90hz */ + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 25 09 0A 06 02 04 00 1E 1A]; + qcom,display-topology = <1 1 1>,<2 2 1>; + qcom,default-topology-index = <1>; + qcom,panel-roi-alignment=<720 65 720 65 720 65>; + }; + }; +}; + + diff --git a/arch/arm64/boot/dts/qcom/dsi-panel-samsung_s6e3fc2x01.dtsi b/arch/arm64/boot/dts/qcom/dsi-panel-samsung_s6e3fc2x01.dtsi new file mode 100755 index 0000000000000000000000000000000000000000..bd7245490744a607ec1fc7d13a88e7cd0faa9ea4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/dsi-panel-samsung_s6e3fc2x01.dtsi @@ -0,0 +1,435 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_samsung_s6e3fc2x01_cmd: qcom,mdss_dsi_samsung_s6e3fc2x01_cmd { + qcom,mdss-dsi-panel-name = "samsung s6e3fc2x01 cmd mode dsi panel"; + qcom,mdss-dsi-panel-manufacture = "SAMSUNG"; + qcom,mdss-dsi-panel-version = "S6E3FC2X01"; + qcom,mdss-dsi-backlight-version = "SAMSUNG"; + qcom,mdss-dsi-backlight-manufacture = "SAMSUNG"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-reset-sequence = <1 7>, <0 1>, <1 5>; + qcom,mdss-pan-physical-width-dimension = <68>; + qcom,mdss-pan-physical-height-dimension = <145>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + //qcom,mdss-dsi-te-check-enable; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0A 08]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9F>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-high-brightness-panel; + qcom,mdss-dsi-acl-cmd-index = <0>; + qcom,mdss-dsi-acl-mode-index = <1>; + qcom,mdss-bl-high2bit; + //qcom,mdss-dsi-panel-status-check-mode = "te_signal_check"; + qcom,mdss-dsi-panel-seria-num-year-index = <12>; + qcom,mdss-dsi-panel-seria-num-mon-index = <12>; + qcom,mdss-dsi-panel-seria-num-day-index = <13>; + qcom,mdss-dsi-panel-seria-num-hour-index = <14>; + qcom,mdss-dsi-panel-seria-num-min-index = <15>; + qcom,mdss-dsi-panel-seria-num-sec-index = <16>; + qcom,ulps-enabled; + qcom,mdss-brightness-max-level = <1023>; + /* HDR Setting */ + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15635 16450 34000 16000 13250 34500 7500 3000>; + qcom,mdss-dsi-panel-peak-brightness = <8000000>; + qcom,mdss-dsi-panel-average-brightness = <2000000>; + qcom,mdss-dsi-panel-blackness-level = <5>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <72>; + qcom,mdss-dsi-h-back-porch = <36>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <32>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <1037000000>;// 518.5MHZ + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 03 9F A5 A5 + 05 01 00 00 05 00 02 11 00 + 39 01 00 00 00 00 03 9F 5A 5A + /*FD setting*/ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 01 + 15 01 00 00 00 00 02 CD 01 + 39 01 00 00 0F 00 03 F0 A5 A5 + /*TE ON*/ + 39 01 00 00 00 00 03 9F A5 A5 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 03 9F 5A 5A + /*MIC Setting*/ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 08 EB 17 41 92 0E 10 82 5A + 39 01 00 00 00 00 03 F0 A5 A5 + /*CASET/PASET*/ + 39 01 00 00 00 00 05 2A 00 00 04 37 + 39 01 00 00 00 00 05 2B 00 00 09 23 + /*TSP H_sync Setting*/ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 B0 09 + 39 01 00 00 00 00 03 E8 10 30 + 39 01 00 00 00 00 03 F0 A5 A5 + /*Dimming Setting*/ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 07 + 15 01 00 00 00 00 02 B7 01 + 15 01 00 00 00 00 02 B0 08 + 15 01 00 00 00 00 02 B7 12 + 39 01 00 00 00 00 03 F0 A5 A5 + /*ESD improvement Setting*/ + 39 01 00 00 00 00 03 FC 5A 5A + 39 01 00 00 00 00 02 B0 01 + 39 01 00 00 00 00 02 E3 88 + 39 01 00 00 00 00 02 B0 07 + 39 01 00 00 00 00 02 ED 67 + 39 01 00 00 00 00 03 FC A5 A5 + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 F0 A5 A5 + /*ACL off*/ + 39 01 00 00 01 00 02 55 00 + /*SEED OFF*/ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 B1 00 01 + 39 01 00 00 00 00 03 F0 A5 A5 + /*SEED TCS OFF*/ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 B3 00 C1 + 39 01 00 00 00 00 03 F0 A5 A5 + /*Display on*/ + 39 01 00 00 00 00 03 9F A5 A5 + 05 01 00 00 00 00 02 29 00 + 39 01 00 00 00 00 03 9F 5A 5A + ]; + qcom,mdss-dsi-off-command = [ + 39 01 00 00 00 00 03 9F A5 A5 + 05 01 00 00 0A 00 01 28 + 05 01 00 00 00 00 01 10 + 39 01 00 00 00 00 03 9F 5A 5A + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 05 + 15 01 00 00 00 00 02 F4 01 + 39 01 00 00 96 00 03 F0 A5 A5 + ]; + //qcom,mdss-dsi-post-on-backlight=[ + // 39 01 00 00 00 00 03 9F A5 A5 + // 05 01 00 00 00 00 01 29 + // 39 01 00 00 00 00 03 9F 5A 5A + //]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + /**************************************************************/ + qcom,mdss-dsi-panel-hbm-brightness-on-command = [ + /*HBM ON */ + 39 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 53 E0 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-hbm-brightness-off-command = [ + /* DLY ON */ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 04 B7 00 01 5B + 39 00 00 00 00 00 03 F0 A5 A5 + + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-hbm-on-command-5 = [ + /*ELVSS OFF*/ + 39 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 08 + 15 00 00 00 00 00 02 B7 12 + 39 01 00 00 10 00 03 F0 A5 A5 + /*DLY OFF*/ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 04 B7 00 01 5B + 39 00 00 00 00 00 03 F0 A5 A5 + /*HBM ON */ + 15 00 00 00 00 00 02 53 E0 + 39 01 00 00 0E 00 03 51 03 FF + /*HBM 670nit*/ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 BD 00 00 + 39 00 00 00 00 00 03 F0 A5 A5 + /*DLY OFF*/ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 04 B7 00 01 53 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-hbm-off-command = [ + /*HBM 670nit off*/ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 BD 00 02 + 39 00 00 00 00 00 03 F0 A5 A5 + /*HBM off */ + 15 01 00 00 00 00 02 53 20 + ]; + qcom,mdss-dsi-panel-hbm-max-brightness-command-on = [ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 07 + 15 01 00 00 00 00 02 B7 7F + 15 01 00 00 00 00 02 B0 08 + 15 01 00 00 80 00 02 B7 92 + 39 01 00 00 40 00 02 53 E8 + 39 01 00 00 80 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 51 03 FF + ]; + qcom,mdss-dsi-panel-hbm-max-brightness-command-off = [ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 07 + 15 01 00 00 40 00 02 B7 7F + 15 01 00 00 00 00 02 B0 08 + 15 01 00 00 40 00 02 B7 92 + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 10 00 02 53 28 + ]; + qcom,mdss-dsi-panel-hbm-brightness-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-brightness-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-hbm-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-on-command-5-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-max-brightness-command-on-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-max-brightness-command-off-state = "dsi_lp_mode"; + qcom,mdss-dsi-hbm-off-command-state = "dsi_hs_mode"; + + qcom,mdss-dsi-panel-aod-on-command-1 = [ + 39 01 00 00 00 00 03 9F A5 A5 + 05 01 00 00 0A 00 01 28 + 05 01 00 00 78 00 01 10 + 05 01 00 00 05 00 01 11 + 39 01 00 00 00 00 03 9F 5A 5A + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 01 + 15 01 00 00 64 00 02 CD 02 + 15 01 00 00 00 00 02 53 23 + 15 01 00 00 00 00 02 B0 A5 + 15 01 00 00 00 00 02 C7 00 + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 9F A5 A5 + 05 01 00 00 00 00 01 29 + 39 01 00 00 00 00 03 9F 5A 5A + ]; + qcom,mdss-dsi-panel-aod-on-command-2 = [ + + ]; + + qcom,mdss-dsi-panel-aod-off-command = [ + /*ELVSS OFF*/ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 08 + /*DLY OFF*/ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 04 B7 00 01 5B + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 01 + 15 01 00 00 00 00 02 CD 01 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 F0 A5 A5 + /*DLY ON*/ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 04 B7 00 01 53 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-aod-off-samsung-command = [ + + ]; + qcom,mdss-dsi-panel-aod-off-new-command = [ + + ]; + qcom,mdss-dsi-panel-aod-off-new-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-samsung-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-hbm-on-command = [ + /*ELVSS OFF*/ + 39 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 08 + 15 00 00 00 00 00 02 B7 12 + 39 00 00 00 00 00 03 F0 A5 A5 + /*DL0 OFF*/ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 04 B7 00 01 5B + 39 00 00 00 00 00 03 F0 A5 A5 + /*HB0 ON */ + 15 00 00 00 00 00 02 53 E0 + 39 01 00 00 00 00 03 51 03 FF + /*HB0 670nit*/ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 BD 00 00 + 39 01 00 00 00 00 03 F0 A5 A5 + /*DL0 OFF*/ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 04 B7 00 01 53 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-aod-off-hbm-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-off-aod-on-command = [ + /*HBM 670nit off*/ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 BD 00 02 + 39 00 00 00 00 00 03 F0 A5 A5 + /*HBM off */ + 15 01 00 00 00 00 02 53 20 + ]; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command = [ + + 39 01 00 00 00 00 02 81 90 + 39 01 00 00 00 00 03 f0 5A 5A + 39 01 00 00 00 00 02 B0 02 + 39 01 00 00 00 00 16 B1 CE 01 02 1D E3 00 07 0D E9 28 FD F0 D3 0A E2 EA EA 01 FF FF F2 + 39 01 00 00 00 00 03 B1 00 00 + 39 01 00 00 00 00 03 f0 A5 A5 + + ]; + qcom,mdss-dsi-panel-display-p3-mode-on-command = [ + 39 01 00 00 00 00 02 81 90 + 39 01 00 00 00 00 03 f0 5A 5A + 39 01 00 00 00 00 02 B0 02 + 39 01 00 00 00 00 16 B1 CE 01 02 1D E3 00 07 0D E9 28 FD F0 D3 0A E2 EA EA 01 FF FF F2 + 39 01 00 00 00 00 03 B1 00 00 + 39 01 00 00 00 00 03 f0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command = [ + 39 01 00 00 00 00 02 81 90 + 39 01 00 00 00 00 03 f0 5A 5A + 39 01 00 00 00 00 02 B0 02 + 39 01 00 00 00 00 16 B1 FF 00 00 00 FF 00 00 00 FF 00 FF FF FF 00 FF FF FF 00 FF FF FF + 39 01 00 00 00 00 03 B1 00 00 + 39 01 00 00 00 00 03 f0 A5 A5 + ]; + qcom,mdss-dsi-panel-dci-p3-off-command = [ + + ]; + qcom,mdss-dsi-customer-srgb-enable-command = [ + 39 01 00 00 00 00 02 81 90 + 39 01 00 00 00 00 03 f0 5A 5A + 39 01 00 00 00 00 02 B0 02 + 39 01 00 00 00 00 16 B1 CE 01 02 1D E3 00 07 0D E9 28 FD F0 D3 0A E2 EA EA 01 FF FF F2 + 39 01 00 00 00 00 03 B1 00 00 + 39 01 00 00 00 00 03 f0 A5 A5 + ]; + qcom,mdss-dsi-customer-p3-enable-command = [ + 39 01 00 00 00 00 02 81 90 + 39 01 00 00 00 00 03 f0 5A 5A + 39 01 00 00 00 00 02 B0 02 + 39 01 00 00 00 00 16 B1 FF 00 00 00 FF 00 00 00 FF 00 FF FF FF 00 FF FF FF 00 FF FF F2 + 39 01 00 00 00 00 03 B1 00 00 + 39 01 00 00 00 00 03 f0 A5 A5 + ]; + qcom,mdss-dsi-customer-p3-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-customer-srgb-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-p3-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-off-aod-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-on-command-2-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-aod-mode-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-command = [ + 06 01 00 00 00 00 01 A1 + ]; + + qcom,mdss-dsi-panel-serial-num-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0E 08]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id-command = [06 01 00 01 05 00 02 DC 08]; + qcom,mdss-dsi-panel-id-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id1-command = [06 01 00 01 05 00 02 0A 08]; + qcom,mdss-dsi-panel-id1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id2-command = [06 01 00 01 05 00 02 0E 08]; + qcom,mdss-dsi-panel-id2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id3-command = [06 01 00 01 05 00 02 E0 08]; + qcom,mdss-dsi-panel-id3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id4-command = [06 01 00 01 05 00 02 0F 08]; + qcom,mdss-dsi-panel-id4-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id5-command = [06 01 00 01 05 00 02 E3 08]; + qcom,mdss-dsi-panel-id5-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id6-command = [06 01 00 01 05 00 02 E5 08]; + qcom,mdss-dsi-panel-id6-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id7-command = [06 01 00 01 05 00 02 FB 08]; + qcom,mdss-dsi-panel-id7-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-level1-command = [15 01 00 00 00 00 02 B0 08]; + qcom,mdss-dsi-panel-hbm-level1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-read-command = [06 01 00 01 05 00 02 B7 08]; + qcom,mdss-dsi-panel-hbm-read-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-open-command = [ + 39 01 00 00 00 00 03 FC 5A 5A]; + qcom,mdss-dsi-panel-read-register-close-command = [ + 39 01 00 00 00 00 03 FC A5 A5]; + qcom,mdss-dsi-panel-read-register-open-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-close-command-state = "dsi_lp_mode"; + }; + }; + }; +}; + +&dsi_samsung_s6e3fc2x01_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; + qcom,platform-poc-gpio = <&tlmm 130 0>; + qcom,tp1v8-gpio = <&tlmm 119 0>; +}; + +&soc { + dsi_samsung_s6e3fc2x01_cmd_display { + qcom,dsi-display-active; + }; +}; + +&dsi_samsung_s6e3fc2x01_cmd { + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 25 23 + 09 09 06 03 04 00 1C 19]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + + diff --git a/arch/arm64/boot/dts/qcom/dsi-panel-samsung_sofef00_m_video.dtsi b/arch/arm64/boot/dts/qcom/dsi-panel-samsung_sofef00_m_video.dtsi new file mode 100755 index 0000000000000000000000000000000000000000..15a81d8158d478620e116c17cf2cd6439ce987b1 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/dsi-panel-samsung_sofef00_m_video.dtsi @@ -0,0 +1,103 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_samsung_sofef00_m_video: qcom,mdss_dsi_samsung_sofef00_m_video { + qcom,mdss-dsi-panel-name = + "samsung sofef00_m video mode dsi panel"; + qcom,mdss-dsi-panel-manufacture = "SAMSUNG"; + qcom,mdss-dsi-panel-version = "SOFEF00_M"; + qcom,mdss-dsi-backlight-version = "SAMSUNG"; + qcom,mdss-dsi-backlight-manufacture = "SAMSUNG"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-reset-sequence = <1 5>, <0 2>, <1 12>; + qcom,mdss-pan-physical-width-dimension = <68>; + qcom,mdss-pan-physical-height-dimension = <145>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-high-brightness-panel; + qcom,mdss-bl-high2bit; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2280>; + qcom,mdss-dsi-h-front-porch = <112>; + qcom,mdss-dsi-h-back-porch = <36>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <12>; + qcom,mdss-dsi-v-front-porch = <36>; + qcom,mdss-dsi-v-pulse-width = <8>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-on-command = [ + 05 01 00 00 0A 00 02 11 00 + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 03 F0 A5 A5 + 15 01 00 00 00 00 02 53 20 + 15 01 00 00 00 00 02 55 00 + ]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 28 00 02 28 00 + 05 01 00 00 A0 00 02 10 00 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + }; + }; + }; +}; + +&dsi_samsung_sofef00_m_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; + qcom,platform-reset-gpio-tmo = <&tlmm 78 0>; +}; + +&soc { + dsi_samsung_sofef00_m_video_display { + qcom,dsi-display-active; + }; +}; + +&dsi_samsung_sofef00_m_video { + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 20 07 07 0c 12 06 + 08 06 03 04 00]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/dsi-panel-samsung_sofef03f_m_fhd_dsc_cmd.dtsi b/arch/arm64/boot/dts/qcom/dsi-panel-samsung_sofef03f_m_fhd_dsc_cmd.dtsi new file mode 100755 index 0000000000000000000000000000000000000000..1f92da987b0760cf074e405826b1ea6b46bee7ba --- /dev/null +++ b/arch/arm64/boot/dts/qcom/dsi-panel-samsung_sofef03f_m_fhd_dsc_cmd.dtsi @@ -0,0 +1,915 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_samsung_sofef03f_m_fhd_dsc_cmd: qcom,mdss_dsi_samsung_sofef03f_m_fhd_dsc_cmd { + qcom,mdss-dsi-panel-name = "samsung sofef03f_m fhd cmd mode dsc dsi panel"; + qcom,mdss-dsi-panel-manufacture = "SAMSUNG"; + qcom,mdss-dsi-panel-version = "DSC"; + qcom,mdss-dsi-backlight-version = "SAMSUNG"; + qcom,mdss-dsi-backlight-manufacture = "SAMSUNG"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 1>, <1 10>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-bl-min-level = <6>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-default-val = <160>; + qcom,mdss-brightness-max-level = <1023>; + qcom,mdss-pan-physical-width-dimension = <68>; + qcom,mdss-pan-physical-height-dimension = <145>; + qcom,mdss-dsi-init-delay-us = <1000>; + //qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-high-brightness-panel; + qcom,mdss-bl-high2bit; + qcom,mdss-loading-effect; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,dynamic-mode-switch-enabled; + qcom,dynamic-mode-switch-type = "dynamic-switch-immediate"; + /* HDR Setting */ + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15635 16450 34000 16000 13250 34500 7500 3000>; + qcom,mdss-dsi-panel-peak-brightness = <6800000>; + qcom,mdss-dsi-panel-average-brightness = <2000000>; + qcom,mdss-dsi-panel-blackness-level = <2000>; + qcom,mdss-dsi-panel-seria-num-year-index = <12>; + qcom,mdss-dsi-panel-seria-num-mon-index = <12>; + qcom,mdss-dsi-panel-seria-num-day-index = <13>; + qcom,mdss-dsi-panel-seria-num-hour-index = <14>; + qcom,mdss-dsi-panel-seria-num-min-index = <15>; + qcom,mdss-dsi-panel-seria-num-sec-index = <16>; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [ + 06 01 00 00 00 00 02 0A 00 + ]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9C>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + /* + * ************************************************************************************************************************ + * DMS (Dynamic Mode Switch) + * ************************************************************************************************************************ + */ + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,display-topology = <1 1 1>, <2 2 1>; + qcom,default-topology-index = <1>; + qcom,mdss-mdp-transfer-time-us = <8000>; //for 60fps + qcom,mdss-dsi-timing-default; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-clockrate = <1100000000>; + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 25 09 0A 06 02 04 00 1E 1A]; + qcom,mdss-dsi-t-clk-pre = <0x1E>; + qcom,mdss-dsi-t-clk-post = <0x1A>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <52>; + qcom,mdss-dsi-h-back-porch = <24>; + qcom,mdss-dsi-h-pulse-width = <24>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <1208>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [ + 06 01 00 00 00 00 02 0A 00 + ]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9C>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-panel-read-register-open-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + ]; + qcom,mdss-dsi-panel-id1-command = [ + 06 01 00 00 00 00 02 0A 00 + ]; + qcom,mdss-dsi-panel-id2-command = [ + 06 01 00 00 00 00 02 B6 00 + ]; + qcom,mdss-dsi-panel-read-register-close-command = [ + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + + qcom,mdss-dsi-timing-switch-command = [ + /* 60hz â†?90hz Transition */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 60 00 /* 0x00 : 60 Hz */ + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-on-command = [ + /* DSC Setting */ + 39 01 00 00 00 00 02 9D 01 /* Compression Enable */ + 39 01 00 00 00 00 81 9E /* PPS Setting */ + 11 00 00 89 30 80 09 60 + 04 38 00 1E 02 1C 02 1C + 02 00 02 0E 00 20 02 E3 + 00 07 00 0C 03 50 03 64 + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A F6 + 2B 34 2B 74 3B 74 6B F4 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + + /* Sleep Out(11h) */ + 05 01 00 00 0A 00 01 11 + + /* Common Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 35 00 /* TE Vsync On */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* PAGE ADDRESS SET */ + 39 01 00 00 00 00 05 2A 00 00 04 37 + 39 01 00 00 00 00 05 2B 00 00 09 5F + /* ELVSS Dim Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 B0 05 + 39 01 00 00 00 00 02 B7 13 + 39 01 00 00 00 00 03 F0 A5 A5 + /* Dimming Delay control */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 B0 01 + 39 01 00 00 00 00 02 B7 53 /* 0x53 : DLY ON */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* Dimming Speed Control */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 B0 06 + 39 01 00 00 00 00 02 B7 01 /* 0x01 : 1 Frames */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* TSP H_sync Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 DF 83 /* TSP H Sync ON */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* FD(Fast Discharge) Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 B0 0A + 39 01 00 00 00 00 02 D5 05 /* FD Set Normal Mode */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* ERR_FG Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 B0 02 + 39 01 00 00 00 00 05 EC 00 C2 C2 42 + 39 01 00 00 00 00 02 B0 0D + 39 01 00 00 00 00 02 EC 19 + 39 01 00 00 00 00 03 F0 A5 A5 + /* OFC Setting */ + 39 01 00 00 00 00 03 FC 5A 5A + 39 01 00 00 00 00 02 B0 01 + 39 01 00 00 00 00 04 E4 A6 C3 42 + 39 01 00 00 00 00 0F E9 11 75 A6 C3 42 96 2F 58 96 2F 58 00 32 32 + 39 01 00 00 00 00 03 FC A5 A5 + /* Brightness Control */ + 39 01 00 00 00 00 02 53 20 /* 0x20 Normal transition */ + /* 60hz â†?90hz Transition */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 60 00 /* 0x00 : 60 Hz */ + 39 01 00 00 3C 00 03 F0 A5 A5 + + /* Display On */ + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-dsi-off-command=[ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 64 00 02 10 00 + ]; + qcom,mdss-dsi-panel-hbm-brightness-on-command = [ + /* HBM Mode Setting */ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 B0 BB + 39 00 00 00 00 00 02 BA 77 + 39 00 00 00 00 00 02 B0 01 + 39 00 00 00 00 00 03 B7 57 FF + 39 00 00 00 00 00 02 B0 0A + 39 00 00 00 00 00 11 B7 00 + 01 02 03 24 45 46 47 68 09 + 6A 8B 8C 40 A1 02 + 39 00 00 00 00 00 02 B0 3C + 39 00 00 00 00 00 1B B7 41 + 65 4A 67 E7 FF 80 08 55 8A + A9 54 9F EA A8 B5 2B FC CA + 6D 50 DF AE A4 F4 E0 + 39 01 00 00 11 00 03 F0 A5 A5 + /* HBM Mode ON */ + 39 01 00 00 00 00 02 53 E0 + ]; + qcom,mdss-dsi-panel-hbm-brightness-off-command = [ + /* HBM Mode OFF */ + 39 00 00 00 00 00 02 53 20 + 39 01 00 00 11 00 03 51 03 FF + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 B0 BB + 39 00 00 00 00 00 02 BA F7 + 39 00 00 00 00 00 02 B0 01 + 39 00 00 00 00 00 03 B7 52 A8 + 39 00 00 00 00 00 02 B0 0A + 39 00 00 00 00 00 11 B7 00 + 00 00 00 21 41 41 41 62 02 + 62 82 83 43 A3 03 + 39 00 00 00 00 00 02 B0 3C + 39 00 00 00 00 00 1B B7 2E + 23 2F 37 C3 C9 41 64 63 4B + 04 FD 54 A5 97 5E 46 31 67 + E6 CB 71 87 65 7B 20 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-hbm-on-command-1 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-2 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-3 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-4 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-5 = [ + /* ELVSS Dim Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 B0 05 + 39 01 00 00 00 00 02 B7 13 /* 0x13 : ELVSS DIM OFF */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* Dimming Delay control */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 B0 01 + 39 01 00 00 00 00 02 B7 5B /* 0x5B : DLY OFF */ + 39 01 00 00 11 00 03 F0 A5 A5 + /* HBM Mode ON */ + 39 01 00 00 00 00 02 53 E0 /* 0xE0 Normal transition */ + 39 01 00 00 11 00 03 51 01 84 /* 670nit */ + /* Dimming Delay control */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 B0 01 + 39 01 00 00 00 00 02 B7 53 /* 0x53 : DLY ON */ + 39 01 00 00 07 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-hbm-off-command = [ + /* HBM Mode OFF */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 53 20 /* 0x20 Normal transition */ + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-serial-num-pre-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + 37 01 00 00 05 00 02 10 00 + ]; + qcom,mdss-dsi-panel-serial-num-command = [ + 06 01 00 00 00 00 01 A1 00 + ]; + qcom,mdss-dsi-panel-code-info-command = [ + 06 01 00 00 00 00 01 DA 00 + ]; + qcom,mdss-dsi-panel-stage-info-command = [ + 06 01 00 00 00 00 01 DB 00 + ]; + qcom,mdss-dsi-panel-production-info-command = [ + 06 01 00 00 00 00 01 DC 00 + ]; + qcom,mdss-dsi-panel-serial-num-post-command = [ + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-aod-on-command-1 = [ + ]; + qcom,mdss-dsi-panel-aod-on-command-2 = [ + ]; + qcom,mdss-dsi-panel-aod-off-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-samsung-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-new-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-hbm-on-command = [ + /* ELVSS Dim Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 B0 05 + 39 01 00 00 00 00 02 B7 13 /* 0x13 : ELVSS DIM OFF */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* Dimming Delay control */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 B0 01 + 39 01 00 00 00 00 02 B7 5B /* 0x5B : DLY OFF */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* HBM Mode ON */ + 39 01 00 00 00 00 02 53 E0 /* 0xE0 Normal transition */ + 39 01 00 00 00 00 03 51 01 84 /* 670nit */ + /* Dimming Delay control */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 B0 01 + 39 01 00 00 00 00 02 B7 53 /* 0x53 : DLY ON */ + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-hbm-off-aod-on-command = [ + /* HBM Mode OFF */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 53 20 /* 0x20 Normal transition */ + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command = [ + 29 01 00 00 00 00 02 81 90 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 01 + 29 01 00 00 00 00 16 B1 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 02 B1 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-night-mode-on-command = [ + ]; + qcom,mdss-dsi-panel-display-p3-mode-on-command = [ + 29 01 00 00 00 00 02 81 90 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 01 + 29 01 00 00 00 00 16 B1 E0 03 00 11 E2 01 0D 08 E5 1A FA FC E5 09 F6 EA F3 01 FE FF F7 + 29 01 00 00 00 00 02 B1 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command = [ + 29 01 00 00 00 00 02 81 90 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 01 + 29 01 00 00 00 00 16 B1 FF 00 00 00 FF 00 00 00 FF 00 FF FF FF 00 FF FF FF 00 FF FF FF + 29 01 00 00 00 00 02 B1 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-dci-p3-off-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 03 B1 00 01 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-customer-srgb-enable-command = [ + 29 01 00 00 00 00 02 81 90 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 01 + 29 01 00 00 00 00 16 B1 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 02 B1 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-customer-p3-enable-command = [ + 29 01 00 00 00 00 02 81 90 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 01 + 29 01 00 00 00 00 16 B1 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 02 B1 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-command = [ + 39 01 00 00 00 00 02 81 90 + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 B0 01 + 39 01 00 00 00 00 16 B1 E0 + 03 00 11 E2 01 0D 08 E5 1A + FA FC E5 09 F6 EA F3 01 FE + FF F7 + 39 01 00 00 00 00 02 B1 00 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-seed-command = [ + 39 01 00 00 00 00 02 81 90 + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 B0 01 + 39 01 00 00 00 00 16 B1 E0 03 00 11 E2 01 0D 08 E5 1A FA FC E5 09 F6 EA F3 01 FE FF F7 + 39 01 00 00 00 00 02 B1 00 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-loading-effect-enable-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 B0 01 + 39 01 00 00 00 00 06 C2 87 FF 6D C0 70 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-loading-effect-disable-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 B0 01 + 39 01 00 00 00 00 06 C2 A7 73 40 C0 30 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + + qcom,mdss-dsi-timing-switch-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-open-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-close-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-customer-p3-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-customer-srgb-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-seed-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-loading-effect-enable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-loading-effect-disable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-p3-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-night-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-dci-p3-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-new-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-samsung-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-hbm-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-off-aod-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-aod-on-command-1-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-on-command-2-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-pre-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-code-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-state-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-production-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-post-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-brightness-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-brightness-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-on-command-1-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-on-command-2-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-on-command-3-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-on-command-5-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-off-command-state = "dsi_hs_mode"; + + qcom,panel-roi-alignment=<540 30 540 30 540 30>; + qcom,compression-mode = "dsc"; + qcom,lm-split = <540 540>; + qcom,mdss-dsc-encoders = <2>; + qcom,mdss-dsc-slice-height = <30>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@1 { + qcom,display-topology = <1 1 1>, <2 2 1>; + qcom,default-topology-index = <1>; + qcom,mdss-mdp-transfer-time-us = <8000>; //for 90fps + qcom,mdss-dsi-timing-default; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-clockrate = <1100000000>; + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 25 09 0A 06 02 04 00 1E 1A]; + qcom,mdss-dsi-t-clk-pre = <0x1E>; + qcom,mdss-dsi-t-clk-post = <0x1A>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <52>; + qcom,mdss-dsi-h-back-porch = <24>; + qcom,mdss-dsi-h-pulse-width = <24>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <4>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [ + 06 01 00 00 00 00 02 0A 00 + ]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9C>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-panel-read-register-open-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + ]; + qcom,mdss-dsi-panel-id1-command = [ + 06 01 00 00 00 00 02 0A 00 + ]; + qcom,mdss-dsi-panel-id2-command = [ + 06 01 00 00 00 00 02 B6 00 + ]; + qcom,mdss-dsi-panel-read-register-close-command = [ + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + + qcom,mdss-dsi-timing-switch-command = [ + /* 60hz â†?90hz Transition */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 60 10 /* 0x10 : 90 Hz */ + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-on-command = [ + /* DSC Setting */ + 39 01 00 00 00 00 02 9D 01 /* Compression Enable */ + 39 01 00 00 00 00 81 9E /* PPS Setting */ + 11 00 00 89 30 80 09 60 + 04 38 00 1E 02 1C 02 1C + 02 00 02 0E 00 20 02 E3 + 00 07 00 0C 03 50 03 64 + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A F6 + 2B 34 2B 74 3B 74 6B F4 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + + /* Sleep Out(11h) */ + 05 01 00 00 0A 00 01 11 + + /* Common Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 35 00 /* TE Vsync On */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* PAGE ADDRESS SET */ + 39 01 00 00 00 00 05 2A 00 00 04 37 + 39 01 00 00 00 00 05 2B 00 00 09 5F + /* ELVSS Dim Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 B0 05 + 39 01 00 00 00 00 02 B7 13 + 39 01 00 00 00 00 03 F0 A5 A5 + /* Dimming Delay control */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 B0 01 + 39 01 00 00 00 00 02 B7 53 /* 0x53 : DLY ON */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* Dimming Speed Control */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 B0 06 + 39 01 00 00 00 00 02 B7 01 /* 0x01 : 1 Frames */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* TSP H_sync Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 DF 83 /* TSP H Sync ON */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* FD(Fast Discharge) Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 B0 0A + 39 01 00 00 00 00 02 D5 05 /* FD Set Normal Mode */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* ERR_FG Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 B0 02 + 39 01 00 00 00 00 05 EC 00 C2 C2 42 + 39 01 00 00 00 00 02 B0 0D + 39 01 00 00 00 00 02 EC 19 + 39 01 00 00 00 00 03 F0 A5 A5 + /* OFC Setting */ + 39 01 00 00 00 00 03 FC 5A 5A + 39 01 00 00 00 00 02 B0 01 + 39 01 00 00 00 00 04 E4 A6 C3 42 + 39 01 00 00 00 00 0F E9 11 75 A6 C3 42 96 2F 58 96 2F 58 00 32 32 + 39 01 00 00 00 00 03 FC A5 A5 + /* Brightness Control */ + 39 01 00 00 00 00 02 53 20 /* 0x20 Normal transition */ + /* 60hz â†?90hz Transition */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 60 10 /* 0x10 : 90 Hz */ + 39 01 00 00 3C 00 03 F0 A5 A5 + + /* Display On */ + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-dsi-off-command=[ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 64 00 02 10 00 + ]; + qcom,mdss-dsi-panel-hbm-brightness-on-command = [ + /* HBM Mode Setting */ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 B0 BB + 39 00 00 00 00 00 02 BA 77 + 39 00 00 00 00 00 02 B0 01 + 39 00 00 00 00 00 03 B7 57 FF + 39 00 00 00 00 00 02 B0 0A + 39 00 00 00 00 00 11 B7 00 + 01 02 03 24 45 46 47 68 09 + 6A 8B 8C 40 A1 02 + 39 00 00 00 00 00 02 B0 3C + 39 00 00 00 00 00 1B B7 41 + 65 4A 67 E7 FF 80 08 55 8A + A9 54 9F EA A8 B5 2B FC CA + 6D 50 DF AE A4 F4 E0 + 39 01 00 00 0C 00 03 F0 A5 A5 + /* HBM Mode ON */ + 39 01 00 00 00 00 02 53 E0 + ]; + qcom,mdss-dsi-panel-hbm-brightness-off-command = [ + /* HBM Mode OFF */ + 39 00 00 00 00 00 02 53 20 + 39 01 00 00 0C 00 03 51 03 FF + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 B0 BB + 39 00 00 00 00 00 02 BA F7 + 39 00 00 00 00 00 02 B0 01 + 39 00 00 00 00 00 03 B7 52 A8 + 39 00 00 00 00 00 02 B0 0A + 39 00 00 00 00 00 11 B7 00 + 00 00 00 21 41 41 41 62 02 + 62 82 83 43 A3 03 + 39 00 00 00 00 00 02 B0 3C + 39 00 00 00 00 00 1B B7 2E + 23 2F 37 C3 C9 41 64 63 4B + 04 FD 54 A5 97 5E 46 31 67 + E6 CB 71 87 65 7B 20 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-hbm-on-command-1 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-2 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-3 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-4 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-5 = [ + /* ELVSS Dim Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 B0 05 + 39 01 00 00 00 00 02 B7 13 /* 0x13 : ELVSS DIM OFF */ + 39 01 00 00 03 00 03 F0 A5 A5 + /* Dimming Delay control */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 B0 01 + 39 01 00 00 00 00 02 B7 5B /* 0x5B : DLY OFF */ + 39 01 00 00 0C 00 03 F0 A5 A5 + /* HBM Mode ON */ + 39 01 00 00 00 00 02 53 E0 /* 0xE0 Normal transition */ + 39 01 00 00 0C 00 03 51 01 84 /* 670nit */ + /* Dimming Delay control */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 B0 01 + 39 01 00 00 00 00 02 B7 53 /* 0x53 : DLY ON */ + 39 01 00 00 09 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-hbm-off-command = [ + /* HBM Mode OFF */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 53 20 /* 0x20 Normal transition */ + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-serial-num-pre-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + 37 01 00 00 05 00 02 10 00 + ]; + qcom,mdss-dsi-panel-serial-num-command = [ + 06 01 00 00 00 00 01 A1 00 + ]; + qcom,mdss-dsi-panel-code-info-command = [ + 06 01 00 00 00 00 01 DA 00 + ]; + qcom,mdss-dsi-panel-stage-info-command = [ + 06 01 00 00 00 00 01 DB 00 + ]; + qcom,mdss-dsi-panel-production-info-command = [ + 06 01 00 00 00 00 01 DC 00 + ]; + qcom,mdss-dsi-panel-serial-num-post-command = [ + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-aod-on-command-1 = [ + ]; + qcom,mdss-dsi-panel-aod-on-command-2 = [ + ]; + qcom,mdss-dsi-panel-aod-off-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-samsung-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-new-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-hbm-on-command = [ + /* ELVSS Dim Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 B0 05 + 39 01 00 00 00 00 02 B7 13 /* 0x13 : ELVSS DIM OFF */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* Dimming Delay control */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 B0 01 + 39 01 00 00 00 00 02 B7 5B /* 0x5B : DLY OFF */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* HBM Mode ON */ + 39 01 00 00 00 00 02 53 E0 /* 0xE0 Normal transition */ + 39 01 00 00 00 00 03 51 01 84 /* 670nit */ + /* Dimming Delay control */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 B0 01 + 39 01 00 00 00 00 02 B7 53 /* 0x53 : DLY ON */ + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-hbm-off-aod-on-command = [ + /* HBM Mode OFF */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 53 20 /* 0x20 Normal transition */ + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command = [ + 29 01 00 00 00 00 02 81 90 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 01 + 29 01 00 00 00 00 16 B1 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 02 B1 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-night-mode-on-command = [ + ]; + qcom,mdss-dsi-panel-display-p3-mode-on-command = [ + 29 01 00 00 00 00 02 81 90 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 01 + 29 01 00 00 00 00 16 B1 E0 03 00 11 E2 01 0D 08 E5 1A FA FC E5 09 F6 EA F3 01 FE FF F7 + 29 01 00 00 00 00 02 B1 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command = [ + 29 01 00 00 00 00 02 81 90 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 01 + 29 01 00 00 00 00 16 B1 FF 00 00 00 FF 00 00 00 FF 00 FF FF FF 00 FF FF FF 00 FF FF FF + 29 01 00 00 00 00 02 B1 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-dci-p3-off-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 03 B1 00 01 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-customer-srgb-enable-command = [ + 29 01 00 00 00 00 02 81 90 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 01 + 29 01 00 00 00 00 16 B1 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 02 B1 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-customer-p3-enable-command = [ + 29 01 00 00 00 00 02 81 90 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 01 + 29 01 00 00 00 00 16 B1 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 02 B1 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-command = [ + 39 01 00 00 00 00 02 81 90 + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 B0 01 + 39 01 00 00 00 00 16 B1 E0 + 03 00 11 E2 01 0D 08 E5 1A + FA FC E5 09 F6 EA F3 01 FE + FF F7 + 39 01 00 00 00 00 02 B1 00 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-seed-command = [ + 39 01 00 00 00 00 02 81 90 + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 B0 01 + 39 01 00 00 00 00 16 B1 E0 03 00 11 E2 01 0D 08 E5 1A FA FC E5 09 F6 EA F3 01 FE FF F7 + 39 01 00 00 00 00 02 B1 00 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-loading-effect-enable-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 B0 01 + 39 01 00 00 00 00 06 C2 87 FF 6D C0 70 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-loading-effect-disable-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 B0 01 + 39 01 00 00 00 00 06 C2 A7 73 40 C0 30 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + + qcom,mdss-dsi-timing-switch-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-open-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-close-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-customer-p3-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-customer-srgb-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-seed-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-loading-effect-enable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-loading-effect-disable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-p3-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-night-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-dci-p3-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-new-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-samsung-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-hbm-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-off-aod-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-aod-on-command-1-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-on-command-2-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-pre-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-code-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-state-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-production-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-post-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-brightness-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-brightness-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-on-command-1-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-on-command-2-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-on-command-3-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-on-command-4-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-on-command-5-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-off-command-state = "dsi_hs_mode"; + + qcom,panel-roi-alignment=<540 30 540 30 540 30>; + qcom,compression-mode = "dsc"; + qcom,lm-split = <540 540>; + qcom,mdss-dsc-encoders = <2>; + qcom,mdss-dsc-slice-height = <30>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; + +&dsi_samsung_sofef03f_m_fhd_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; + qcom,platform-poc-gpio = <&tlmm 130 0>; + qcom,tp1v8-gpio = <&tlmm 119 0>; + qcom,vddd-gpio = <&tlmm 120 0>; + qcom,err-flag-gpio = <&tlmm 114 0>; +}; + +&soc { + dsi_samsung_sofef03f_m_fhd_dsc_cmd_display { + qcom,dsi-display-active; + }; +}; + +&dsi_samsung_sofef03f_m_fhd_dsc_cmd { + qcom,mdss-dsi-display-timings { + timing@0 { /* fhd 60hz */ + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 25 09 0A 06 02 04 00 1E 1A]; + qcom,display-topology = <1 1 1>,<2 2 1>; + qcom,default-topology-index = <1>; + qcom,panel-roi-alignment=<540 30 540 30 540 30>; + }; + timing@1 { /* fhd 90hz */ + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 25 09 0A 06 02 04 00 1E 1A]; + qcom,display-topology = <1 1 1>,<2 2 1>; + qcom,default-topology-index = <1>; + qcom,panel-roi-alignment=<540 30 540 30 540 30>; + }; + }; +}; + + diff --git a/arch/arm64/boot/dts/qcom/guacamole-overlay-dvt.dts b/arch/arm64/boot/dts/qcom/guacamole-overlay-dvt.dts new file mode 100644 index 0000000000000000000000000000000000000000..e273cc611f3f47474508b6b03e82996c89ea217e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole-overlay-dvt.dts @@ -0,0 +1,43 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sm8150.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_evt1.dtsi" +#include "guacamole_evt2.dtsi" +#include "guacamole_evt3.dtsi" +#include "guacamole_dvt.dtsi" + +/ { + model = "MTP 18821 18831 15"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0 >; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18821 18831>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <15>; +}; + diff --git a/arch/arm64/boot/dts/qcom/guacamole-overlay-evt1.dts b/arch/arm64/boot/dts/qcom/guacamole-overlay-evt1.dts new file mode 100644 index 0000000000000000000000000000000000000000..68749dd8d7956f6dfa2f6508e82e15fb2d3588bc --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole-overlay-evt1.dts @@ -0,0 +1,39 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sm8150.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_evt1.dtsi" +/ { + model = "MTP 18821 18831 12"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18821 18831>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <12>; +}; + diff --git a/arch/arm64/boot/dts/qcom/guacamole-overlay-evt2-second.dts b/arch/arm64/boot/dts/qcom/guacamole-overlay-evt2-second.dts new file mode 100644 index 0000000000000000000000000000000000000000..64fc4a52eb2543835f9144366b363e36e7c205fa --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole-overlay-evt2-second.dts @@ -0,0 +1,40 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sm8150.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_evt1.dtsi" +#include "guacamole_evt2.dtsi" +/ { + model = "MTP 18821 18831 second 55"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18821 18831>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <55>; +}; + diff --git a/arch/arm64/boot/dts/qcom/guacamole-overlay-evt2.dts b/arch/arm64/boot/dts/qcom/guacamole-overlay-evt2.dts new file mode 100644 index 0000000000000000000000000000000000000000..d75754eb4b0f771d1b4af104c7832506065e15f5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole-overlay-evt2.dts @@ -0,0 +1,40 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sm8150.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_evt1.dtsi" +#include "guacamole_evt2.dtsi" +/ { + model = "MTP 18821 18831 13 54 evt2"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18821 18831>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <13 54>; +}; + diff --git a/arch/arm64/boot/dts/qcom/guacamole-overlay-evt3.dts b/arch/arm64/boot/dts/qcom/guacamole-overlay-evt3.dts new file mode 100644 index 0000000000000000000000000000000000000000..070ed1c5453c17fe8c3646109a982765dfe9a756 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole-overlay-evt3.dts @@ -0,0 +1,41 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sm8150.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_evt1.dtsi" +#include "guacamole_evt2.dtsi" +#include "guacamole_evt3.dtsi" +/ { + model = "MTP 18821 18831 14 52 53"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18821 18831>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <14 52 53>; +}; + diff --git a/arch/arm64/boot/dts/qcom/guacamole-overlay-pvt.dts b/arch/arm64/boot/dts/qcom/guacamole-overlay-pvt.dts new file mode 100644 index 0000000000000000000000000000000000000000..1a3299e5dfed8706b05294b4037a4e1751cc8734 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole-overlay-pvt.dts @@ -0,0 +1,44 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sm8150.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_evt1.dtsi" +#include "guacamole_evt2.dtsi" +#include "guacamole_evt3.dtsi" +#include "guacamole_dvt.dtsi" +#include "guacamole_pvt.dtsi" + +/ { + model = "MTP 18821 18831 21 22"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0 >; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18821 18831>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <21 22>; +}; + diff --git a/arch/arm64/boot/dts/qcom/guacamole-overlay-t0.dts b/arch/arm64/boot/dts/qcom/guacamole-overlay-t0.dts new file mode 100644 index 0000000000000000000000000000000000000000..ef389e47a2751975099ae13ccb2800e0d140699c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole-overlay-t0.dts @@ -0,0 +1,39 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sm8150.dtsi" +#include "guacamole_t0.dtsi" + +/ { + model = "MTP 18821 18831 T0 11"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18821 18831>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <11>; +}; + diff --git a/arch/arm64/boot/dts/qcom/guacamole-sdx50m-overlay-dvt.dts b/arch/arm64/boot/dts/qcom/guacamole-sdx50m-overlay-dvt.dts new file mode 100644 index 0000000000000000000000000000000000000000..1f8a448555d7387c14cc251c48c6e53c5b835219 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole-sdx50m-overlay-dvt.dts @@ -0,0 +1,46 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdx50m.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sdx50m.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_evt1.dtsi" +#include "guacamole_evt2.dtsi" +#include "guacamole_dvt.dtsi" + + +/ { + model = "SDX50M MTP 18827 15"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <0x01010008 0x1>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18827>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <15>; + +}; diff --git a/arch/arm64/boot/dts/qcom/guacamole-sdx50m-overlay-evt1.dts b/arch/arm64/boot/dts/qcom/guacamole-sdx50m-overlay-evt1.dts new file mode 100644 index 0000000000000000000000000000000000000000..5826102194b86164c54ab6ef0b7a552fb36af630 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole-sdx50m-overlay-evt1.dts @@ -0,0 +1,44 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdx50m.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sdx50m.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_evt1.dtsi" + + +/ { + model = "SDX50M MTP 18827 12 13"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <0x01010008 0x1>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18827>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <12 13>; + +}; diff --git a/arch/arm64/boot/dts/qcom/guacamole-sdx50m-overlay-evt2.dts b/arch/arm64/boot/dts/qcom/guacamole-sdx50m-overlay-evt2.dts new file mode 100644 index 0000000000000000000000000000000000000000..df0d8368088284df40a790da55dd816b8049ea12 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole-sdx50m-overlay-evt2.dts @@ -0,0 +1,45 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdx50m.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sdx50m.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_evt1.dtsi" +#include "guacamole_evt2.dtsi" + + +/ { + model = "SDX50M MTP 18827 14"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <0x01010008 0x1>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18827>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <14>; + +}; diff --git a/arch/arm64/boot/dts/qcom/guacamole-sdx50m-overlay-pvt.dts b/arch/arm64/boot/dts/qcom/guacamole-sdx50m-overlay-pvt.dts new file mode 100644 index 0000000000000000000000000000000000000000..440fa057b30e7f9d426bc7d0f48a0ccd48647688 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole-sdx50m-overlay-pvt.dts @@ -0,0 +1,47 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdx50m.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sdx50m.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_evt1.dtsi" +#include "guacamole_evt2.dtsi" +#include "guacamole_dvt.dtsi" +#include "guacamole_pvt.dtsi" + + +/ { + model = "SDX50M MTP 18827 21 22"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <0x01010008 0x1>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18827>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <21 22>; + +}; diff --git a/arch/arm64/boot/dts/qcom/guacamole-sdx50m-overlay-t0.dts b/arch/arm64/boot/dts/qcom/guacamole-sdx50m-overlay-t0.dts new file mode 100644 index 0000000000000000000000000000000000000000..31c592f7d9a4b958dc1cfc697e5af77a8ce43367 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole-sdx50m-overlay-t0.dts @@ -0,0 +1,43 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdx50m.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sdx50m.dtsi" +#include "guacamole_t0.dtsi" + + +/ { + model = "SDX50M MTP 18827 11"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <0x01010008 0x1>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18827>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <11>; + +}; diff --git a/arch/arm64/boot/dts/qcom/guacamole.dtsi b/arch/arm64/boot/dts/qcom/guacamole.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..18151a2d7ffb7e14bb7cfc6629b4e379986ded06 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole.dtsi @@ -0,0 +1,166 @@ +/*this is for different project dtsi*/ +/* OnePlus add thermistor, by rio.zhao*/ + +&thermal_zones { + skin-therm { + polling-delay-passive = <2000>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM1_PU2>; + trips { + freq_config1: freq_config1 { + temperature = <52000>; + hysteresis = <2000>; + type = "passive"; + }; + freq_config2: freq_config2 { + temperature = <54000>; + hysteresis = <2000>; + type = "passive"; + }; + }; + cooling-maps { + freq_dev0 { + trip = <&freq_config1>; + cooling-device = + <&msm_gpu THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-1)>;/*345*/ + }; + freq_dev1 { + trip = <&freq_config1>; + cooling-device = + <&CPU0 9 9>;/*1036*/ + }; + freq_dev2 { + trip = <&freq_config1>; + cooling-device = + <&CPU4 13 13>;/*1056*/ + }; + freq_dev3 { + trip = <&freq_config1>; + cooling-device = + <&CPU7 16 16>;/*1171*/ + }; + freq_dev4 { + trip = <&freq_config2>; + cooling-device = + <&CPU0 11 11>;/*844*/ + }; + freq_dev5 { + trip = <&freq_config2>; + cooling-device = + <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + freq_dev6 { + trip = <&freq_config2>; + cooling-device = + <&CPU5 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + freq_dev7 { + trip = <&freq_config2>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + freq_dev8 { + trip = <&freq_config2>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pa-therm1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM2_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + skin-msm-therm { + trips { + freq_config3: freq_config3 { + temperature = <62000>; + hysteresis = <2000>; + type = "passive"; + }; + freq_config4: freq_config4 { + temperature = <64000>; + hysteresis = <2000>; + type = "passive"; + }; + freq_config5: freq_config5 { + temperature = <66000>; + hysteresis = <2000>; + type = "passive"; + }; + }; + cooling-maps { + freq_dev0 { + trip = <&freq_config3>; + cooling-device = + <&CPU0 2 2>;/*1632 18*/ + }; + freq_dev1 { + trip = <&freq_config3>; + cooling-device = + <&CPU4 8 8>;/*1612 17*/ + }; + freq_dev2 { + trip = <&freq_config3>; + cooling-device = + <&CPU7 9 9>;/*1920 20*/ + }; + freq_dev3 { + trip = <&freq_config4>; + cooling-device = + <&CPU0 4 4>;/*1478*/ + }; + freq_dev4 { + trip = <&freq_config4>; + cooling-device = + <&CPU4 11 11>;/*1286*/ + }; + freq_dev5 { + trip = <&freq_config4>; + cooling-device = + <&CPU7 13 13>;/*1497*/ + }; + freq_dev6 { + trip = <&freq_config4>; + cooling-device = + <&msm_gpu THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-3)>;/*499*/ + }; + freq_dev7 { + trip = <&freq_config5>; + cooling-device = + <&msm_gpu THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-2)>;/*427*/ + }; + }; + }; +}; +&pm8150b_charger { + /* for verify test adjust 530->500 */ + hot-bat-decidegc = <500>; + op,dis_ctrl_current; +}; + +&mtp_batterydata { + #include "OP-fg-batterydata-4000mah.dtsi" +}; + +&wdog{ + qcom,bark-time = <15000>; +}; diff --git a/arch/arm64/boot/dts/qcom/guacamole_dvt.dtsi b/arch/arm64/boot/dts/qcom/guacamole_dvt.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..18b79ae52abaee1b2905554c37a4abb1f2b35a21 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole_dvt.dtsi @@ -0,0 +1 @@ +/*this is for one project different hw version */ \ No newline at end of file diff --git a/arch/arm64/boot/dts/qcom/guacamole_evt1.dtsi b/arch/arm64/boot/dts/qcom/guacamole_evt1.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..8f699bb7f92226a6738f092d41e20a7f5bec7f1e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole_evt1.dtsi @@ -0,0 +1,2 @@ +/*this is for one project different hw version */ + diff --git a/arch/arm64/boot/dts/qcom/guacamole_evt2.dtsi b/arch/arm64/boot/dts/qcom/guacamole_evt2.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..8f699bb7f92226a6738f092d41e20a7f5bec7f1e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole_evt2.dtsi @@ -0,0 +1,2 @@ +/*this is for one project different hw version */ + diff --git a/arch/arm64/boot/dts/qcom/guacamole_evt3.dtsi b/arch/arm64/boot/dts/qcom/guacamole_evt3.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..8f699bb7f92226a6738f092d41e20a7f5bec7f1e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole_evt3.dtsi @@ -0,0 +1,2 @@ +/*this is for one project different hw version */ + diff --git a/arch/arm64/boot/dts/qcom/guacamole_pvt.dtsi b/arch/arm64/boot/dts/qcom/guacamole_pvt.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..18b79ae52abaee1b2905554c37a4abb1f2b35a21 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole_pvt.dtsi @@ -0,0 +1 @@ +/*this is for one project different hw version */ \ No newline at end of file diff --git a/arch/arm64/boot/dts/qcom/guacamole_sdx50m.dtsi b/arch/arm64/boot/dts/qcom/guacamole_sdx50m.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..78884d9ed1617cac0faaa08c6af44ce90bd01359 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole_sdx50m.dtsi @@ -0,0 +1,17 @@ +/*this is for sdx50m project */ +&ois_rear_0 { +ois_gyro,id = <2>;//18827 +}; +&ois_rear_1 { +ois_gyro,id = <2>;//18827 +}; + +&soc { + qcom,msm-imem@146bf000 { + download_mode@0{ + compatible = "qcom,msm-imem-download_mode"; + reg = <0x658 4>; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/qcom/guacamole_sm8150.dtsi b/arch/arm64/boot/dts/qcom/guacamole_sm8150.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..a9e5ae4e8b229b5128a8f9628d11e957421ca6c1 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole_sm8150.dtsi @@ -0,0 +1,8 @@ +/*this is for sm8150 version */ + +&ois_rear_0 { + ois_gyro,id = <1>;//18821 +}; +&ois_rear_1 { + ois_gyro,id = <1>;//18821 +}; diff --git a/arch/arm64/boot/dts/qcom/guacamole_t0.dtsi b/arch/arm64/boot/dts/qcom/guacamole_t0.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..cba91f6891463853b0e0af58ffad1fdf07d53e22 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole_t0.dtsi @@ -0,0 +1,99 @@ +/*this is for one project different hw version */ + +/*tp 1.8v power change to gpio119 for T0 hw*/ +&qupv3_se17_i2c { + sec-s6sy761@48 { + //enable1v8_gpio = <&tlmm 119 0x00>; + pinctrl-0 = <&tp_irq_active &tp_rst_active &tp_1v8_t0_active>; + pinctrl-1 = <&tp_rst_suspend &tp_1v8_t0_suspend>; + }; +}; + +&qupv3_se17_i2c { + st_fts@49 { + //enable1v8_gpio = <&tlmm 119 0x00>; + pinctrl-0 = <&tp_irq_active &tp_rst_active &tp_1v8_t0_active>; + pinctrl-1 = <&tp_rst_suspend &tp_1v8_t0_suspend>; + }; +}; + +&tlmm { + + + tp_1v8_t0_active: tp_1v8_t0_active { + mux { + pins = "gpio119"; + function = "gpio"; + }; + config { + pins = "gpio119"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + tp_1v8_t0_suspend: tp_1v8_t0_suspend { + mux { + pins = "gpio119"; + function = "gpio"; + }; + config { + pins = "gpio119"; + drive-strength = <8>; + bias-pull-down; + }; + }; +}; + +/* for Battery & Charging STRAT */ +&qupv3_se8_i2c { + oneplus_fastchg@26{ + microchip,mcu-en-gpio = <&tlmm 10 0x00>; + microchip,usb-sw-2-gpio = <&tlmm 59 0x00>; + op,mcl_verion; + }; + +}; + +&pm8150b_charger { + /* for external ship mode suppot */ + op,stm-ctrl-gpio = <&tlmm 21 0x00>; + op,vbus-ctrl-gpio = <&pm8150_gpios 9 GPIO_ACTIVE_LOW>; +}; + +/* for Battery & Charging END */ + +/* @bsp, usb config START*/ +&usb2_phy0 { + qcom,param-override-seq = + <0x67 0x6c/*Disconnection voltage +21.56%*/ + 0x06 0x70/*Pre-emphasis:4x DC voltage level:+6.50%*/ + 0x28 0x74>; +}; + +&extcon_usb1 { + status = "disabled"; +}; + +&usb1 { + status = "disabled"; +}; + +/* @bsp, As QRD-DVT have this config, keep the same config + * for ldo18 power suspend + */ +&usb_qmp_dp_phy { + vdd-supply = <&pm8150_l18>; + qcom,vdd-voltage-level = <0 912000 912000>; +}; + +&sde_dp { + vdda-0p9-supply = <&pm8150_l18>; + qcom,phy-supply-entries { + qcom,phy-supply-entry@0 { + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <912000>; + }; + }; +}; +/* @bsp, usb config END*/ diff --git a/arch/arm64/boot/dts/qcom/guacamoleb-overlay-dvt.dts b/arch/arm64/boot/dts/qcom/guacamoleb-overlay-dvt.dts new file mode 100644 index 0000000000000000000000000000000000000000..8db1e3b3e02016ec569e057415ffa03b917096c3 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamoleb-overlay-dvt.dts @@ -0,0 +1,39 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-guacamoleb.dtsi" +#include "guacamoleb_sm8150.dtsi" +#include "guacamoleb.dtsi" +#include "guacamoleb_dvt.dtsi" + +/ { + model = "MTP 18857 13"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0 >; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18857 >; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <13>; +}; + diff --git a/arch/arm64/boot/dts/qcom/guacamoleb-overlay-evt.dts b/arch/arm64/boot/dts/qcom/guacamoleb-overlay-evt.dts new file mode 100644 index 0000000000000000000000000000000000000000..cbc81cc94b9bdb733948cd660072983fecde33dd --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamoleb-overlay-evt.dts @@ -0,0 +1,39 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-guacamoleb.dtsi" +#include "guacamoleb_sm8150.dtsi" +#include "guacamoleb.dtsi" +#include "guacamoleb_evt.dtsi" + +/ { + model = "MTP 18857 12 "; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18857>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <12>; +}; + diff --git a/arch/arm64/boot/dts/qcom/guacamoleb-overlay-pvt.dts b/arch/arm64/boot/dts/qcom/guacamoleb-overlay-pvt.dts new file mode 100644 index 0000000000000000000000000000000000000000..0914cf131d2f6c5177c34c8e7112dc04c7ea4253 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamoleb-overlay-pvt.dts @@ -0,0 +1,39 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-guacamoleb.dtsi" +#include "guacamoleb_sm8150.dtsi" +#include "guacamoleb.dtsi" +#include "guacamoleb_pvt.dtsi" + +/ { + model = "MTP 18857 14 15"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0 >; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18857>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <14 15>; +}; + diff --git a/arch/arm64/boot/dts/qcom/guacamoleb-overlay-t0.dts b/arch/arm64/boot/dts/qcom/guacamoleb-overlay-t0.dts new file mode 100644 index 0000000000000000000000000000000000000000..694df9a2a39bd171f25a8944ab45ecc5363d10ee --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamoleb-overlay-t0.dts @@ -0,0 +1,39 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-guacamoleb.dtsi" +#include "guacamoleb_sm8150.dtsi" +#include "guacamoleb.dtsi" +#include "guacamoleb_t0.dtsi" + +/ { + model = "MTP 18857 T0 11"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18857>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <11>; +}; + diff --git a/arch/arm64/boot/dts/qcom/guacamoleb.dtsi b/arch/arm64/boot/dts/qcom/guacamoleb.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..2685b9ccd4a4db197d4d6117575df14bdf59fc7e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamoleb.dtsi @@ -0,0 +1,490 @@ +/*this is for different project dtsi*/ +/* OnePlus add thermistor, by rio.zhao*/ +&pm8150_adc_tm { + skin_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm1 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&thermal_zones { + skin-therm { + polling-delay-passive = <2000>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM1_PU2>; + trips { + freq_config1: freq_config1 { + temperature = <52000>; + hysteresis = <2000>; + type = "passive"; + }; + freq_config2: freq_config2 { + temperature = <54000>; + hysteresis = <2000>; + type = "passive"; + }; + }; + cooling-maps { + freq_dev0 { + trip = <&freq_config1>; + cooling-device = + <&msm_gpu THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-1)>;/*345*/ + }; + freq_dev1 { + trip = <&freq_config1>; + cooling-device = + <&CPU0 9 9>;/*1036*/ + }; + freq_dev2 { + trip = <&freq_config1>; + cooling-device = + <&CPU4 13 13>;/*1056*/ + }; + freq_dev3 { + trip = <&freq_config1>; + cooling-device = + <&CPU7 16 16>;/*1171*/ + }; + freq_dev4 { + trip = <&freq_config2>; + cooling-device = + <&CPU0 11 11>;/*844*/ + }; + freq_dev5 { + trip = <&freq_config2>; + cooling-device = + <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + freq_dev6 { + trip = <&freq_config2>; + cooling-device = + <&CPU5 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + freq_dev7 { + trip = <&freq_config2>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + freq_dev8 { + trip = <&freq_config2>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pa-therm1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM2_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + skin-msm-therm { + trips { + freq_config3: freq_config3 { + temperature = <63000>; + hysteresis = <2000>; + type = "passive"; + }; + freq_config4: freq_config4 { + temperature = <65000>; + hysteresis = <2000>; + type = "passive"; + }; + }; + cooling-maps { + freq_dev0 { + trip = <&freq_config3>; + cooling-device = + <&CPU0 2 2>;/*1632 18*/ + }; + freq_dev1 { + trip = <&freq_config3>; + cooling-device = + <&CPU4 8 8>;/*1612 17*/ + }; + freq_dev2 { + trip = <&freq_config3>; + cooling-device = + <&CPU7 9 9>;/*1920 20*/ + }; + freq_dev3 { + trip = <&freq_config4>; + cooling-device = + <&CPU0 4 4>;/*1478*/ + }; + freq_dev4 { + trip = <&freq_config4>; + cooling-device = + <&CPU4 11 11>;/*1286*/ + }; + freq_dev5 { + trip = <&freq_config4>; + cooling-device = + <&CPU7 13 13>;/*1497*/ + }; + freq_dev6 { + trip = <&freq_config3>; + cooling-device = + <&msm_gpu THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-3)>;/*499*/ + }; + freq_dev7 { + trip = <&freq_config4>; + cooling-device = + <&msm_gpu THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-2)>;/*427*/ + }; + }; + }; +}; + +/*tp 1.8v power change to gpio119 for T0 hw*/ +&qupv3_se17_i2c { + sec-s6sy761@48 { + status = "disable"; + // enable1v8_gpio = <&tlmm 119 0x00>; + pinctrl-0 = <&tp_irq_active &tp_rst_active &tp_1v8_t0_active>; + pinctrl-1 = <&tp_rst_suspend &tp_1v8_t0_suspend>; + }; +}; +&qupv3_se17_i2c { + st_fts@49{ + status = "disable"; + }; +}; +&qupv3_se17_i2c { + synaptics-s3706@20 { + //enable1v8_gpio = <&tlmm 119 0x00>; + project-name = "18857"; + reset-gpio = <&tlmm 54 0x00>; + touchpanel,display-coords = <1079 2339>; + touchpanel,panel-coords = <1079 2339>; + touchpanel,tx-rx-num = <16 33>; + pinctrl-0 = <&tp_irq_active &tp_1v8_t0_active &tp_rst_active>; + pinctrl-1 = <&tp_rst_suspend &tp_1v8_t0_suspend>; + }; + /delete-node/ sec-s6sy761@48; + /delete-node/ st_fts@49; +}; + +&tp_rst_active{ + mux { + pins = "gpio54"; + function = "gpio"; + }; + config { + pins = "gpio54"; + drive-strength = <8>; + bias-pull-up; + }; + +}; +&tlmm { + tp_1v8_t0_active: tp_1v8_t0_active { + mux { + pins = "gpio119"; + function = "gpio"; + }; + config { + pins = "gpio119"; + drive-strength = <8>; + bias-pull-up; + }; + }; + tp_1v8_t0_suspend: tp_1v8_t0_suspend { + mux { + pins = "gpio119"; + function = "gpio"; + }; + config { + pins = "gpio119"; + drive-strength = <8>; + bias-pull-down; + }; + }; +}; + +/* add for hall tri_state_key */ + +&tri_state_key { + compatible = "oneplus,hall_tri_state_key"; + status = "ok"; + interrupt-parent = <&tlmm>; +}; + +&qupv3_se9_i2c { + //qcom,clk-freq-out = <300000>; + status = "ok"; + magnachip@0D { + compatible = "tri_key_magnachip,tk_mxm1120,up"; + reg = <0x0D>; + vdd-supply = <&pm8150l_l7>; + magnachip,init-interval = <200>; + interrupt-parent = <&tlmm>; + interrupts = <26 0x02>; + dhall,irq-gpio = <&tlmm 26 0x2008>; + mxm,id = <1>; + pinctrl-names = "uphall_tri_state_key_active"; + pinctrl-0 = <&uphall_tri_state_key_active>; + }; + magnachip@0C { + compatible = "tri_key_magnachip,tk_mxm1120,down"; + reg = <0x0C>; + vdd-supply = <&pm8150l_l7>; + magnachip,init-interval = <200>; + interrupt-parent = <&tlmm>; + interrupts = <27 0x02>; + dhall,irq-gpio = <&tlmm 27 0x2008>; + mxm,id = <2>; + pinctrl-names = "downhall_tri_state_key_active"; + pinctrl-0 = <&downhall_tri_state_key_active>; + }; +}; + +&tlmm { + uphall_tri_state_key_active: uphall_tri_state_key_active { + mux { + pins = "gpio26"; + function = "gpio"; + }; + config { + pins = "gpio26"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + downhall_tri_state_key_active: downhall_tri_state_key_active { + mux { + pins = "gpio27"; + function = "gpio"; + }; + config { + pins = "gpio27"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + +/* for Battery & Charging STRAT */ +&qupv3_se8_i2c { + oneplus_fastchg@26{ + microchip,mcu-en-gpio = <&tlmm 10 0x00>; + microchip,usb-sw-2-gpio = <&tlmm 59 0x00>; + }; +}; + +&pm8150b_charger { + /* for external ship mode support */ + op,stm-ctrl-gpio = <&tlmm 21 0x00>; + op,vbus-ctrl-gpio = <&pm8150_gpios 9 GPIO_ACTIVE_LOW>; + /* ibatmax setting for different temp regions */ + op,dis_ctrl_current; + ibatmax-little-cold-ma = <320>; + ibatmax-little-cool-thr-ma = <1750>; + ibatmax-cool-thr-ma = <1000>; + ibatmax-cool-ma = <1450>; + ibatmax-warm-ma = <1050>; + op,little_cold_term_current = <250>; + vph-sel-disable; +}; + +&mtp_batterydata { + #include "OP-fg-batterydata-3700mah.dtsi" +}; +/* for Battery & Charging END */ + +/* @bsp, USB oem config START*/ +&usb2_phy0 { + qcom,param-override-seq = + <0x67 0x6c/*Disconnection voltage +21.56%*/ + 0x09 0x70/*Pre-emphasis:4x DC voltage level:+13.30%*/ + 0x28 0x74>; +}; + +&extcon_usb1 { + status = "disabled"; +}; + +&usb1 { + status = "disabled"; +}; +/* @bsp, USB oem config END*/ + +&qupv3_se1_i2c { + magnachip@0C { + status = "disabled"; + }; + + magnachip@0D { + status = "disabled"; + }; +}; + +&vendor { + step_motor { + status = "disabled"; + }; +}; + +&motor_pl { + status = "disabled"; +}; + +&infrared_pl { + interrupt-parent = <&tlmm>; + interrupts = <163 0x2>; + infrared,irq-gpio = <&tlmm 163 0x2008>; + pinctrl-names = "infrared_input"; + pinctrl-0 = <&free_fall_input>; +}; + +&tlmm { + infrared_input: infrared_input { + mux { + pins = "gpio163"; + function = "gpio"; + }; + config { + pins = "gpio163"; + drive-strength = <2>; + input-enable; + bias-disable; //No Pull + }; + }; + +}; + + + + +&oem_rf_cable { + rf,cable-gpio-1 = <&pm8150_gpios 4 0>; + pinctrl-0 = <&rf_cable_ant0_active &rf_pm8150_cable_ant1>; +}; + +&oem_aboard_check { + /delete-property/ oem,aboard-gpio-1; + pinctrl-0 = <&ab_id1_default>; +}; + +&pm8150_gpios { + rf_pm8150_cable_ant1: rf_pm8150_cable_ant1 { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + bias-pull-up; + input-enable; + }; +}; +&pm8150b_gpios { + haptics_boost { + haptics_boost_default: haptics_boost_default { + pins = "gpio5"; + function = "normal"; + output-enable; + input-disable; + bias-disable; + qcom,drive-strength = <3>; /* high */ + power-source = <0>; /* VPH_PWR */ + }; + }; +}; +/* OnePlus add haptic, by yangfb*/ +&aw8697_haptic { + status = "disabled"; +}; + +&vendor { + step_motor { + status = "disabled"; + }; +}; + +&pm8150b_gpios { + haptics_boost { + haptics_boost_default: haptics_boost_default { + pins = "gpio5"; + function = "normal"; + output-enable; + input-disable; + bias-disable; + qcom,drive-strength = <3>; /* high */ + power-source = <0>; /* VPH_PWR */ + }; + }; +}; + +&vendor { + haptics_boost_vreg: haptics_boost_vreg { + compatible = "regulator-fixed"; + regulator-name = "haptics_boost"; + gpio = <&pm8150b_gpios 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-enable-ramp-delay = <300>; + pinctrl-names = "default"; + pinctrl-0 = <&haptics_boost_default>; + status = "ok"; + }; +}; +&pm8150b_haptics { + status = "ok"; + vdd-supply = <&haptics_boost_vreg>; + wf_5 { + qcom,wf-brake-pattern = [03 03 03 03]; + }; + wf_6 { + /* WEAK */ + qcom,effect-id = <6>; + qcom,wf-vmax-mv = <2500>; + qcom,wf-pattern = [7e 7e 7e fe fe]; + qcom,wf-play-rate-us = <6667>; + qcom,wf-brake-pattern = [00 00 00 00]; + qcom,lra-auto-resonance-disable; + }; + wf_7 { + /* MIDDLE */ + qcom,effect-id = <7>; + qcom,wf-vmax-mv = <2500>; + qcom,wf-pattern = [7e 7e 7e 7e fe fe fe]; + qcom,wf-play-rate-us = <6667>; + qcom,wf-brake-pattern = [00 00 00 00]; + qcom,lra-auto-resonance-disable; + }; + wf_8 { + /* STRONG */ + qcom,effect-id = <8>; + qcom,wf-vmax-mv = <2500>; + qcom,wf-pattern = [7e 7e 7e 7e 7e fe fe fe]; + qcom,wf-play-rate-us = <6667>; + qcom,wf-brake-pattern = [00 00 00 00]; + qcom,lra-auto-resonance-disable; + }; +}; + +&wdog{ + qcom,bark-time = <15000>; +}; diff --git a/arch/arm64/boot/dts/qcom/guacamoleb_dvt.dtsi b/arch/arm64/boot/dts/qcom/guacamoleb_dvt.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..18b79ae52abaee1b2905554c37a4abb1f2b35a21 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamoleb_dvt.dtsi @@ -0,0 +1 @@ +/*this is for one project different hw version */ \ No newline at end of file diff --git a/arch/arm64/boot/dts/qcom/guacamoleb_evt.dtsi b/arch/arm64/boot/dts/qcom/guacamoleb_evt.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..18b79ae52abaee1b2905554c37a4abb1f2b35a21 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamoleb_evt.dtsi @@ -0,0 +1 @@ +/*this is for one project different hw version */ \ No newline at end of file diff --git a/arch/arm64/boot/dts/qcom/guacamoleb_pvt.dtsi b/arch/arm64/boot/dts/qcom/guacamoleb_pvt.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..18b79ae52abaee1b2905554c37a4abb1f2b35a21 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamoleb_pvt.dtsi @@ -0,0 +1 @@ +/*this is for one project different hw version */ \ No newline at end of file diff --git a/arch/arm64/boot/dts/qcom/guacamoleb_sm8150.dtsi b/arch/arm64/boot/dts/qcom/guacamoleb_sm8150.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..8ec64a5dc40811d133112dff0b41f099e0734d09 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamoleb_sm8150.dtsi @@ -0,0 +1,7 @@ +/*this is for sm8150 version */ +&ois_rear_0 { +ois_gyro,id = <3>;//18821 +}; +&ois_rear_1 { +ois_gyro,id = <3>;//18821 +}; diff --git a/arch/arm64/boot/dts/qcom/guacamoleb_t0.dtsi b/arch/arm64/boot/dts/qcom/guacamoleb_t0.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..479382ca9ad90a1d9f20e80ddf3b8ed514217b6d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamoleb_t0.dtsi @@ -0,0 +1,4 @@ +/*this is for one project different hw version */ + + + diff --git a/arch/arm64/boot/dts/qcom/guacamoles-sdx50m-overlay-dvt.dts b/arch/arm64/boot/dts/qcom/guacamoles-sdx50m-overlay-dvt.dts new file mode 100644 index 0000000000000000000000000000000000000000..5d9f553032f1f919df52e1531948fe228d3debb6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamoles-sdx50m-overlay-dvt.dts @@ -0,0 +1,45 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdx50m.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamoles_sdx50m.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_dvt.dtsi" + +#include "guacamoles_sdx50m_dvt.dtsi" + +/ { + model = "SDX50M MTP 18825 15"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <0x01010008 0x1>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18825>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <15>; + +}; diff --git a/arch/arm64/boot/dts/qcom/guacamoles-sdx50m-overlay-evt.dts b/arch/arm64/boot/dts/qcom/guacamoles-sdx50m-overlay-evt.dts new file mode 100644 index 0000000000000000000000000000000000000000..2b3166bb095961bb813d61d67f7587e08021d5b3 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamoles-sdx50m-overlay-evt.dts @@ -0,0 +1,45 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdx50m.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamoles_sdx50m.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_evt1.dtsi" + +#include "guacamoles_sdx50m_evt.dtsi" + +/ { + model = "SDX50M MTP 18825 24"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <0x01010008 0x1>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18825>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <24>; + +}; diff --git a/arch/arm64/boot/dts/qcom/guacamoles-sdx50m-overlay-pvt.dts b/arch/arm64/boot/dts/qcom/guacamoles-sdx50m-overlay-pvt.dts new file mode 100644 index 0000000000000000000000000000000000000000..5e6f508497cc4405e1013f190e025473b28626d4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamoles-sdx50m-overlay-pvt.dts @@ -0,0 +1,45 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdx50m.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamoles_sdx50m.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_pvt.dtsi" + +#include "guacamoles_sdx50m_pvt.dtsi" + +/ { + model = "SDX50M MTP 18825 21"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <0x01010008 0x1>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18825>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <21>; + +}; diff --git a/arch/arm64/boot/dts/qcom/guacamoles-sdx50m-overlay-t0.dts b/arch/arm64/boot/dts/qcom/guacamoles-sdx50m-overlay-t0.dts new file mode 100644 index 0000000000000000000000000000000000000000..a2b12f352416e7d367d27c7c47178d69477a4e20 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamoles-sdx50m-overlay-t0.dts @@ -0,0 +1,44 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdx50m.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamoles_sdx50m.dtsi" +#include "guacamole_t0.dtsi" + +#include "guacamoles_sdx50m_t0.dtsi" + +/ { + model = "SDX50M MTP 18825 11"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <0x01010008 0x1>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18825>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <11>; + +}; diff --git a/arch/arm64/boot/dts/qcom/guacamoles_sdx50m.dtsi b/arch/arm64/boot/dts/qcom/guacamoles_sdx50m.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..74a3457efd7b335c393e7bfc80c823fb2c34ef21 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamoles_sdx50m.dtsi @@ -0,0 +1,11 @@ +/*this is for sdx50m project */ +&ois_rear_0 { +ois_gyro,id = <2>;//18827 +}; +&ois_rear_1 { +ois_gyro,id = <2>;//18827 +}; + +&pm8150b_charger { + op,dis_ctrl_current; +}; diff --git a/arch/arm64/boot/dts/qcom/guacamoles_sdx50m_dvt.dtsi b/arch/arm64/boot/dts/qcom/guacamoles_sdx50m_dvt.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..50cb0f3e043601c99377aeffce727b4a013d162c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamoles_sdx50m_dvt.dtsi @@ -0,0 +1,2 @@ +/*this is for sdx50m project */ + diff --git a/arch/arm64/boot/dts/qcom/guacamoles_sdx50m_evt.dtsi b/arch/arm64/boot/dts/qcom/guacamoles_sdx50m_evt.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..25e705a507d391c03ab8ce123ff40fd1dc501b92 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamoles_sdx50m_evt.dtsi @@ -0,0 +1 @@ +/*this is for sdx50m project */ diff --git a/arch/arm64/boot/dts/qcom/guacamoles_sdx50m_pvt.dtsi b/arch/arm64/boot/dts/qcom/guacamoles_sdx50m_pvt.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..25e705a507d391c03ab8ce123ff40fd1dc501b92 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamoles_sdx50m_pvt.dtsi @@ -0,0 +1 @@ +/*this is for sdx50m project */ diff --git a/arch/arm64/boot/dts/qcom/guacamoles_sdx50m_t0.dtsi b/arch/arm64/boot/dts/qcom/guacamoles_sdx50m_t0.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..25e705a507d391c03ab8ce123ff40fd1dc501b92 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamoles_sdx50m_t0.dtsi @@ -0,0 +1 @@ +/*this is for sdx50m project */ diff --git a/arch/arm64/boot/dts/qcom/hotdogb-overlay-dvt-second.dts b/arch/arm64/boot/dts/qcom/hotdogb-overlay-dvt-second.dts new file mode 100644 index 0000000000000000000000000000000000000000..318774b09d7ba39b69ccf24281281a765b5844d2 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/hotdogb-overlay-dvt-second.dts @@ -0,0 +1,39 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" +#include "sm8150-oem-camera-hotdogb-t0.dtsi" + +#include "sm8150-oem.dtsi" +#include "hotdogb_sm8150.dtsi" +#include "hotdogb.dtsi" +#include "hotdogb_dvt_second.dtsi" + +/ { + model = "MTP 18865 19863 43 53"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0 >; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18865 19863>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <43 53>; +}; + diff --git a/arch/arm64/boot/dts/qcom/hotdogb-overlay-dvt.dts b/arch/arm64/boot/dts/qcom/hotdogb-overlay-dvt.dts new file mode 100644 index 0000000000000000000000000000000000000000..f64242076caeecfdfd743dad4f391c3997f9f5fb --- /dev/null +++ b/arch/arm64/boot/dts/qcom/hotdogb-overlay-dvt.dts @@ -0,0 +1,39 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" +#include "sm8150-oem-camera-hotdogb-t0.dtsi" + +#include "sm8150-oem.dtsi" +#include "hotdogb_sm8150.dtsi" +#include "hotdogb.dtsi" +#include "hotdogb_dvt.dtsi" + +/ { + model = "MTP 18865 19863 13"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0 >; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18865 19863>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <13>; +}; + diff --git a/arch/arm64/boot/dts/qcom/hotdogb-overlay-evt-second.dts b/arch/arm64/boot/dts/qcom/hotdogb-overlay-evt-second.dts new file mode 100644 index 0000000000000000000000000000000000000000..954948cdbd2802a7c87da11fb4168cc47feffef9 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/hotdogb-overlay-evt-second.dts @@ -0,0 +1,38 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" +#include "sm8150-oem-camera-hotdogb-t0.dtsi" + +#include "sm8150-oem.dtsi" +#include "hotdogb_sm8150.dtsi" +#include "hotdogb.dtsi" +#include "hotdogb_evt_second.dtsi" + +/ { + model = "MTP 18865 19863 52"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18865 19863>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <52>; +}; diff --git a/arch/arm64/boot/dts/qcom/hotdogb-overlay-evt.dts b/arch/arm64/boot/dts/qcom/hotdogb-overlay-evt.dts new file mode 100644 index 0000000000000000000000000000000000000000..e01a21fde2024f28b404aa294ce0c837aa6e94b7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/hotdogb-overlay-evt.dts @@ -0,0 +1,39 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" +#include "sm8150-oem-camera-hotdogb-t0.dtsi" + +#include "sm8150-oem.dtsi" +#include "hotdogb_sm8150.dtsi" +#include "hotdogb.dtsi" +#include "hotdogb_evt.dtsi" + +/ { + model = "MTP 18865 19863 12"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18865 19863>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <12>; +}; + diff --git a/arch/arm64/boot/dts/qcom/hotdogb-overlay-pvt-second.dts b/arch/arm64/boot/dts/qcom/hotdogb-overlay-pvt-second.dts new file mode 100644 index 0000000000000000000000000000000000000000..7de493c0a14f5156d57c5e77f561ebe5b5e54b93 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/hotdogb-overlay-pvt-second.dts @@ -0,0 +1,39 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" +#include "sm8150-oem-camera-hotdogb-t0.dtsi" + +#include "sm8150-oem.dtsi" +#include "hotdogb_sm8150.dtsi" +#include "hotdogb.dtsi" +#include "hotdogb_pvt_second.dtsi" + +/ { + model = "MTP 18865 19863 44 54"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0 >; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18865 19863>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <44 54>; +}; + diff --git a/arch/arm64/boot/dts/qcom/hotdogb-overlay-pvt.dts b/arch/arm64/boot/dts/qcom/hotdogb-overlay-pvt.dts new file mode 100644 index 0000000000000000000000000000000000000000..034cc980c6e6b2eb0e6b8879faf818593d838874 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/hotdogb-overlay-pvt.dts @@ -0,0 +1,39 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" +#include "sm8150-oem-camera-hotdogb-t0.dtsi" + +#include "sm8150-oem.dtsi" +#include "hotdogb_sm8150.dtsi" +#include "hotdogb.dtsi" +#include "hotdogb_pvt.dtsi" + +/ { + model = "MTP 18865 19863 14 15"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0 >; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18865 19863>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <14 15>; +}; + diff --git a/arch/arm64/boot/dts/qcom/hotdogb-overlay-t0.dts b/arch/arm64/boot/dts/qcom/hotdogb-overlay-t0.dts new file mode 100644 index 0000000000000000000000000000000000000000..af46aa2981ac8d8f3d441e7c9055482df2be7cb9 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/hotdogb-overlay-t0.dts @@ -0,0 +1,39 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" +#include "sm8150-oem-camera-hotdogb-t0.dtsi" + +#include "sm8150-oem.dtsi" +#include "hotdogb_sm8150.dtsi" +#include "hotdogb.dtsi" +#include "hotdogb_t0.dtsi" + +/ { + model = "MTP 18865 19863 T0 11"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18865 19863>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <11>; +}; + diff --git a/arch/arm64/boot/dts/qcom/hotdogb.dtsi b/arch/arm64/boot/dts/qcom/hotdogb.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..eb180c85465c774b2aa29f951e7808910be46eca --- /dev/null +++ b/arch/arm64/boot/dts/qcom/hotdogb.dtsi @@ -0,0 +1,601 @@ +/*this is for different project dtsi*/ +/* OnePlus add thermistor, by rio.zhao*/ +&pm8150_adc_tm { + skin_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm1 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&thermal_zones { + skin-therm { + polling-delay-passive = <2000>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM1_PU2>; + trips { + freq_config1: freq_config1 { + temperature = <52000>; + hysteresis = <2000>; + type = "passive"; + }; + freq_config2: freq_config2 { + temperature = <54000>; + hysteresis = <2000>; + type = "passive"; + }; + }; + cooling-maps { + freq_dev0 { + trip = <&freq_config1>; + cooling-device = + <&msm_gpu THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-1)>;/*345*/ + }; + freq_dev1 { + trip = <&freq_config1>; + cooling-device = + <&CPU0 9 9>;/*1036*/ + }; + freq_dev2 { + trip = <&freq_config1>; + cooling-device = + <&CPU4 13 13>;/*1056*/ + }; + freq_dev3 { + trip = <&freq_config1>; + cooling-device = + <&CPU7 16 16>;/*1171*/ + }; + freq_dev4 { + trip = <&freq_config2>; + cooling-device = + <&CPU0 11 11>;/*844*/ + }; + freq_dev5 { + trip = <&freq_config2>; + cooling-device = + <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + freq_dev6 { + trip = <&freq_config2>; + cooling-device = + <&CPU5 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + freq_dev7 { + trip = <&freq_config2>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + freq_dev8 { + trip = <&freq_config2>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pa-therm1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM2_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + skin-msm-therm { + trips { + freq_config3: freq_config3 { + temperature = <63000>; + hysteresis = <2000>; + type = "passive"; + }; + freq_config4: freq_config4 { + temperature = <65000>; + hysteresis = <2000>; + type = "passive"; + }; + }; + cooling-maps { + freq_dev0 { + trip = <&freq_config3>; + cooling-device = + <&CPU0 2 2>;/*1632 18*/ + }; + freq_dev1 { + trip = <&freq_config3>; + cooling-device = + <&CPU4 8 8>;/*1612 17*/ + }; + freq_dev2 { + trip = <&freq_config3>; + cooling-device = + <&CPU7 9 9>;/*1920 20*/ + }; + freq_dev3 { + trip = <&freq_config4>; + cooling-device = + <&CPU0 4 4>;/*1478*/ + }; + freq_dev4 { + trip = <&freq_config4>; + cooling-device = + <&CPU4 11 11>;/*1286*/ + }; + freq_dev5 { + trip = <&freq_config4>; + cooling-device = + <&CPU7 13 13>;/*1497*/ + }; + freq_dev6 { + trip = <&freq_config3>; + cooling-device = + <&msm_gpu THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-3)>;/*499*/ + }; + freq_dev7 { + trip = <&freq_config4>; + cooling-device = + <&msm_gpu THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-2)>;/*427*/ + }; + }; + }; +}; + +/*tp 1.8v power change to gpio119 for T0 hw*/ +&qupv3_se17_i2c { + sec-s6sy761@48 { + status = "disable"; + // enable1v8_gpio = <&tlmm 119 0x00>; + pinctrl-0 = <&tp_irq_active &tp_rst_active &tp_1v8_t0_active>; + pinctrl-1 = <&tp_rst_suspend &tp_1v8_t0_suspend>; + }; +}; +&qupv3_se17_i2c { + st_fts@49{ + status = "disable"; + }; +}; +&qupv3_se17_i2c { + synaptics-s3706@20 { + project-name = "18865"; + //enable1v8_gpio = <&tlmm 119 0x00>; + reset-gpio = <&tlmm 80 0x00>; + touchpanel,display-coords = <1079 2399>; + touchpanel,panel-coords = <1079 2399>; + touchpanel,tx-rx-num = <15 34>; + module_id_support = <1>; + ctrl_base_change = <1>; /*only change for 18865*/ + pinctrl-0 = <&tp_irq_active &tp_1v8_t0_active &tp_rst_active>; + pinctrl-1 = <&tp_rst_suspend &tp_1v8_t0_suspend>; + }; + /delete-node/ sec-s6sy761@48; + /delete-node/ st_fts@49; +}; + +&tp_rst_active{ + mux { + pins = "gpio80"; + function = "gpio"; + }; + config { + pins = "gpio80"; + drive-strength = <8>; + bias-pull-up; + }; + +}; +&tlmm { + tp_1v8_t0_active: tp_1v8_t0_active { + mux { + pins = "gpio119"; + function = "gpio"; + }; + config { + pins = "gpio119"; + drive-strength = <8>; + bias-pull-up; + }; + }; + tp_1v8_t0_suspend: tp_1v8_t0_suspend { + mux { + pins = "gpio119"; + function = "gpio"; + }; + config { + pins = "gpio119"; + drive-strength = <8>; + bias-pull-down; + }; + }; +}; + +/* add for hall tri_state_key */ + +&tri_state_key { + compatible = "oneplus,hall_tri_state_key"; + status = "ok"; + interrupt-parent = <&tlmm>; +}; + +&qupv3_se9_i2c { + //qcom,clk-freq-out = <300000>; + status = "ok"; + magnachip@0D { + compatible = "tri_key_magnachip,tk_mxm1120,up"; + reg = <0x0D>; + vdd-supply = <&pm8150l_l7>; + magnachip,init-interval = <200>; + interrupt-parent = <&tlmm>; + interrupts = <10 0x02>; + dhall,irq-gpio = <&tlmm 10 0x2008>; + mxm,id = <1>; + pinctrl-names = "uphall_tri_state_key_active"; + pinctrl-0 = <&uphall_tri_state_key_active>; + }; + magnachip@0C { + compatible = "tri_key_magnachip,tk_mxm1120,down"; + reg = <0x0C>; + vdd-supply = <&pm8150l_l7>; + magnachip,init-interval = <200>; + interrupt-parent = <&tlmm>; + interrupts = <36 0x02>; + dhall,irq-gpio = <&tlmm 36 0x2008>; + mxm,id = <2>; + pinctrl-names = "downhall_tri_state_key_active"; + pinctrl-0 = <&downhall_tri_state_key_active>; + }; +}; + +&qupv3_se9_i2c { + status = "ok"; + ist8801@19 { + compatible = "oneplus,hall-ist8801,up"; + reg = <0x19>; + dhall,id = <1>; + interrupt-parent = <&tlmm>; + dhall,irq-gpio = <&tlmm 10 0x2008>; + vdd-supply = <&pm8150l_l7>; + pinctrl-names = "ist8801_hall_up_active"; + pinctrl-0 = <&ist8801_hall_up_active>; + }; + ist8801@18 { + compatible = "oneplus,hall-ist8801,down"; + reg = <0x18>; + dhall,id = <2>; + interrupt-parent = <&tlmm>; + dhall,irq-gpio = <&tlmm 36 0x2008>; + vdd-supply = <&pm8150l_l7>; + pinctrl-names = "ist8801_hall_down_active"; + pinctrl-0 = <&ist8801_hall_down_active>; + }; +}; +&tlmm { + uphall_tri_state_key_active: uphall_tri_state_key_active { + mux { + pins = "gpio10"; + function = "gpio"; + }; + config { + pins = "gpio10"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + downhall_tri_state_key_active: downhall_tri_state_key_active { + mux { + pins = "gpio36"; + function = "gpio"; + }; + config { + pins = "gpio36"; + drive-strength = <2>; + bias-pull-up; + }; + }; + ist8801_hall_up_active: ist8801_hall_up_active { + mux { + pins = "gpio10"; + function = "gpio"; + }; + config { + pins = "gpio10"; + drive-strength = <2>; + bias-pull-up; + }; + }; + ist8801_hall_down_active: ist8801_hall_down_active { + mux { + pins = "gpio36"; + function = "gpio"; + }; + config { + pins = "gpio36"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + +/* for Battery & Charging STRAT */ +&qupv3_se8_i2c { + oneplus_fastchg@26{ + //microchip,mcu-en-gpio = <&tlmm 10 0x00>; + microchip,mcu-en-gpio = <&tlmm 134 0x00>; + microchip,usb-sw-2-gpio = <&tlmm 59 0x00>; + op,mcl_verion; + op,3800mAh_4p45_support; + }; +}; + +&pm8150b_charger { + /* for external ship mode support */ + op,stm-ctrl-gpio = <&tlmm 21 0x00>; + op,vbus-ctrl-gpio = <&pm8150_gpios 9 GPIO_ACTIVE_LOW>; + + /*not need vph sel 300mv for LCD DCDC mode switch issue*/ + vph-sel-disable; + + /* ibatmax setting for different temp regions */ + ibatmax-little-cold-ma = <320>; + ibatmax-little-cool-thr-ma = <1750>; + ibatmax-cool-thr-ma = <1000>; + ibatmax-cool-ma = <1450>; + ibatmax-warm-ma = <1050>; + op,little_cold_term_current = <250>; + + /* for usb connecter temperature check */ + op,normal-check-interval-period = <300>; + op,fast-check-interval-period = <50>; + op,fast-check-threshold-temp = <33>; + op,high-temp-short-check-timeout = <1500>; + op,first-protect-connecter-temp = <60>; + op,second-protect-connecter-temp = <45>; + op,second-protect-interval-temp = <12>; + op,third-protect-rise-rate = <3>; + op,third-protect-loop-temp = <40>; + op,third-protect-interval-temp = <8>; + + /* for charge current&voltage curve optimize */ + op,fv-offset-voltage-mv = <50>; + + /* skin thermal temp adjust the dash current */ + op,skin-thermal-high-threshold = <37>; + op,skin-thermal-normal-threshold = <34>; + op,enable-dash-current-dynamic-adjust; + + /* for 4p45v not charge full issue add sw full count numb */ + op,full-count-sw-numb = <2>; + + io-channels = <&pm8150b_vadc ADC_MID_CHG_DIV6>, + <&pm8150b_vadc ADC_USB_IN_V_16>, + <&pm8150b_vadc ADC_USB_IN_I>, + <&pm8150b_vadc ADC_CHG_TEMP>, + <&pm8150b_vadc ADC_AMUX_THM4_PU1>, + <&pm8150_vadc ADC_AMUX_THM1_PU2>, + <&pm8150b_vadc ADC_VPH_PWR>, + <&pm8150b_vadc ADC_SBUx>; + io-channel-names = "mid_voltage", + "usb_in_voltage", + "usb_in_current", + "chg_temp", + "gpio1_voltage", + "skin_therm", + "vph_voltage", + "sbux_res"; +}; + +&mtp_batterydata { + #include "OP-fg-batterydata-3800mah.dtsi" +}; +/* for Battery & Charging END */ + +/* @bsp, USB oem config START*/ +&usb2_phy0 { + qcom,param-override-seq = + <0x67 0x6c/*Disconnection voltage +21.56%*/ + 0x09 0x70/*Pre-emphasis:4x DC voltage level:+13.30%*/ + 0x28 0x74>; +}; + +&extcon_usb1 { + status = "disabled"; +}; + +&usb1 { + status = "disabled"; +}; +/* @bsp, USB oem config END*/ + +&motor_pl { + status = "disabled"; +}; + +&oem_rf_cable { + rf,cable-gpio-0 = <&tlmm 121 0>; +}; + +&rf_cable_ant0_active { + mux { + pins = "gpio121"; + function = "gpio"; + }; + config { + pins = "gpio121"; + drive-strength = <2>; + bias-pull-up; + }; +}; + +&pm8150_gpios { + rf_pm8150_cable_ant1: rf_pm8150_cable_ant1 { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + bias-pull-up; + input-enable; + }; + ab_id1 { + ab_id1_default: ab_id1_default { + pins = "gpio1"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + qcom,drive-strength = <3>; /* low */ + }; + ab_id1_sleep: ab_id1_sleep { + pins = "gpio1"; + function = "normal"; + input-enable; + bias-disable; + power-source = <0>; + qcom,drive-strength = <3>; /* low */ + }; + + }; +}; +&pm8150b_gpios { + haptics_boost { + haptics_boost_default: haptics_boost_default { + pins = "gpio5"; + function = "normal"; + output-enable; + input-disable; + bias-disable; + qcom,drive-strength = <3>; /* high */ + power-source = <0>; /* VPH_PWR */ + }; + }; + ab_id2 { + ab_id2_default: ab_id2_default { + pins = "gpio2"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + qcom,drive-strength = <3>; /* low */ + }; + ab_id2_sleep: ab_id2_sleep { + pins = "gpio2"; + function = "normal"; + input-enable; + bias-disable; + power-source = <0>; + qcom,drive-strength = <3>; /* low */ + }; + + }; +}; + +&oem_aboard_check { + pinctrl-names = "oem_aboard_active","oem_aboard_sleep"; + pinctrl-0 = <&ab_id1_default &ab_id2_default>; + pinctrl-1 = <&ab_id1_sleep &ab_id2_sleep>; +}; + +&vendor { + step_motor { + status = "disabled"; + }; +}; + +&pm8150b_gpios { + haptics_boost { + haptics_boost_default: haptics_boost_default { + pins = "gpio5"; + function = "normal"; + output-enable; + input-disable; + bias-disable; + qcom,drive-strength = <3>; /* high */ + power-source = <0>; /* VPH_PWR */ + }; + }; +}; + +&vendor { + haptics_boost_vreg: haptics_boost_vreg { + compatible = "regulator-fixed"; + regulator-name = "haptics_boost"; + gpio = <&pm8150b_gpios 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-enable-ramp-delay = <300>; + pinctrl-names = "default"; + pinctrl-0 = <&haptics_boost_default>; + status = "ok"; + }; +}; +&pm8150b_haptics { + status = "ok"; + vdd-supply = <&haptics_boost_vreg>; + wf_6 { + /* WEAK */ + qcom,effect-id = <6>; + qcom,wf-vmax-mv = <2500>; + qcom,wf-pattern = [7e 7e 7e fe fe]; + qcom,wf-play-rate-us = <6667>; + qcom,wf-brake-pattern = [00 00 00 00]; + qcom,lra-auto-resonance-disable; + }; + wf_7 { + /* MIDDLE */ + qcom,effect-id = <7>; + qcom,wf-vmax-mv = <2500>; + qcom,wf-pattern = [7e 7e 7e 7e fe fe fe]; + qcom,wf-play-rate-us = <6667>; + qcom,wf-brake-pattern = [00 00 00 00]; + qcom,lra-auto-resonance-disable; + }; + wf_8 { + /* STRONG */ + qcom,effect-id = <8>; + qcom,wf-vmax-mv = <2500>; + qcom,wf-pattern = [7e 7e 7e 7e 7e fe fe fe]; + qcom,wf-play-rate-us = <6667>; + qcom,wf-brake-pattern = [00 00 00 00]; + qcom,lra-auto-resonance-disable; + }; +}; + +&wdog{ + qcom,bark-time = <15000>; +}; + +&motor_pl { + status = "disabled"; +}; + +&qupv3_se1_i2c { + magnachip@0C { + status = "disabled"; + }; + + magnachip@0D { + status = "disabled"; + }; +}; + +&aw8697_haptic { + op,count_go; +}; + diff --git a/arch/arm64/boot/dts/qcom/hotdogb_dvt.dtsi b/arch/arm64/boot/dts/qcom/hotdogb_dvt.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..87593fa94f17d36658c7e47eb59d13984fcb5617 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/hotdogb_dvt.dtsi @@ -0,0 +1,57 @@ +/*this is for one project different hw version */ +&bq27541_battery { + op,bat-4p45v; +}; + +&pm8150b_charger { + qcom,fcc-max-ua = <2000000>; + qcom,usb-icl-ua = <1800000>; + /* ibatmax setting for different temp regions */ + ibatmax-little-cold-ma = <350>; + ibatmax-cool-ma = <1750>; + ibatmax-little-cool-ma = <2000>; + ibatmax-pre-normal-ma = <2000>; + ibatmax-normal-ma = <2000>; + ibatmax-warm-ma = <1050>; + ibatmax-little-cool-thr-ma = <1750>; + ibatmax-cool-thr-ma = <1050>; + /* vbatmax setting for different temp regions */ + vbatmax-little-cold-mv = <3975>; + vbatmax-cool-mv = <4435>; + vbatmax-little-cool-mv = <4435>; + vbatmax-pre-normal-mv = <4435>; + vbatmax-normal-mv = <4435>; + vbatmax-warm-mv = <4130>; + little-cool-vbat-thr-mv = <4180>; + cool-vbat-thr-mv = <4180>; + /* vbatdet setting for different temp regions */ + vbatdet-little-cold-mv = <3675>; + vbatdet-cool-mv = <4235>; + vbatdet-little-cool-mv = <4335>; + vbatdet-pre-normal-mv = <4335>; + vbatdet-normal-mv = <4335>; + vbatdet-warm-mv = <4030>; + /* temp region settings */ + cold-bat-decidegc = <20>; + little-cold-bat-decidegc = <0>; + cool-bat-decidegc = <50>; + little-cool-bat-decidegc = <120>; + pre-normal-bat-decidegc = <160>; + warm-bat-decidegc = <450>; + hot-bat-decidegc = <500>; + qcom,otg-cl-ua = <1500000>; + op,sw-iterm-ma = <210>; + op,sw-check-full-enable; + + /*ffc temp region*/ + ffc-pre-normal-decidegc = <120>; + ffc-normal-decidegc = <350>; + ffc-warm-decidegc = <400>; + ffc-normal-fcc-ma = <950>; + ffc-warm-fcc-ma = <1050>; + ffc-normal-cutoff-ma = <800>; + ffc-warm-cutoff-ma = <880>; + ffc-full-vbat-mv = <4480>; + + /delete-property/ qcom,sw-jeita-enable; +}; diff --git a/arch/arm64/boot/dts/qcom/hotdogb_dvt_second.dtsi b/arch/arm64/boot/dts/qcom/hotdogb_dvt_second.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..9c8c92af602ef33ff16556c1da958c7536de3a4d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/hotdogb_dvt_second.dtsi @@ -0,0 +1,93 @@ +/*this is for one project different hw version */ +&bq27541_battery { + op,bat-4p45v; +}; + +&pm8150b_charger { + qcom,fcc-max-ua = <2000000>; + qcom,usb-icl-ua = <1800000>; + /* ibatmax setting for different temp regions */ + ibatmax-little-cold-ma = <350>; + ibatmax-cool-ma = <1750>; + ibatmax-little-cool-ma = <2000>; + ibatmax-pre-normal-ma = <2000>; + ibatmax-normal-ma = <2000>; + ibatmax-warm-ma = <1050>; + ibatmax-little-cool-thr-ma = <1750>; + ibatmax-cool-thr-ma = <1050>; + /* vbatmax setting for different temp regions */ + vbatmax-little-cold-mv = <3975>; + vbatmax-cool-mv = <4435>; + vbatmax-little-cool-mv = <4435>; + vbatmax-pre-normal-mv = <4435>; + vbatmax-normal-mv = <4435>; + vbatmax-warm-mv = <4130>; + little-cool-vbat-thr-mv = <4180>; + cool-vbat-thr-mv = <4180>; + /* vbatdet setting for different temp regions */ + vbatdet-little-cold-mv = <3675>; + vbatdet-cool-mv = <4235>; + vbatdet-little-cool-mv = <4335>; + vbatdet-pre-normal-mv = <4335>; + vbatdet-normal-mv = <4335>; + vbatdet-warm-mv = <4030>; + /* temp region settings */ + cold-bat-decidegc = <20>; + little-cold-bat-decidegc = <0>; + cool-bat-decidegc = <50>; + little-cool-bat-decidegc = <120>; + pre-normal-bat-decidegc = <160>; + warm-bat-decidegc = <450>; + hot-bat-decidegc = <500>; + qcom,otg-cl-ua = <1500000>; + op,sw-iterm-ma = <210>; + op,sw-check-full-enable; + + /*ffc temp region*/ + ffc-pre-normal-decidegc = <120>; + ffc-normal-decidegc = <350>; + ffc-warm-decidegc = <400>; + ffc-normal-fcc-ma = <950>; + ffc-warm-fcc-ma = <1050>; + ffc-normal-cutoff-ma = <800>; + ffc-warm-cutoff-ma = <880>; + ffc-full-vbat-mv = <4480>; + + /delete-property/ qcom,sw-jeita-enable; +}; + +&qupv3_se8_i2c { + oneplus_fastchg@26{ + status = "disable"; + }; + + oneplus_fastchg@52{ + status = "ok"; + compatible = "microchip,oneplus_fastchg"; + reg = <0x52>; + microchip,mcu-en-gpio = <&tlmm 134 0x00>; + microchip,usb-sw-1-gpio = <&tlmm 94 0x00>; + microchip,usb-sw-2-gpio = <&tlmm 59 0x00>; + microchip,ap-clk = <&tlmm 92 0x00>; + microchip,ap-data = <&tlmm 93 0x00>; + op,fw-erase-count = <959>; + op,fw-addr-low = <0>; + op,fw-addr-high = <0>; + op,n76e_support; + op,mcl_verion; + + pinctrl-names = "mux_fastchg_active", + "mux_fastchg_suspend", + "mcu_data_active", + "mcu_data_suspend"; + pinctrl-0 = <&fastchg_active + &usb_sw_active + &ap_clk_active >; + pinctrl-1 = <&usb_sw_suspend + &fastchg_suspend + &ap_clk_suspend>; + pinctrl-2 =<&ap_data_active>; + pinctrl-3 =<&ap_data_suspend>; + }; +}; + diff --git a/arch/arm64/boot/dts/qcom/hotdogb_evt.dtsi b/arch/arm64/boot/dts/qcom/hotdogb_evt.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..87593fa94f17d36658c7e47eb59d13984fcb5617 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/hotdogb_evt.dtsi @@ -0,0 +1,57 @@ +/*this is for one project different hw version */ +&bq27541_battery { + op,bat-4p45v; +}; + +&pm8150b_charger { + qcom,fcc-max-ua = <2000000>; + qcom,usb-icl-ua = <1800000>; + /* ibatmax setting for different temp regions */ + ibatmax-little-cold-ma = <350>; + ibatmax-cool-ma = <1750>; + ibatmax-little-cool-ma = <2000>; + ibatmax-pre-normal-ma = <2000>; + ibatmax-normal-ma = <2000>; + ibatmax-warm-ma = <1050>; + ibatmax-little-cool-thr-ma = <1750>; + ibatmax-cool-thr-ma = <1050>; + /* vbatmax setting for different temp regions */ + vbatmax-little-cold-mv = <3975>; + vbatmax-cool-mv = <4435>; + vbatmax-little-cool-mv = <4435>; + vbatmax-pre-normal-mv = <4435>; + vbatmax-normal-mv = <4435>; + vbatmax-warm-mv = <4130>; + little-cool-vbat-thr-mv = <4180>; + cool-vbat-thr-mv = <4180>; + /* vbatdet setting for different temp regions */ + vbatdet-little-cold-mv = <3675>; + vbatdet-cool-mv = <4235>; + vbatdet-little-cool-mv = <4335>; + vbatdet-pre-normal-mv = <4335>; + vbatdet-normal-mv = <4335>; + vbatdet-warm-mv = <4030>; + /* temp region settings */ + cold-bat-decidegc = <20>; + little-cold-bat-decidegc = <0>; + cool-bat-decidegc = <50>; + little-cool-bat-decidegc = <120>; + pre-normal-bat-decidegc = <160>; + warm-bat-decidegc = <450>; + hot-bat-decidegc = <500>; + qcom,otg-cl-ua = <1500000>; + op,sw-iterm-ma = <210>; + op,sw-check-full-enable; + + /*ffc temp region*/ + ffc-pre-normal-decidegc = <120>; + ffc-normal-decidegc = <350>; + ffc-warm-decidegc = <400>; + ffc-normal-fcc-ma = <950>; + ffc-warm-fcc-ma = <1050>; + ffc-normal-cutoff-ma = <800>; + ffc-warm-cutoff-ma = <880>; + ffc-full-vbat-mv = <4480>; + + /delete-property/ qcom,sw-jeita-enable; +}; diff --git a/arch/arm64/boot/dts/qcom/hotdogb_evt_second.dtsi b/arch/arm64/boot/dts/qcom/hotdogb_evt_second.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..d4ceb266b3cea5344fbb5278ed9f444c546b461e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/hotdogb_evt_second.dtsi @@ -0,0 +1,92 @@ +/*this is for one project different hw version */ +&bq27541_battery { + op,bat-4p45v; +}; + +&pm8150b_charger { + qcom,fcc-max-ua = <2000000>; + qcom,usb-icl-ua = <1800000>; + /* ibatmax setting for different temp regions */ + ibatmax-little-cold-ma = <350>; + ibatmax-cool-ma = <1750>; + ibatmax-little-cool-ma = <2000>; + ibatmax-pre-normal-ma = <2000>; + ibatmax-normal-ma = <2000>; + ibatmax-warm-ma = <1050>; + ibatmax-little-cool-thr-ma = <1750>; + ibatmax-cool-thr-ma = <1050>; + /* vbatmax setting for different temp regions */ + vbatmax-little-cold-mv = <3975>; + vbatmax-cool-mv = <4435>; + vbatmax-little-cool-mv = <4435>; + vbatmax-pre-normal-mv = <4435>; + vbatmax-normal-mv = <4435>; + vbatmax-warm-mv = <4130>; + little-cool-vbat-thr-mv = <4180>; + cool-vbat-thr-mv = <4180>; + /* vbatdet setting for different temp regions */ + vbatdet-little-cold-mv = <3675>; + vbatdet-cool-mv = <4235>; + vbatdet-little-cool-mv = <4335>; + vbatdet-pre-normal-mv = <4335>; + vbatdet-normal-mv = <4335>; + vbatdet-warm-mv = <4030>; + /* temp region settings */ + cold-bat-decidegc = <20>; + little-cold-bat-decidegc = <0>; + cool-bat-decidegc = <50>; + little-cool-bat-decidegc = <120>; + pre-normal-bat-decidegc = <160>; + warm-bat-decidegc = <450>; + hot-bat-decidegc = <500>; + qcom,otg-cl-ua = <1500000>; + op,sw-iterm-ma = <210>; + op,sw-check-full-enable; + + /*ffc temp region*/ + ffc-pre-normal-decidegc = <120>; + ffc-normal-decidegc = <350>; + ffc-warm-decidegc = <400>; + ffc-normal-fcc-ma = <950>; + ffc-warm-fcc-ma = <1050>; + ffc-normal-cutoff-ma = <800>; + ffc-warm-cutoff-ma = <880>; + ffc-full-vbat-mv = <4480>; + + /delete-property/ qcom,sw-jeita-enable; +}; + +&qupv3_se8_i2c { + oneplus_fastchg@26{ + status = "disable"; + }; + + oneplus_fastchg@52{ + status = "ok"; + compatible = "microchip,oneplus_fastchg"; + reg = <0x52>; + microchip,mcu-en-gpio = <&tlmm 134 0x00>; + microchip,usb-sw-1-gpio = <&tlmm 94 0x00>; + microchip,usb-sw-2-gpio = <&tlmm 59 0x00>; + microchip,ap-clk = <&tlmm 92 0x00>; + microchip,ap-data = <&tlmm 93 0x00>; + op,fw-erase-count = <959>; + op,fw-addr-low = <0>; + op,fw-addr-high = <0>; + op,n76e_support; + op,mcl_verion; + + pinctrl-names = "mux_fastchg_active", + "mux_fastchg_suspend", + "mcu_data_active", + "mcu_data_suspend"; + pinctrl-0 = <&fastchg_active + &usb_sw_active + &ap_clk_active >; + pinctrl-1 = <&usb_sw_suspend + &fastchg_suspend + &ap_clk_suspend>; + pinctrl-2 =<&ap_data_active>; + pinctrl-3 =<&ap_data_suspend>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/hotdogb_pvt.dtsi b/arch/arm64/boot/dts/qcom/hotdogb_pvt.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..87593fa94f17d36658c7e47eb59d13984fcb5617 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/hotdogb_pvt.dtsi @@ -0,0 +1,57 @@ +/*this is for one project different hw version */ +&bq27541_battery { + op,bat-4p45v; +}; + +&pm8150b_charger { + qcom,fcc-max-ua = <2000000>; + qcom,usb-icl-ua = <1800000>; + /* ibatmax setting for different temp regions */ + ibatmax-little-cold-ma = <350>; + ibatmax-cool-ma = <1750>; + ibatmax-little-cool-ma = <2000>; + ibatmax-pre-normal-ma = <2000>; + ibatmax-normal-ma = <2000>; + ibatmax-warm-ma = <1050>; + ibatmax-little-cool-thr-ma = <1750>; + ibatmax-cool-thr-ma = <1050>; + /* vbatmax setting for different temp regions */ + vbatmax-little-cold-mv = <3975>; + vbatmax-cool-mv = <4435>; + vbatmax-little-cool-mv = <4435>; + vbatmax-pre-normal-mv = <4435>; + vbatmax-normal-mv = <4435>; + vbatmax-warm-mv = <4130>; + little-cool-vbat-thr-mv = <4180>; + cool-vbat-thr-mv = <4180>; + /* vbatdet setting for different temp regions */ + vbatdet-little-cold-mv = <3675>; + vbatdet-cool-mv = <4235>; + vbatdet-little-cool-mv = <4335>; + vbatdet-pre-normal-mv = <4335>; + vbatdet-normal-mv = <4335>; + vbatdet-warm-mv = <4030>; + /* temp region settings */ + cold-bat-decidegc = <20>; + little-cold-bat-decidegc = <0>; + cool-bat-decidegc = <50>; + little-cool-bat-decidegc = <120>; + pre-normal-bat-decidegc = <160>; + warm-bat-decidegc = <450>; + hot-bat-decidegc = <500>; + qcom,otg-cl-ua = <1500000>; + op,sw-iterm-ma = <210>; + op,sw-check-full-enable; + + /*ffc temp region*/ + ffc-pre-normal-decidegc = <120>; + ffc-normal-decidegc = <350>; + ffc-warm-decidegc = <400>; + ffc-normal-fcc-ma = <950>; + ffc-warm-fcc-ma = <1050>; + ffc-normal-cutoff-ma = <800>; + ffc-warm-cutoff-ma = <880>; + ffc-full-vbat-mv = <4480>; + + /delete-property/ qcom,sw-jeita-enable; +}; diff --git a/arch/arm64/boot/dts/qcom/hotdogb_pvt_second.dtsi b/arch/arm64/boot/dts/qcom/hotdogb_pvt_second.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..9c8c92af602ef33ff16556c1da958c7536de3a4d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/hotdogb_pvt_second.dtsi @@ -0,0 +1,93 @@ +/*this is for one project different hw version */ +&bq27541_battery { + op,bat-4p45v; +}; + +&pm8150b_charger { + qcom,fcc-max-ua = <2000000>; + qcom,usb-icl-ua = <1800000>; + /* ibatmax setting for different temp regions */ + ibatmax-little-cold-ma = <350>; + ibatmax-cool-ma = <1750>; + ibatmax-little-cool-ma = <2000>; + ibatmax-pre-normal-ma = <2000>; + ibatmax-normal-ma = <2000>; + ibatmax-warm-ma = <1050>; + ibatmax-little-cool-thr-ma = <1750>; + ibatmax-cool-thr-ma = <1050>; + /* vbatmax setting for different temp regions */ + vbatmax-little-cold-mv = <3975>; + vbatmax-cool-mv = <4435>; + vbatmax-little-cool-mv = <4435>; + vbatmax-pre-normal-mv = <4435>; + vbatmax-normal-mv = <4435>; + vbatmax-warm-mv = <4130>; + little-cool-vbat-thr-mv = <4180>; + cool-vbat-thr-mv = <4180>; + /* vbatdet setting for different temp regions */ + vbatdet-little-cold-mv = <3675>; + vbatdet-cool-mv = <4235>; + vbatdet-little-cool-mv = <4335>; + vbatdet-pre-normal-mv = <4335>; + vbatdet-normal-mv = <4335>; + vbatdet-warm-mv = <4030>; + /* temp region settings */ + cold-bat-decidegc = <20>; + little-cold-bat-decidegc = <0>; + cool-bat-decidegc = <50>; + little-cool-bat-decidegc = <120>; + pre-normal-bat-decidegc = <160>; + warm-bat-decidegc = <450>; + hot-bat-decidegc = <500>; + qcom,otg-cl-ua = <1500000>; + op,sw-iterm-ma = <210>; + op,sw-check-full-enable; + + /*ffc temp region*/ + ffc-pre-normal-decidegc = <120>; + ffc-normal-decidegc = <350>; + ffc-warm-decidegc = <400>; + ffc-normal-fcc-ma = <950>; + ffc-warm-fcc-ma = <1050>; + ffc-normal-cutoff-ma = <800>; + ffc-warm-cutoff-ma = <880>; + ffc-full-vbat-mv = <4480>; + + /delete-property/ qcom,sw-jeita-enable; +}; + +&qupv3_se8_i2c { + oneplus_fastchg@26{ + status = "disable"; + }; + + oneplus_fastchg@52{ + status = "ok"; + compatible = "microchip,oneplus_fastchg"; + reg = <0x52>; + microchip,mcu-en-gpio = <&tlmm 134 0x00>; + microchip,usb-sw-1-gpio = <&tlmm 94 0x00>; + microchip,usb-sw-2-gpio = <&tlmm 59 0x00>; + microchip,ap-clk = <&tlmm 92 0x00>; + microchip,ap-data = <&tlmm 93 0x00>; + op,fw-erase-count = <959>; + op,fw-addr-low = <0>; + op,fw-addr-high = <0>; + op,n76e_support; + op,mcl_verion; + + pinctrl-names = "mux_fastchg_active", + "mux_fastchg_suspend", + "mcu_data_active", + "mcu_data_suspend"; + pinctrl-0 = <&fastchg_active + &usb_sw_active + &ap_clk_active >; + pinctrl-1 = <&usb_sw_suspend + &fastchg_suspend + &ap_clk_suspend>; + pinctrl-2 =<&ap_data_active>; + pinctrl-3 =<&ap_data_suspend>; + }; +}; + diff --git a/arch/arm64/boot/dts/qcom/hotdogb_sm8150.dtsi b/arch/arm64/boot/dts/qcom/hotdogb_sm8150.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..e46645fb1b1398c137b42cc689892198d2f53633 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/hotdogb_sm8150.dtsi @@ -0,0 +1,8 @@ +/*this is for sm8150 version */ + &ois_rear_0 { + ois_gyro,id = <3>; + master_cci,id = <0>; + }; + &ois_rear_1 { + ois_gyro,id = <3>; + }; diff --git a/arch/arm64/boot/dts/qcom/hotdogb_t0.dtsi b/arch/arm64/boot/dts/qcom/hotdogb_t0.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..6bb1f0f4de67d78dc2ff6c1c933d68f73c976310 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/hotdogb_t0.dtsi @@ -0,0 +1,15 @@ +/*this is for one project different hw version */ +&pm8150b_charger { + qcom,fcc-max-ua = <2000000>; + qcom,usb-icl-ua = <1800000>; + /* ibatmax setting for different temp regions */ + ibatmax-little-cold-ma = <350>; + ibatmax-cool-ma = <1750>; + ibatmax-little-cool-ma = <2000>; + ibatmax-pre-normal-ma = <2000>; + ibatmax-normal-ma = <2000>; + ibatmax-warm-ma = <1050>; + ibatmax-little-cool-thr-ma = <1750>; + ibatmax-cool-thr-ma = <1050>; +}; + diff --git a/arch/arm64/boot/dts/qcom/msm-arm-smmu-atoll.dtsi b/arch/arm64/boot/dts/qcom/msm-arm-smmu-atoll.dtsi index 9c050f741e010e76dbca25754046dbb66fc735fe..d96746cce5cd20d7c876d5742d85cf6055ac8090 100644 --- a/arch/arm64/boot/dts/qcom/msm-arm-smmu-atoll.dtsi +++ b/arch/arm64/boot/dts/qcom/msm-arm-smmu-atoll.dtsi @@ -10,7 +10,6 @@ * GNU General Public License for more details. */ #include -#include &soc { kgsl_smmu: arm,smmu-kgsl@5040000 { @@ -37,20 +36,6 @@ ; clock-names = "gcc_gpu_memnoc_gfx_clk"; clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>; - - attach-impl-defs = - <0x6000 0x2378>, - <0x6060 0x1055>, - <0x678c 0x8>, - <0x6794 0x28>, - <0x6800 0x6>, - <0x6900 0x3ff>, - <0x6924 0x204>, - <0x6928 0x11000>, - <0x6930 0x800>, - <0x6960 0xffffffff>, - <0x6b64 0x1a5551>, - <0x6b68 0x9a82a382>; }; apps_smmu: apps-smmu@0x15000000 { @@ -146,17 +131,6 @@ , , ; - qcom,msm-bus,name = "apps_smmu"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,active-only; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - , - , - <0 0>, - , - , - <0 1000>; anoc_1_tbu: anoc_1_tbu@0x15185000 { compatible = "qcom,qsmmuv500-tbu"; @@ -164,17 +138,6 @@ <0x15182200 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x0 0x400>; - qcom,msm-bus,name = "apps_smmu"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,active-only; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - , - , - <0 0>, - , - , - <0 1000>; }; anoc_2_tbu: anoc_2_tbu@0x15189000 { @@ -183,17 +146,6 @@ <0x15182208 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x400 0x400>; - qcom,msm-bus,name = "apps_smmu"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,active-only; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - , - , - <0 0>, - , - , - <0 1000>; }; mnoc_hf_0_tbu: mnoc_hf_0_tbu@0x1518d000 { @@ -204,17 +156,6 @@ qcom,stream-id-range = <0x800 0x400>; qcom,regulator-names = "vdd"; vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>; - qcom,msm-bus,name = "mnoc_hf_0_tbu"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,active-only; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - , - , - <0 0>, - , - , - <0 1000>; }; mnoc_sf_0_tbu: mnoc_sf_0_tbu@0x15191000 { @@ -225,17 +166,6 @@ qcom,stream-id-range = <0xc00 0x400>; qcom,regulator-names = "vdd"; vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc>; - qcom,msm-bus,name = "mnoc_sf_0_tbu"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,active-only; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - , - , - <0 0>, - , - , - <0 1000>; }; lpass_noc_tbu: lpass_noc_tbu@0x15195000 { @@ -244,17 +174,6 @@ <0x15182220 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x1000 0x400>; - qcom,msm-bus,name = "apps_smmu"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,active-only; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - , - , - <0 0>, - , - , - <0 1000>; }; compute_dsp_0_tbu: compute_dsp_0_tbu@0x15199000 { @@ -264,17 +183,6 @@ reg-names = "base", "status-reg"; qcom,stream-id-range = <0x1400 0x400>; /* No GDSC */ - qcom,msm-bus,name = "apps_smmu"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,active-only; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - , - , - <0 0>, - , - , - <0 1000>; }; }; @@ -294,13 +202,3 @@ dma-coherent; }; }; - -&apps_smmu { - qcom,actlr = - /* HF_0 and SF_0 TBUs: +3 deep PF */ - <0x800 0x7ff 0x103>, - - /* NPU SIDs: +3 deep PF */ - <0x1460 0x1f 0x303>, - <0x1480 0x1f 0x303>; -}; diff --git a/arch/arm64/boot/dts/qcom/msm-arm-smmu-trinket.dtsi b/arch/arm64/boot/dts/qcom/msm-arm-smmu-trinket.dtsi index f9cb196a2c2f1c0f6ec738e02f67ef3ca6a24707..6fab5f53ea615c34427f7d886ea7c26ccf224aea 100644 --- a/arch/arm64/boot/dts/qcom/msm-arm-smmu-trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/msm-arm-smmu-trinket.dtsi @@ -23,12 +23,12 @@ #iommu-cells = <2>; qcom,dynamic; qcom,skip-init; - qcom,testbus-version = <1>; qcom,no-dynamic-asid; qcom,use-3-lvl-tables; #global-interrupts = <1>; qcom,regulator-names = "vdd"; vdd-supply = <&gpu_cx_gdsc>; + qcom,deferred-regulator-disable-delay = <80>; clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>, <&clock_gcc GCC_GPU_SNOC_DVM_GFX_CLK>, <&clock_gpucc GPU_CC_AHB_CLK>, @@ -56,7 +56,6 @@ <0x59c2200 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x0 0x400>; - interrupts = ; }; }; @@ -155,7 +154,6 @@ <0xc782200 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x0 0x400>; - interrupts = ; qcom,msm-bus,name = "apps_smmu"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,active-only; @@ -181,7 +179,6 @@ <0xc782208 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x400 0x400>; - interrupts = ; qcom,regulator-names = "vdd"; vdd-supply = <&hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc>; qcom,msm-bus,name = "apps_smmu"; @@ -209,7 +206,6 @@ <0xc782210 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x800 0x400>; - interrupts = ; qcom,regulator-names = "vdd"; vdd-supply = <&hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc>; qcom,msm-bus,name = "apps_smmu"; @@ -237,7 +233,6 @@ <0xc782218 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0xc00 0x400>; - interrupts = ; qcom,regulator-names = "vdd"; vdd-supply = <&hlos1_vote_turing_mmu_tbu0_gdsc>; qcom,msm-bus,name = "apps_smmu"; diff --git a/arch/arm64/boot/dts/qcom/msm-audio-lpass.dtsi b/arch/arm64/boot/dts/qcom/msm-audio-lpass.dtsi index ece4cd67e5e4aa7720d4ae14222e829f3ffb3279..34a342a4256127be1b1c53b5ce3e248e12459ea0 100644 --- a/arch/arm64/boot/dts/qcom/msm-audio-lpass.dtsi +++ b/arch/arm64/boot/dts/qcom/msm-audio-lpass.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -179,11 +179,6 @@ qcom,msm-dai-cdc-dma-dev-id = <45091>; }; - va_cdc_dma_2_tx: qcom,msm-dai-va-cdc-dma-2-tx { - compatible = "qcom,msm-dai-cdc-dma-dev"; - qcom,msm-dai-cdc-dma-dev-id = <45093>; - }; - rx_cdc_dma_0_rx: qcom,msm-dai-rx-cdc-dma-0-rx { compatible = "qcom,msm-dai-cdc-dma-dev"; qcom,msm-dai-cdc-dma-dev-id = <45104>; @@ -336,7 +331,6 @@ sb_7_tx: qcom,msm-dai-q6-sb-7-tx { compatible = "qcom,msm-dai-q6-dev"; qcom,msm-dai-q6-dev-id = <16399>; - qcom,msm-dai-q6-slim-dev-id = <0>; }; sb_8_rx: qcom,msm-dai-q6-sb-8-rx { @@ -347,7 +341,6 @@ sb_8_tx: qcom,msm-dai-q6-sb-8-tx { compatible = "qcom,msm-dai-q6-dev"; qcom,msm-dai-q6-dev-id = <16401>; - qcom,msm-dai-q6-slim-dev-id = <0>; }; sb_9_rx: qcom,msm-dai-q6-sb-9-rx { @@ -517,20 +510,6 @@ qcom,msm-cpudai-afe-clk-ver = <2>; }; - dai_sen_auxpcm: qcom,msm-sen-auxpcm { - compatible = "qcom,msm-auxpcm-dev"; - qcom,msm-cpudai-auxpcm-mode = <0>, <0>; - qcom,msm-cpudai-auxpcm-sync = <1>, <1>; - qcom,msm-cpudai-auxpcm-frame = <5>, <4>; - qcom,msm-cpudai-auxpcm-quant = <2>, <2>; - qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>; - qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>; - qcom,msm-cpudai-auxpcm-data = <0>, <0>; - qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>; - qcom,msm-auxpcm-interface = "senary"; - qcom,msm-cpudai-afe-clk-ver = <2>; - }; - hdmi_dba: qcom,msm-hdmi-dba-codec-rx { compatible = "qcom,msm-hdmi-dba-codec-rx"; qcom,dba-bridge-chip = "adv7533"; @@ -732,44 +711,6 @@ }; }; - tdm_sen_rx: qcom,msm-dai-tdm-sen-rx { - compatible = "qcom,msm-dai-tdm"; - qcom,msm-cpudai-tdm-group-id = <37200>; - qcom,msm-cpudai-tdm-group-num-ports = <1>; - qcom,msm-cpudai-tdm-group-port-id = <36944>; - qcom,msm-cpudai-tdm-clk-rate = <1536000>; - qcom,msm-cpudai-tdm-clk-internal = <1>; - qcom,msm-cpudai-tdm-sync-mode = <1>; - qcom,msm-cpudai-tdm-sync-src = <1>; - qcom,msm-cpudai-tdm-data-out = <0>; - qcom,msm-cpudai-tdm-invert-sync = <1>; - qcom,msm-cpudai-tdm-data-delay = <1>; - dai_sen_tdm_rx_0: qcom,msm-dai-q6-tdm-sen-rx-0 { - compatible = "qcom,msm-dai-q6-tdm"; - qcom,msm-cpudai-tdm-dev-id = <36944>; - qcom,msm-cpudai-tdm-data-align = <0>; - }; - }; - - tdm_sen_tx: qcom,msm-dai-tdm-sen-tx { - compatible = "qcom,msm-dai-tdm"; - qcom,msm-cpudai-tdm-group-id = <37201>; - qcom,msm-cpudai-tdm-group-num-ports = <1>; - qcom,msm-cpudai-tdm-group-port-id = <36945>; - qcom,msm-cpudai-tdm-clk-rate = <1536000>; - qcom,msm-cpudai-tdm-clk-internal = <1>; - qcom,msm-cpudai-tdm-sync-mode = <1>; - qcom,msm-cpudai-tdm-sync-src = <1>; - qcom,msm-cpudai-tdm-data-out = <0>; - qcom,msm-cpudai-tdm-invert-sync = <1>; - qcom,msm-cpudai-tdm-data-delay = <1>; - dai_sen_tdm_tx_0: qcom,msm-dai-q6-tdm-sen-tx-0 { - compatible = "qcom,msm-dai-q6-tdm"; - qcom,msm-cpudai-tdm-dev-id = <36945>; - qcom,msm-cpudai-tdm-data-align = <0>; - }; - }; - dai_pri_spdif_rx: qcom,msm-dai-q6-spdif-pri-rx { compatible = "qcom,msm-dai-q6-spdif"; qcom,msm-dai-q6-dev-id = <20480>; diff --git a/arch/arm64/boot/dts/qcom/pm6150.dtsi b/arch/arm64/boot/dts/qcom/pm6150.dtsi index e198ed897b557dc3b50109045e7611491c1800de..087aa21910cef20496cab5afb963124f840994b5 100644 --- a/arch/arm64/boot/dts/qcom/pm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150.dtsi @@ -449,11 +449,15 @@ compatible = "qcom,bcl-v5"; reg = <0x1d00 0x100>; interrupts = <0x0 0x1d 0x0 IRQ_TYPE_NONE>, + <0x0 0x1d 0x1 IRQ_TYPE_NONE>, + <0x0 0x1d 0x0 IRQ_TYPE_NONE>, <0x0 0x1d 0x1 IRQ_TYPE_NONE>, <0x0 0x1d 0x2 IRQ_TYPE_NONE>; - interrupt-names = "bcl-lvl0", - "bcl-lvl1", - "bcl-lvl2"; + interrupt-names = "bcl-ibat-lvl0", + "bcl-ibat-lvl1", + "bcl-vbat-lvl0", + "bcl-vbat-lvl1", + "bcl-vbat-lvl2"; #thermal-sensor-cells = <1>; }; @@ -560,7 +564,7 @@ }; pm6150-ibat-lvl0 { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&pm6150_bcl 0>; @@ -592,7 +596,7 @@ }; pm6150-vbat-lvl0 { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-governor = "low_limits_cap"; thermal-sensors = <&pm6150_bcl 2>; @@ -642,54 +646,6 @@ }; }; - pm6150-bcl-lvl0 { - polling-delay-passive = <100>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&pm6150_bcl 5>; - wake-capable-sensor; - - trips { - bcl_lvl0: bcl-lvl0 { - temperature = <1>; - hysteresis = <1>; - type = "passive"; - }; - }; - }; - - pm6150-bcl-lvl1 { - polling-delay-passive = <100>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&pm6150_bcl 6>; - wake-capable-sensor; - - trips { - bcl_lvl1: bcl-lvl1 { - temperature = <1>; - hysteresis = <1>; - type = "passive"; - }; - }; - }; - - pm6150-bcl-lvl2 { - polling-delay-passive = <100>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&pm6150_bcl 7>; - wake-capable-sensor; - - trips { - bcl_lvl2: bcl-lvl2 { - temperature = <1>; - hysteresis = <1>; - type = "passive"; - }; - }; - }; - soc { polling-delay-passive = <100>; polling-delay = <0>; diff --git a/arch/arm64/boot/dts/qcom/pm6150l.dtsi b/arch/arm64/boot/dts/qcom/pm6150l.dtsi index 8398790f72ec1aa423b0ced93bbdf92afb399e82..64672673a4f92df43b205cc4bb59bf1d12c8848e 100644 --- a/arch/arm64/boot/dts/qcom/pm6150l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150l.dtsi @@ -46,9 +46,9 @@ interrupts = <0x4 0x3d 0x0 IRQ_TYPE_NONE>, <0x4 0x3d 0x1 IRQ_TYPE_NONE>, <0x4 0x3d 0x2 IRQ_TYPE_NONE>; - interrupt-names = "bcl-lvl0", - "bcl-lvl1", - "bcl-lvl2"; + interrupt-names = "bcl-vbat-lvl0", + "bcl-vbat-lvl1", + "bcl-vbat-lvl2"; #thermal-sensor-cells = <1>; }; @@ -120,7 +120,6 @@ <0x4 0xc3 0 IRQ_TYPE_NONE>, <0x4 0xc4 0 IRQ_TYPE_NONE>, <0x4 0xc5 0 IRQ_TYPE_NONE>, - <0x4 0xc6 0 IRQ_TYPE_NONE>, <0x4 0xc7 0 IRQ_TYPE_NONE>, <0x4 0xc8 0 IRQ_TYPE_NONE>, <0x4 0xc9 0 IRQ_TYPE_NONE>, @@ -129,11 +128,12 @@ interrupt-names = "pm6150l_gpio1", "pm6150l_gpio2", "pm6150l_gpio3", "pm6150l_gpio4", "pm6150l_gpio5", "pm6150l_gpio6", - "pm6150l_gpio7", "pm6150l_gpio8", - "pm6150l_gpio9", "pm6150l_gpio10", - "pm6150l_gpio11", "pm6150l_gpio12"; + "pm6150l_gpio8", "pm6150l_gpio9", + "pm6150l_gpio10", "pm6150l_gpio11", + "pm6150l_gpio12"; gpio-controller; #gpio-cells = <2>; + qcom,gpios-disallowed = <7>; }; }; @@ -511,52 +511,4 @@ }; }; }; - - pm6150l-bcl-lvl0 { - polling-delay-passive = <100>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&pm6150l_bcl 5>; - wake-capable-sensor; - - trips { - l_bcl_lvl0: l-bcl-lvl0 { - temperature = <1>; - hysteresis = <1>; - type = "passive"; - }; - }; - }; - - pm6150l-bcl-lvl1 { - polling-delay-passive = <100>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&pm6150l_bcl 6>; - wake-capable-sensor; - - trips { - l_bcl_lvl1: l-bcl-lvl1 { - temperature = <1>; - hysteresis = <1>; - type = "passive"; - }; - }; - }; - - pm6150l-bcl-lvl2 { - polling-delay-passive = <100>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&pm6150l_bcl 7>; - wake-capable-sensor; - - trips { - l_bcl_lvl2: l-bcl-lvl2 { - temperature = <1>; - hysteresis = <1>; - type = "passive"; - }; - }; - }; }; diff --git a/arch/arm64/boot/dts/qcom/pm8150.dtsi b/arch/arm64/boot/dts/qcom/pm8150.dtsi index 4f780f07ecb8d715db9790624ead7985b67ceac7..f1e9dc2f82831f373463da7878b18b311b85e4c0 100644 --- a/arch/arm64/boot/dts/qcom/pm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150.dtsi @@ -96,14 +96,15 @@ <0x0 0xc2 0 IRQ_TYPE_NONE>, <0x0 0xc3 0 IRQ_TYPE_NONE>, <0x0 0xc5 0 IRQ_TYPE_NONE>, + <0x0 0xc6 0 IRQ_TYPE_NONE>, <0x0 0xc8 0 IRQ_TYPE_NONE>, <0x0 0xc9 0 IRQ_TYPE_NONE>; interrupt-names = "pm8150_gpio1", "pm8150_gpio3", "pm8150_gpio4", "pm8150_gpio6", - "pm8150_gpio9", "pm8150_gpio10"; + "pm8150_gpio7","pm8150_gpio9", "pm8150_gpio10"; gpio-controller; #gpio-cells = <2>; - qcom,gpios-disallowed = <2 5 7 8>; + qcom,gpios-disallowed = <2 5 8>; }; pm8150_sdam_2: sdam@b100 { diff --git a/arch/arm64/boot/dts/qcom/pm8150b.dtsi b/arch/arm64/boot/dts/qcom/pm8150b.dtsi index e1ff572b262d5608fc70a5c1e8b8bea9a72edca9..c410e178f2e6e083e71d118487bbf72cfac766d9 100644 --- a/arch/arm64/boot/dts/qcom/pm8150b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150b.dtsi @@ -55,11 +55,6 @@ clock-names = "xo"; }; - pm8150b_pbs1: qcom,pbs@7200 { - compatible = "qcom,qpnp-pbs"; - reg = <0x7200 0x100>; - }; - pm8150b_qnovo: qcom,sdam-qnovo@b000 { compatible = "qcom,qpnp-qnovo5"; reg = <0xb000 0x100>; @@ -365,11 +360,15 @@ compatible = "qcom,bcl-v5"; reg = <0x1d00 0x100>; interrupts = <0x2 0x1d 0x0 IRQ_TYPE_NONE>, + <0x2 0x1d 0x1 IRQ_TYPE_NONE>, + <0x2 0x1d 0x0 IRQ_TYPE_NONE>, <0x2 0x1d 0x1 IRQ_TYPE_NONE>, <0x2 0x1d 0x2 IRQ_TYPE_NONE>; - interrupt-names = "bcl-lvl0", - "bcl-lvl1", - "bcl-lvl2"; + interrupt-names = "bcl-ibat-lvl0", + "bcl-ibat-lvl1", + "bcl-vbat-lvl0", + "bcl-vbat-lvl1", + "bcl-vbat-lvl2"; #thermal-sensor-cells = <1>; }; @@ -383,7 +382,6 @@ #address-cells = <1>; #size-cells = <1>; qcom,pmic-revid = <&pm8150b_revid>; - qcom,pmic-pbs = <&pm8150b_pbs1>; status = "okay"; qcom,fg-batt-soc@4000 { @@ -599,7 +597,7 @@ }; pm8150b-ibat-lvl0 { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&pm8150b_bcl 0>; @@ -615,7 +613,7 @@ }; pm8150b-ibat-lvl1 { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&pm8150b_bcl 1>; @@ -631,7 +629,7 @@ }; pm8150b-vbat-lvl0 { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-governor = "low_limits_cap"; thermal-sensors = <&pm8150b_bcl 2>; @@ -648,7 +646,7 @@ }; pm8150b-vbat-lvl1 { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-governor = "low_limits_cap"; thermal-sensors = <&pm8150b_bcl 3>; @@ -665,7 +663,7 @@ }; pm8150b-vbat-lvl2 { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-governor = "low_limits_cap"; thermal-sensors = <&pm8150b_bcl 4>; @@ -681,56 +679,8 @@ }; }; - pm8150b-bcl-lvl0 { - polling-delay-passive = <100>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&pm8150b_bcl 5>; - wake-capable-sensor; - - trips { - b_bcl_lvl0: b-bcl-lvl0 { - temperature = <1>; - hysteresis = <1>; - type = "passive"; - }; - }; - }; - - pm8150b-bcl-lvl1 { - polling-delay-passive = <100>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&pm8150b_bcl 6>; - wake-capable-sensor; - - trips { - b_bcl_lvl1: b-bcl-lvl1 { - temperature = <1>; - hysteresis = <1>; - type = "passive"; - }; - }; - }; - - pm8150b-bcl-lvl2 { - polling-delay-passive = <100>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&pm8150b_bcl 7>; - wake-capable-sensor; - - trips { - b_bcl_lvl2: b-bcl-lvl2 { - temperature = <1>; - hysteresis = <1>; - type = "passive"; - }; - }; - }; - soc { - polling-delay-passive = <100>; + polling-delay-passive = <1000>; polling-delay = <0>; thermal-governor = "low_limits_cap"; thermal-sensors = <&bcl_soc>; @@ -739,7 +689,12 @@ trips { soc_trip:soc-trip { - temperature = <10>; + temperature = <5>; + hysteresis = <0>; + type = "passive"; + }; + soc_trip2:soc-trip2 { + temperature = <15>; hysteresis = <0>; type = "passive"; }; diff --git a/arch/arm64/boot/dts/qcom/pm8150l.dtsi b/arch/arm64/boot/dts/qcom/pm8150l.dtsi index 3586af695f4f93bef0a041856fa04dcdd87c6d6c..96e20a8df850d7cf26551b480f8ef0cf548770a8 100644 --- a/arch/arm64/boot/dts/qcom/pm8150l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150l.dtsi @@ -117,9 +117,9 @@ interrupts = <0x4 0x3d 0x0 IRQ_TYPE_NONE>, <0x4 0x3d 0x1 IRQ_TYPE_NONE>, <0x4 0x3d 0x2 IRQ_TYPE_NONE>; - interrupt-names = "bcl-lvl0", - "bcl-lvl1", - "bcl-lvl2"; + interrupt-names = "bcl-vbat-lvl0", + "bcl-vbat-lvl1", + "bcl-vbat-lvl2"; #thermal-sensor-cells = <1>; }; @@ -464,7 +464,7 @@ }; pm8150l-vph-lvl0 { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-governor = "low_limits_cap"; thermal-sensors = <&pm8150l_bcl 2>; @@ -481,7 +481,7 @@ }; pm8150l-vph-lvl1 { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-governor = "low_limits_cap"; thermal-sensors = <&pm8150l_bcl 3>; @@ -498,7 +498,7 @@ }; pm8150l-vph-lvl2 { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-governor = "low_limits_cap"; thermal-sensors = <&pm8150l_bcl 4>; @@ -513,52 +513,4 @@ }; }; }; - - pm8150l-bcl-lvl0 { - polling-delay-passive = <100>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&pm8150l_bcl 5>; - wake-capable-sensor; - - trips { - l_bcl_lvl0: l-bcl-lvl0 { - temperature = <1>; - hysteresis = <1>; - type = "passive"; - }; - }; - }; - - pm8150l-bcl-lvl1 { - polling-delay-passive = <100>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&pm8150l_bcl 6>; - wake-capable-sensor; - - trips { - l_bcl_lvl1: l-bcl-lvl1 { - temperature = <1>; - hysteresis = <1>; - type = "passive"; - }; - }; - }; - - pm8150l-bcl-lvl2 { - polling-delay-passive = <100>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&pm8150l_bcl 7>; - wake-capable-sensor; - - trips { - l_bcl_lvl2: l-bcl-lvl2 { - temperature = <1>; - hysteresis = <1>; - type = "passive"; - }; - }; - }; }; diff --git a/arch/arm64/boot/dts/qcom/pmi632.dtsi b/arch/arm64/boot/dts/qcom/pmi632.dtsi index 41ddd00c89e192871dbcb61e3de57bf32acb095c..f97fe75e7fe01979ed2e95ff0c28338d3321de14 100644 --- a/arch/arm64/boot/dts/qcom/pmi632.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi632.dtsi @@ -394,11 +394,15 @@ compatible = "qcom,bcl-v5"; reg = <0x3d00 0x100>; interrupts = <0x2 0x3d 0x0 IRQ_TYPE_NONE>, + <0x2 0x3d 0x1 IRQ_TYPE_NONE>, + <0x2 0x3d 0x0 IRQ_TYPE_NONE>, <0x2 0x3d 0x1 IRQ_TYPE_NONE>, <0x2 0x3d 0x2 IRQ_TYPE_NONE>; - interrupt-names = "bcl-lvl0", - "bcl-lvl1", - "bcl-lvl2"; + interrupt-names = "bcl-ibat-lvl0", + "bcl-ibat-lvl1", + "bcl-vbat-lvl0", + "bcl-vbat-lvl1", + "bcl-vbat-lvl2"; qcom,ibat-use-qg-adc-5a; #thermal-sensor-cells = <1>; }; @@ -632,7 +636,7 @@ }; pmi632-ibat-lvl0 { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&bcl_sensor 0>; @@ -648,7 +652,7 @@ }; pmi632-ibat-lvl1 { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&bcl_sensor 1>; @@ -664,7 +668,7 @@ }; pmi632-vbat-lvl0 { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-governor = "low_limits_cap"; thermal-sensors = <&bcl_sensor 2>; @@ -681,7 +685,7 @@ }; pmi632-vbat-lvl1 { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-governor = "low_limits_cap"; thermal-sensors = <&bcl_sensor 3>; @@ -698,7 +702,7 @@ }; pmi632-vbat-lvl2 { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-governor = "low_limits_cap"; thermal-sensors = <&bcl_sensor 4>; @@ -714,54 +718,6 @@ }; }; - pmi632-bcl-lvl0 { - polling-delay-passive = <100>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&bcl_sensor 5>; - wake-capable-sensor; - - trips { - bcl_lvl0: bcl-lvl0 { - temperature = <1>; - hysteresis = <1>; - type = "passive"; - }; - }; - }; - - pmi632-bcl-lvl1 { - polling-delay-passive = <100>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&bcl_sensor 6>; - wake-capable-sensor; - - trips { - bcl_lvl1: bcl-lvl1 { - temperature = <1>; - hysteresis = <1>; - type = "passive"; - }; - }; - }; - - pmi632-bcl-lvl2 { - polling-delay-passive = <100>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&bcl_sensor 7>; - wake-capable-sensor; - - trips { - bcl_lvl2: bcl-lvl2 { - temperature = <1>; - hysteresis = <1>; - type = "passive"; - }; - }; - }; - soc { polling-delay-passive = <100>; polling-delay = <0>; diff --git a/arch/arm64/boot/dts/qcom/qcs401.dtsi b/arch/arm64/boot/dts/qcom/qcs401.dtsi index 06387ed9e2e36e92a1501349e5e653a6ad059a62..abf0c5893a2b0948998d66a7d9e1950a075895f6 100644 --- a/arch/arm64/boot/dts/qcom/qcs401.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs401.dtsi @@ -11,7 +11,7 @@ * GNU General Public License for more details. */ -#include "qcs403.dtsi" +#include "qcs405.dtsi" / { model = "Qualcomm Technologies, Inc. QCS401"; @@ -20,5 +20,29 @@ }; &soc { - /delete-node/ qcom,turing@800000; + /delete-node/ qcom,msm-cpufreq; + + msm_cpufreq: qcom,msm-cpufreq { + compatible = "qcom,msm-cpufreq"; + clock-names = "cpu0_clk"; + clocks = <&clock_cpu APCS_MUX_CLK>; + + qcom,cpufreq-table = + < 1094400 >, + < 1248000 >, + < 1401600 >; + }; + + /delete-node/ qcom,cpu0-computemon; + + cpu0_computemon: qcom,cpu0-computemon { + compatible = "qcom,arm-cpu-mon"; + qcom,cpulist = <&CPU0 &CPU1>; + qcom,target-dev = <&cpu0_cpu_ddr_latfloor>; + qcom,core-dev-table = + < 1094400 MHZ_TO_MBPS( 297, 8) >, + < 1248000 MHZ_TO_MBPS( 597, 8) >, + < 1401600 MHZ_TO_MBPS( 710, 8) >; + }; }; + diff --git a/arch/arm64/boot/dts/qcom/qcs403-iot-sku1.dts b/arch/arm64/boot/dts/qcom/qcs403-iot-sku1.dts index 34de78d0baf63603059aba229f17836d3289ceea..bcf65cf5aa3e94b7554c98887bc028dda27b06db 100644 --- a/arch/arm64/boot/dts/qcom/qcs403-iot-sku1.dts +++ b/arch/arm64/boot/dts/qcom/qcs403-iot-sku1.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -22,6 +22,61 @@ compatible = "qcom,qcs403-iot", "qcom,qcs403", "qcom,iot"; qcom,board-id = <0x010020 0x3>; + cpus { + /delete-node/ cpu@102; + /delete-node/ cpu@103; + + cpu-map { + cluster0 { + /delete-node/ core2; + /delete-node/ core3; + }; + }; + }; +}; + +&soc { + cpuss_dump { + /delete-node/ qcom,l1_i_cache102; + /delete-node/ qcom,l1_i_cache103; + /delete-node/ qcom,l1_d_cache102; + /delete-node/ qcom,l1_d_cache103; + }; + + qcom,spm@b012000 { + qcom,cpu-vctl-list = <&CPU0 &CPU1>; + }; + + qcom,lpm-levels { + qcom,pm-cluster@0{ + qcom,pm-cpu { + qcom,cpu = <&CPU0 &CPU1>; + }; + }; + }; + + /delete-node/ cti@61ba000; + /delete-node/ cti@61bb000; + /delete-node/ etm@61be000; + /delete-node/ etm@61bf000; + funnel@61a1000 { + ports { + /delete-node/ port@3; + /delete-node/ port@4; + }; + }; +}; + +&thermal_zones { + cpuss-max-step { + cooling-maps { + /delete-node/ cpu2_cdev; + /delete-node/ cpu3_cdev; + }; + }; + + /delete-node/ cpuss-2-step; + /delete-node/ cpuss-3-step; }; &qnand_1 { diff --git a/arch/arm64/boot/dts/qcom/qcs403-iot-sku2.dts b/arch/arm64/boot/dts/qcom/qcs403-iot-sku2.dts index c782e1d43ca48d6845ac06ada852f6b4e73a7069..4220f8e48ef5517024aff632b9d44400a97245dc 100644 --- a/arch/arm64/boot/dts/qcom/qcs403-iot-sku2.dts +++ b/arch/arm64/boot/dts/qcom/qcs403-iot-sku2.dts @@ -22,6 +22,61 @@ compatible = "qcom,qcs403-iot", "qcom,qcs403", "qcom,iot"; qcom,board-id = <0x010015 0x0>; + cpus { + /delete-node/ cpu@102; + /delete-node/ cpu@103; + + cpu-map { + cluster0 { + /delete-node/ core2; + /delete-node/ core3; + }; + }; + }; +}; + +&soc { + cpuss_dump { + /delete-node/ qcom,l1_i_cache102; + /delete-node/ qcom,l1_i_cache103; + /delete-node/ qcom,l1_d_cache102; + /delete-node/ qcom,l1_d_cache103; + }; + + qcom,spm@b012000 { + qcom,cpu-vctl-list = <&CPU0 &CPU1>; + }; + + qcom,lpm-levels { + qcom,pm-cluster@0{ + qcom,pm-cpu { + qcom,cpu = <&CPU0 &CPU1>; + }; + }; + }; + + /delete-node/ cti@61ba000; + /delete-node/ cti@61bb000; + /delete-node/ etm@61be000; + /delete-node/ etm@61bf000; + funnel@61a1000 { + ports { + /delete-node/ port@3; + /delete-node/ port@4; + }; + }; +}; + +&thermal_zones { + cpuss-max-step { + cooling-maps { + /delete-node/ cpu2_cdev; + /delete-node/ cpu3_cdev; + }; + }; + + /delete-node/ cpuss-2-step; + /delete-node/ cpuss-3-step; }; #include "qcs405-mdss-panels.dtsi" diff --git a/arch/arm64/boot/dts/qcom/qcs403-iot-sku3.dts b/arch/arm64/boot/dts/qcom/qcs403-iot-sku3.dts index 7497da5aad38bd95af18ff016118a0cfba63ab62..637d94ce2e505441fc42a4360b7c3e1aa0a7b19f 100644 --- a/arch/arm64/boot/dts/qcom/qcs403-iot-sku3.dts +++ b/arch/arm64/boot/dts/qcom/qcs403-iot-sku3.dts @@ -22,9 +22,50 @@ compatible = "qcom,qcs403-iot", "qcom,qcs403", "qcom,iot"; qcom,board-id = <0x010020 0x4>; + cpus { + /delete-node/ cpu@102; + /delete-node/ cpu@103; + + cpu-map { + cluster0 { + /delete-node/ core2; + /delete-node/ core3; + }; + }; + }; }; &soc { + cpuss_dump { + /delete-node/ qcom,l1_i_cache102; + /delete-node/ qcom,l1_i_cache103; + /delete-node/ qcom,l1_d_cache102; + /delete-node/ qcom,l1_d_cache103; + }; + + qcom,spm@b012000 { + qcom,cpu-vctl-list = <&CPU0 &CPU1>; + }; + + qcom,lpm-levels { + qcom,pm-cluster@0{ + qcom,pm-cpu { + qcom,cpu = <&CPU0 &CPU1>; + }; + }; + }; + + /delete-node/ cti@61ba000; + /delete-node/ cti@61bb000; + /delete-node/ etm@61be000; + /delete-node/ etm@61bf000; + funnel@61a1000 { + ports { + /delete-node/ port@3; + /delete-node/ port@4; + }; + }; + spi@78b5000 { status = "ok"; spi@0 { @@ -41,6 +82,18 @@ }; }; +&thermal_zones { + cpuss-max-step { + cooling-maps { + /delete-node/ cpu2_cdev; + /delete-node/ cpu3_cdev; + }; + }; + + /delete-node/ cpuss-2-step; + /delete-node/ cpuss-3-step; +}; + &qnand_1 { status = "ok"; }; diff --git a/arch/arm64/boot/dts/qcom/qcs403-iot-sku4.dts b/arch/arm64/boot/dts/qcom/qcs403-iot-sku4.dts index bbc81eb229edd906521b2e04cf6676c996bd8142..77ac0f29bb32457f6fd477e4e589094130b8ab65 100644 --- a/arch/arm64/boot/dts/qcom/qcs403-iot-sku4.dts +++ b/arch/arm64/boot/dts/qcom/qcs403-iot-sku4.dts @@ -22,9 +22,50 @@ compatible = "qcom,qcs403-iot", "qcom,qcs403", "qcom,iot"; qcom,board-id = <0x010020 0x5>; + cpus { + /delete-node/ cpu@102; + /delete-node/ cpu@103; + + cpu-map { + cluster0 { + /delete-node/ core2; + /delete-node/ core3; + }; + }; + }; }; &soc { + cpuss_dump { + /delete-node/ qcom,l1_i_cache102; + /delete-node/ qcom,l1_i_cache103; + /delete-node/ qcom,l1_d_cache102; + /delete-node/ qcom,l1_d_cache103; + }; + + qcom,spm@b012000 { + qcom,cpu-vctl-list = <&CPU0 &CPU1>; + }; + + qcom,lpm-levels { + qcom,pm-cluster@0{ + qcom,pm-cpu { + qcom,cpu = <&CPU0 &CPU1>; + }; + }; + }; + + /delete-node/ cti@61ba000; + /delete-node/ cti@61bb000; + /delete-node/ etm@61be000; + /delete-node/ etm@61bf000; + funnel@61a1000 { + ports { + /delete-node/ port@3; + /delete-node/ port@4; + }; + }; + gpio_keys { vol_mute { gpios = <&tlmm 19 GPIO_ACTIVE_LOW>; @@ -32,6 +73,18 @@ }; }; +&thermal_zones { + cpuss-max-step { + cooling-maps { + /delete-node/ cpu2_cdev; + /delete-node/ cpu3_cdev; + }; + }; + + /delete-node/ cpuss-2-step; + /delete-node/ cpuss-3-step; +}; + &qnand_1 { status = "ok"; }; diff --git a/arch/arm64/boot/dts/qcom/qcs403.dtsi b/arch/arm64/boot/dts/qcom/qcs403.dtsi index 70f1c135f7db0b83162d38a4ad70d8b5f4cc5e4a..c5058cbaec53a2d25ed63db85be5fc89badfebe5 100644 --- a/arch/arm64/boot/dts/qcom/qcs403.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs403.dtsi @@ -17,48 +17,20 @@ model = "Qualcomm Technologies, Inc. QCS403"; qcom,msm-name = "QCS403"; qcom,msm-id = <373 0x0>; - - cpus { - /delete-node/ cpu@102; - /delete-node/ cpu@103; - cpu-map { - cluster0 { - /delete-node/ core2; - /delete-node/ core3; - }; - }; - }; - }; &soc { + /delete-node/ qcom,msm-cpufreq; - cpuss_dump { - /delete-node/ qcom,l1_i_cache102; - /delete-node/ qcom,l1_i_cache103; - /delete-node/ qcom,l1_d_cache102; - /delete-node/ qcom,l1_d_cache103; - }; - qcom,spm@b012000 { - qcom,cpu-vctl-list = <&CPU0 &CPU1>; - }; - qcom,lpm-levels { - qcom,pm-cluster@0{ - qcom,pm-cpu { - qcom,cpu = <&CPU0 &CPU1>; - }; - }; - }; - /delete-node/ cti@61ba000; - /delete-node/ cti@61bb000; - /delete-node/ etm@61be000; - /delete-node/ etm@61bf000; + msm_cpufreq: qcom,msm-cpufreq { + compatible = "qcom,msm-cpufreq"; + clock-names = "cpu0_clk"; + clocks = <&clock_cpu APCS_MUX_CLK>; - funnel@61a1000 { - ports { - /delete-node/ port@3; - /delete-node/ port@4; - }; + qcom,cpufreq-table = + < 1094400 >, + < 1248000 >, + < 1401600 >; }; /delete-node/ qcom,cpu0-computemon; @@ -74,17 +46,6 @@ }; }; -&thermal_zones { - cpuss-max-step { - cooling-maps { - /delete-node/ cpu2_cdev; - /delete-node/ cpu3_cdev; - }; - }; - /delete-node/ cpuss-2-step; - /delete-node/ cpuss-3-step; -}; - &adsp_fw_mem { reg = <0x0 0x87400000 0x0 0x1200000>; }; diff --git a/arch/arm64/boot/dts/qcom/qcs405-linear-pca9956.dtsi b/arch/arm64/boot/dts/qcom/qcs405-linear-pca9956.dtsi index 6980899b38bafa3659a0cb968c8d0c1fa925642a..aa18e3b0ddd7de195f790d403533cf3000460088 100644 --- a/arch/arm64/boot/dts/qcom/qcs405-linear-pca9956.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs405-linear-pca9956.dtsi @@ -11,6 +11,10 @@ * GNU General Public License for more details. */ +&va_macro { + qcom,va-dmic-sample-rate = <2400000>; +}; + &i2c_2 { status = "ok"; qcom,clk-freq-out = <100000>; diff --git a/arch/arm64/boot/dts/qcom/qcs405-mhi.dtsi b/arch/arm64/boot/dts/qcom/qcs405-mhi.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..12ba814820f32f706e933450ea8cf675a3b6f313 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs405-mhi.dtsi @@ -0,0 +1,716 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&pcie_rc0 { + reg = <0 0 0 0 0>; + + mhi_0: qcom,mhi@0 { + reg = <0 0 0 0 0 >; + + pci-ids = "17cb:0304"; + + /* controller specific configuration */ + qcom,smmu-cfg = <0x0>; + qcom,msm-bus,name = "mhi"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <45 512 0 0>, + <45 512 1200000000 650000000>; + + /* mhi bus specific settings */ + mhi,max-channels = <110>; + mhi,timeout = <2000>; + + mhi_channels { + #address-cells = <1>; + #size-cells = <0>; + mhi_chan@0 { + reg = <0>; + label = "LOOPBACK"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@1 { + reg = <1>; + label = "LOOPBACK"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@4 { + reg = <4>; + label = "DIAG"; + mhi,num-elements = <64>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@5 { + reg = <5>; + label = "DIAG"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@14 { + reg = <14>; + label = "QMI0"; + mhi,num-elements = <64>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@15 { + reg = <15>; + label = "QMI0"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@16 { + reg = <16>; + label = "QMI1"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@17 { + reg = <17>; + label = "QMI1"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@20 { + reg = <20>; + label = "IPCR"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + mhi,auto-start; + }; + + mhi_chan@21 { + reg = <21>; + label = "IPCR"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + mhi,auto-queue; + mhi,auto-start; + }; + + mhi_chan@32 { + reg = <32>; + label = "DUN"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@33 { + reg = <33>; + label = "DUN"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@46 { + reg = <46>; + label = "IP_SW_0"; + mhi,num-elements = <512>; + mhi,event-ring = <4>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@47 { + reg = <47>; + label = "IP_SW_0"; + mhi,num-elements = <512>; + mhi,event-ring = <5>; + mhi,chan-dir = <2>; + mhi,data-type = <4>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@100 { + reg = <100>; + label = "IP_HW0"; + mhi,num-elements = <512>; + mhi,event-ring = <6>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <3>; + mhi,ee = <0x4>; + mhi,db-mode-switch; + }; + + mhi_chan@101 { + reg = <101>; + label = "IP_HW0"; + mhi,num-elements = <512>; + mhi,event-ring = <7>; + mhi,chan-dir = <2>; + mhi,data-type = <4>; + mhi,doorbell-mode = <3>; + mhi,ee = <0x4>; + }; + + mhi_chan@105 { + reg = <105>; + label = "IP_HW1"; + mhi,num-elements = <512>; + mhi,event-ring = <8>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@106 { + reg = <106>; + label = "IP_HW1"; + mhi,num-elements = <512>; + mhi,event-ring = <9>; + mhi,chan-dir = <2>; + mhi,data-type = <4>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + }; + + mhi_events { + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <1>; + mhi,msi = <1>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@2 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <3>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@3 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <4>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@4 { + mhi,num-elements = <1024>; + mhi,intmod = <5>; + mhi,msi = <5>; + mhi,chan = <46>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@5 { + mhi,num-elements = <1024>; + mhi,intmod = <5>; + mhi,msi = <6>; + mhi,chan = <47>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,client-manage; + }; + + mhi_event@6 { + mhi,num-elements = <1024>; + mhi,intmod = <5>; + mhi,msi = <5>; + mhi,chan = <100>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + }; + + mhi_event@7 { + mhi,num-elements = <1024>; + mhi,intmod = <5>; + mhi,msi = <6>; + mhi,chan = <101>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + mhi,client-manage; + }; + + mhi_event@8 { + mhi,num-elements = <1024>; + mhi,intmod = <0>; + mhi,msi = <7>; + mhi,chan = <105>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,hw-ev; + }; + + mhi_event@9 { + mhi,num-elements = <1024>; + mhi,intmod = <0>; + mhi,msi = <8>; + mhi,chan = <106>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,hw-ev; + mhi,client-manage; + }; + }; + + mhi_devices { + #address-cells = <1>; + #size-cells = <0>; + mhi_netdev_0: mhi_rmnet@0 { + reg = <0x0>; + mhi,chan = "IP_HW0"; + mhi,interface-name = "rmnet_mhi"; + mhi,mru = <0x8000>; + mhi,disable-chain-skb; + }; + + mhi_netdev_1: mhi_rmnet@1 { + reg = <0x1>; + mhi,chan = "IP_HW1"; + mhi,interface-name = "rmnet_mhi"; + mhi,mru = <0x8000>; + mhi,disable-chain-skb; + }; + + mhi_netdev_2: mhi_rmnet@2 { + reg = <0x2>; + mhi,chan = "IP_SW_0"; + mhi,interface-name = "mhi_swip"; + mhi,mru = <0x4000>; + mhi,ethernet-interface; + mhi,disable-chain-skb; + }; + }; + }; + + mhi_1: qcom,mhi@1 { + reg = <0 0 0 0 0 >; + + pci-ids = "17cb:0306"; + + /* controller specific configuration */ + qcom,smmu-cfg = <0x0>; + qcom,msm-bus,name = "mhi"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <45 512 0 0>, + <45 512 1200000000 650000000>; + + /* mhi bus specific settings */ + mhi,max-channels = <110>; + mhi,timeout = <2000>; + + mhi_channels { + #address-cells = <1>; + #size-cells = <0>; + mhi_chan@0 { + reg = <0>; + label = "LOOPBACK"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@1 { + reg = <1>; + label = "LOOPBACK"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@4 { + reg = <4>; + label = "DIAG"; + mhi,num-elements = <64>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@5 { + reg = <5>; + label = "DIAG"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@14 { + reg = <14>; + label = "QMI0"; + mhi,num-elements = <64>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@15 { + reg = <15>; + label = "QMI0"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@16 { + reg = <16>; + label = "QMI1"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@17 { + reg = <17>; + label = "QMI1"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@20 { + reg = <20>; + label = "IPCR"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + mhi,auto-start; + }; + + mhi_chan@21 { + reg = <21>; + label = "IPCR"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + mhi,auto-queue; + mhi,auto-start; + }; + + mhi_chan@32 { + reg = <32>; + label = "DUN"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@33 { + reg = <33>; + label = "DUN"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@46 { + reg = <46>; + label = "IP_SW_0"; + mhi,num-elements = <512>; + mhi,event-ring = <4>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@47 { + reg = <47>; + label = "IP_SW_0"; + mhi,num-elements = <512>; + mhi,event-ring = <5>; + mhi,chan-dir = <2>; + mhi,data-type = <4>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@100 { + reg = <100>; + label = "IP_HW0"; + mhi,num-elements = <512>; + mhi,event-ring = <6>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <3>; + mhi,ee = <0x4>; + mhi,db-mode-switch; + }; + + mhi_chan@101 { + reg = <101>; + label = "IP_HW0"; + mhi,num-elements = <512>; + mhi,event-ring = <7>; + mhi,chan-dir = <2>; + mhi,data-type = <4>; + mhi,doorbell-mode = <3>; + mhi,ee = <0x4>; + }; + + mhi_chan@105 { + reg = <105>; + label = "IP_HW1"; + mhi,num-elements = <512>; + mhi,event-ring = <8>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@106 { + reg = <106>; + label = "IP_HW1"; + mhi,num-elements = <512>; + mhi,event-ring = <9>; + mhi,chan-dir = <2>; + mhi,data-type = <4>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + }; + + mhi_events { + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <1>; + mhi,msi = <1>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@2 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <3>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@3 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <4>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@4 { + mhi,num-elements = <1024>; + mhi,intmod = <5>; + mhi,msi = <5>; + mhi,chan = <46>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@5 { + mhi,num-elements = <1024>; + mhi,intmod = <5>; + mhi,msi = <6>; + mhi,chan = <47>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,client-manage; + }; + + mhi_event@6 { + mhi,num-elements = <1024>; + mhi,intmod = <5>; + mhi,msi = <5>; + mhi,chan = <100>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + }; + + mhi_event@7 { + mhi,num-elements = <1024>; + mhi,intmod = <5>; + mhi,msi = <6>; + mhi,chan = <101>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + mhi,client-manage; + }; + + mhi_event@8 { + mhi,num-elements = <1024>; + mhi,intmod = <0>; + mhi,msi = <7>; + mhi,chan = <105>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,hw-ev; + }; + + mhi_event@9 { + mhi,num-elements = <1024>; + mhi,intmod = <0>; + mhi,msi = <8>; + mhi,chan = <106>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,hw-ev; + mhi,client-manage; + }; + }; + + mhi_devices { + #address-cells = <1>; + #size-cells = <0>; + mhi_netdev_3: mhi_rmnet@0 { + reg = <0x0>; + mhi,chan = "IP_HW0"; + mhi,interface-name = "rmnet_mhi"; + mhi,mru = <0x8000>; + mhi,disable-chain-skb; + }; + + mhi_netdev_4: mhi_rmnet@1 { + reg = <0x1>; + mhi,chan = "IP_HW1"; + mhi,interface-name = "rmnet_mhi"; + mhi,mru = <0x8000>; + mhi,disable-chain-skb; + }; + + mhi_netdev_5: mhi_rmnet@2 { + reg = <0x2>; + mhi,chan = "IP_SW_0"; + mhi,interface-name = "mhi_swip"; + mhi,mru = <0x4000>; + mhi,ethernet-interface; + mhi,disable-chain-skb; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/qcs405-pcie.dtsi b/arch/arm64/boot/dts/qcom/qcs405-pcie.dtsi index 9c5d1d796a7cd6baffb19b35141f7b29576fb2e4..7ead59ebba67fbe45af1e2acaf029ddbb20b1682 100644 --- a/arch/arm64/boot/dts/qcom/qcs405-pcie.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs405-pcie.dtsi @@ -81,10 +81,13 @@ qcom,phy-status-offset = <0x3c>; qcom,phy-status-bit = <0>; qcom,phy-power-down-offset = <0x98>; - qcom,core-preset = <0x77777777>; - qcom,boot-option = <0x1>; + qcom,boot-option = <0x0>; qcom,keep-powerdown-phy; + qcom,no-l0s-supported; + qcom,no-l1-supported; + qcom,no-l1ss-supported; + qcom,no-aux-clk-sync; linux,pci-domain = <0>; diff --git a/arch/arm64/boot/dts/qcom/qcs405-va-bolero.dtsi b/arch/arm64/boot/dts/qcom/qcs405-va-bolero.dtsi index 7b5fa64c4e441b3e3c6749abc8efab0eb860b060..766714c24e6fc23550be0ead14fcc17b9b1e4f44 100644 --- a/arch/arm64/boot/dts/qcom/qcs405-va-bolero.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs405-va-bolero.dtsi @@ -19,7 +19,7 @@ va-vdd-micb-supply = <&pms405_l7>; qcom,va-vdd-micb-voltage = <1800000 1800000>; qcom,va-vdd-micb-current = <9000>; - qcom,va-dmic-sample-rate = <2400000>; + qcom,va-dmic-sample-rate = <600000>; }; }; diff --git a/arch/arm64/boot/dts/qcom/qcs405.dtsi b/arch/arm64/boot/dts/qcom/qcs405.dtsi index c58da349d3b346de041fd04fd87bd6f66e0f75f3..a669dcfc8f583016a69d7eb1c385206558466d7d 100644 --- a/arch/arm64/boot/dts/qcom/qcs405.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs405.dtsi @@ -139,6 +139,13 @@ sdhc2 = &sdhc_2; /* SDC2 SD Card slot */ qpic_nand1 = &qnand_1; pci-domain0 = &pcie0; /* PCIe0 domain */ + mhi0 = &mhi_0; + mhi_netdev0 = &mhi_netdev_0; + mhi_netdev1 = &mhi_netdev_1; + mhi_netdev2 = &mhi_netdev_2; + mhi_netdev3 = &mhi_netdev_3; + mhi_netdev4 = &mhi_netdev_4; + mhi_netdev5 = &mhi_netdev_5; }; soc: soc { }; @@ -1562,6 +1569,7 @@ #include "qcs405-coresight.dtsi" #include "qcs405-usb.dtsi" #include "qcs405-pcie.dtsi" +#include "qcs405-mhi.dtsi" &i2c_5 { smb1351_otg_supply: smb1351-charger@55 { diff --git a/arch/arm64/boot/dts/qcom/quin-vm-common.dtsi b/arch/arm64/boot/dts/qcom/quin-vm-common.dtsi index bbe8e8e6f225778d88006d3147585d1627cf3a4e..3d353aa5dfcac2b3933292c0d0738a0ea49845e2 100644 --- a/arch/arm64/boot/dts/qcom/quin-vm-common.dtsi +++ b/arch/arm64/boot/dts/qcom/quin-vm-common.dtsi @@ -248,26 +248,4 @@ compatible = "qcom,vm-restart"; status = "ok"; }; - - spmi_bus: qcom,spmi { - compatible = "qcom,viospmi-pmic-arb"; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - cell-index = <0>; - }; - - viospmi: virtio-spmi@1c800000 { - compatible = "virtio,mmio"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x1c800000 0x1100>; - interrupts = ; - status = "okay"; - }; }; diff --git a/arch/arm64/boot/dts/qcom/sa515m-ccard-pcie-ep.dts b/arch/arm64/boot/dts/qcom/sa515m-ccard-pcie-ep.dts index 0d95e1540cf402b9560638ecabbdc7874dc16578..7bd092eebb5ccc5b0bb2e5e7b8f70137152939e5 100644 --- a/arch/arm64/boot/dts/qcom/sa515m-ccard-pcie-ep.dts +++ b/arch/arm64/boot/dts/qcom/sa515m-ccard-pcie-ep.dts @@ -44,7 +44,3 @@ &mhi_device { status = "ok"; }; - -&mhi_net_device { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/qcom/sa515m-ccard.dtsi b/arch/arm64/boot/dts/qcom/sa515m-ccard.dtsi index ee1e7cc77def16cff5edd14c8628148868352cc7..6eb3f9aa57b715673086b9de05455d45013c238c 100644 --- a/arch/arm64/boot/dts/qcom/sa515m-ccard.dtsi +++ b/arch/arm64/boot/dts/qcom/sa515m-ccard.dtsi @@ -23,59 +23,6 @@ gpio = <&tlmm 23 GPIO_ACTIVE_HIGH>; enable-active-high; }; - - snd_tlv3x: sound-auto { - compatible = "qcom,sdx-asoc-snd-auto"; - qcom,model = "sdx-auto-i2s-snd-card"; - qcom,prim_mi2s_aux_master = <&prim_master>; - qcom,prim_mi2s_aux_slave = <&prim_slave>; - qcom,sec_mi2s_aux_master = <&sec_master>; - qcom,sec_mi2s_aux_slave = <&sec_slave>; - - pinctrl-names = "default"; - pinctrl-0 = <&a2b_cdc_sel_default>, <&i2s_mclk_active>; - - asoc-platform = <&pcm0>, <&pcm1>, <&voip>, <&voice>, - <&loopback>, <&hostless>, <&afe>, <&routing>, - <&pcm_dtmf>, <&host_pcm>, <&compress>; - asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", - "msm-voip-dsp", "msm-pcm-voice", - "msm-pcm-loopback", "msm-pcm-hostless", - "msm-pcm-afe", "msm-pcm-routing", - "msm-pcm-dtmf", "msm-voice-host-pcm", - "msm-compress-dsp"; - asoc-cpu = <&dai_pri_auxpcm>, <&mi2s_prim>, <&mi2s_sec>, - <&dtmf_tx>, - <&rx_capture_tx>, <&rx_playback_rx>, - <&tx_capture_tx>, <&tx_playback_rx>, - <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, - <&afe_proxy_tx>, <&incall_record_rx>, - <&incall_record_tx>, <&incall_music_rx>, - <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>, - <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>, - <&dai_sec_auxpcm>; - asoc-cpu-names = "msm-dai-q6-auxpcm.1", - "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", - "msm-dai-stub-dev.4", "msm-dai-stub-dev.5", - "msm-dai-stub-dev.6", "msm-dai-stub-dev.7", - "msm-dai-stub-dev.8", "msm-dai-q6-dev.224", - "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", - "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", - "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", - "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", - "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", - "msm-dai-q6-auxpcm.2"; - asoc-codec = <&tlv320aic3x_codec>, <&stub_codec>; - asoc-codec-names = "tlv320aic3x-codec", "msm-stub-codec.1"; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; }; /* delete pm8150b nodes */ @@ -87,9 +34,6 @@ /delete-node/ pm8150b-vbat-lvl0; /delete-node/ pm8150b-vbat-lvl1; /delete-node/ pm8150b-vbat-lvl2; - /delete-node/ pm8150b-bcl-lvl0; - /delete-node/ pm8150b-bcl-lvl1; - /delete-node/ pm8150b-bcl-lvl2; /delete-node/ soc; }; @@ -116,6 +60,10 @@ status = "okay"; }; +&blsp1_uart4a_hs { + status = "okay"; +}; + &vbus_detect { status = "okay"; }; @@ -151,7 +99,7 @@ interrupts = <88 0>; spi-max-frequency = <5000000>; qcom,clk-freq-mhz = <40000000>; - qcom,max-can-channels = <2>; + qcom,max-can-channels = <1>; qcom,bits-per-word = <8>; qcom,support-can-fd; }; @@ -165,13 +113,6 @@ reset-inverted; AVDD-supply = <&codec_vreg>; IOVDD-supply = <&codec_vreg>; - ai3x-ocmv = <1>; - }; - - eeprom@52 { - compatible = "atmel,24c128"; - reg = <0x52>; - pagesize = <32>; }; }; @@ -183,21 +124,9 @@ /delete-property/ vreg_rgmii-supply; pinctrl-names = "default"; pinctrl-0 = <&vreg_rgmii_off_default>; - qcom,phy-reset-delay-msecs = <10>; }; &vreg_rgmii_io_pads { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - -&cnss_qca6390 { - vdd-wlan-ctrl1-supply = <&vreg_conn_pa>; - vdd-wlan-aon-supply = <&pmxprairie_s3>; - vdd-wlan-rfa1-supply = <&pmxprairie_s2>; - vdd-wlan-rfa3-supply = <&pmxprairie_s4>; - qcom,vdd-wlan-ctrl1-info = <0 0 0 0>; - qcom,vdd-wlan-aon-info = <950000 950000 0 0>; - qcom,vdd-wlan-rfa1-info = <1350000 1350000 0 0>; - qcom,vdd-wlan-rfa3-info = <1904000 1904000 450000 0>; -}; diff --git a/arch/arm64/boot/dts/qcom/sa6155-adp-air.dtsi b/arch/arm64/boot/dts/qcom/sa6155-adp-air.dtsi index e86b8deb8f5764c6d3e69632ead18eabc783fed2..61a1491c3e6e66697371fd1dcb59e483083aafe5 100644 --- a/arch/arm64/boot/dts/qcom/sa6155-adp-air.dtsi +++ b/arch/arm64/boot/dts/qcom/sa6155-adp-air.dtsi @@ -51,7 +51,7 @@ }; hsi2s: qcom,hsi2s { - compatible = "qcom,sa6155-hsi2s", "qcom,hsi2s"; + compatible = "qcom,hsi2s"; number-of-interfaces = <2>; reg = <0x1B40000 0x28000>; reg-names = "lpa_if"; @@ -64,8 +64,6 @@ clock-names = "core_clk", "wr0_mem_clk", "wr1_mem_clk", "wr2_mem_clk", "csr_hclk"; - bit-clock-hz = <20000000>; - interrupt-interval-ms = <10>; sdr0: qcom,hs0_i2s { compatible = "qcom,hsi2s-interface"; diff --git a/arch/arm64/boot/dts/qcom/sa6155-adp-star.dtsi b/arch/arm64/boot/dts/qcom/sa6155-adp-star.dtsi index be1b682abcfc64792e49de992dbc1770d4591f8b..78c3bce754e6cc79e00406f12e2f1874d7adcbca 100644 --- a/arch/arm64/boot/dts/qcom/sa6155-adp-star.dtsi +++ b/arch/arm64/boot/dts/qcom/sa6155-adp-star.dtsi @@ -44,7 +44,7 @@ }; hsi2s: qcom,hsi2s { - compatible = "qcom,sa6155-hsi2s", "qcom,hsi2s"; + compatible = "qcom,hsi2s"; number-of-interfaces = <2>; reg = <0x1B40000 0x28000>; reg-names = "lpa_if"; @@ -57,8 +57,6 @@ clock-names = "core_clk", "wr0_mem_clk", "wr1_mem_clk", "wr2_mem_clk", "csr_hclk"; - bit-clock-hz = <20000000>; - interrupt-interval-ms = <10>; sdr0: qcom,hs0_i2s { compatible = "qcom,hsi2s-interface"; diff --git a/arch/arm64/boot/dts/qcom/sa6155-pcie.dtsi b/arch/arm64/boot/dts/qcom/sa6155-pcie.dtsi index c0c9ac316e4d45cc7ed748ac77a9bf2d74256d7d..d22818a1f4599b4275e3b6a0e03833ad11570737 100644 --- a/arch/arm64/boot/dts/qcom/sa6155-pcie.dtsi +++ b/arch/arm64/boot/dts/qcom/sa6155-pcie.dtsi @@ -151,7 +151,6 @@ qcom,phy-status-offset = <0x974>; qcom,phy-status-bit = <6>; qcom,phy-power-down-offset = <0x804>; - qcom,core-preset = <0x77777777>; qcom,boot-option = <0x1>; diff --git a/arch/arm64/boot/dts/qcom/sa6155-pmic.dtsi b/arch/arm64/boot/dts/qcom/sa6155-pmic.dtsi index 737ab8022869e31142224809edc17fb66dc2b1b0..3e00782bcd6827f6ac629770a92e41da610352bd 100644 --- a/arch/arm64/boot/dts/qcom/sa6155-pmic.dtsi +++ b/arch/arm64/boot/dts/qcom/sa6155-pmic.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -137,15 +137,9 @@ /delete-node/ pm6150-vbat-lvl0; /delete-node/ pm6150-vbat-lvl1; /delete-node/ pm6150-vbat-lvl2; - /delete-node/ pm6150-bcl-lvl0; - /delete-node/ pm6150-bcl-lvl1; - /delete-node/ pm6150-bcl-lvl2; /delete-node/ pm6150l-vph-lvl0; /delete-node/ pm6150l-vph-lvl1; /delete-node/ pm6150l-vph-lvl2; - /delete-node/ pm6150l-bcl-lvl0; - /delete-node/ pm6150l-bcl-lvl1; - /delete-node/ pm6150l-bcl-lvl2; /delete-node/ xo-therm; /delete-node/ sdm-therm; /delete-node/ conn-therm; diff --git a/arch/arm64/boot/dts/qcom/sa6155.dtsi b/arch/arm64/boot/dts/qcom/sa6155.dtsi index b59622839485eaa0216d99bca26df98e322e8b97..1bf14ec01b4ab35e4f5e565013eb267c5435ae74 100644 --- a/arch/arm64/boot/dts/qcom/sa6155.dtsi +++ b/arch/arm64/boot/dts/qcom/sa6155.dtsi @@ -118,62 +118,6 @@ }; }; }; - - cpuss-0-step { - trips { - cpu45-config { - temperature = <115000>; - }; - }; - }; - - cpuss-1-step { - trips { - cpu23-config { - temperature = <115000>; - }; - }; - }; - - cpuss-2-step { - trips { - cpu01-config { - temperature = <115000>; - }; - }; - }; - - cpu-1-0-step { - trips { - cpu6-0-config { - temperature = <115000>; - }; - }; - }; - - cpu-1-1-step { - trips { - cpu6-1-config { - temperature = <115000>; - }; - }; - }; - - cpu-1-2-step { - trips { - cpu7-0-config { - temperature = <115000>; - }; - }; - }; - - cpu-1-3-step { - trips { - cpu7-1-config { - temperature = <115000>; - }; - }; - }; }; /* GPU power level overrides */ diff --git a/arch/arm64/boot/dts/qcom/sa6155p-vm-usb.dtsi b/arch/arm64/boot/dts/qcom/sa6155p-vm-usb.dtsi index ef2dcb739f3538842b85798cde19e2b54f2ed6ba..3db66cf1455fdcbd9f5fd0c0ae98b2410b4945e8 100644 --- a/arch/arm64/boot/dts/qcom/sa6155p-vm-usb.dtsi +++ b/arch/arm64/boot/dts/qcom/sa6155p-vm-usb.dtsi @@ -119,9 +119,9 @@ "tune2_efuse_addr", "tcsr_conn_box_spare_0"; - vdd-supply = <&L5A>; - vdda18-supply = <&L12A>; - vdda33-supply = <&L13A>; + vdd-supply = <&pm6150_l4>; + vdda18-supply = <&pm6150_l11>; + vdda33-supply = <&pm6150_l17>; qcom,vdd-voltage-level = <0 925000 975000>; qcom,tune2-efuse-bit-pos = <25>; qcom,tune2-efuse-num-bits = <4>; @@ -159,8 +159,8 @@ reg-names = "qmp_phy_base", "vls_clamp_reg"; - vdd-supply = <&L5A>; - core-supply = <&L12A>; + vdd-supply = <&pm6150_l4>; + core-supply = <&pm6150_l11>; qcom,vdd-voltage-level = <0 925000 975000>; qcom,core-voltage-level = <0 1800000 1800000>; qcom,qmp-phy-init-seq = @@ -370,9 +370,9 @@ reg-names = "qusb_phy_base", "tcsr_conn_box_spare_0"; - vdd-supply = <&L5A>; - vdda18-supply = <&L12A>; - vdda33-supply = <&L13A>; + vdd-supply = <&pm6150_l4>; + vdda18-supply = <&pm6150_l11>; + vdda33-supply = <&pm6150_l17>; qcom,vdd-voltage-level = <0 925000 975000>; qcom,qusb-phy-init-seq = <0xc8 0x80 0xb3 0x84 diff --git a/arch/arm64/boot/dts/qcom/sa6155p-vm.dts b/arch/arm64/boot/dts/qcom/sa6155p-vm.dts index 17f8330c92f49a1dcc48ad4c573129b8cd4325dd..0caf78c1b2e6f88ba9d5564ee30867a0115cefec 100644 --- a/arch/arm64/boot/dts/qcom/sa6155p-vm.dts +++ b/arch/arm64/boot/dts/qcom/sa6155p-vm.dts @@ -30,10 +30,6 @@ status = "ok"; }; -&qupv3_se7_4uart { - status = "ok"; -}; - &usb0 { status = "ok"; }; diff --git a/arch/arm64/boot/dts/qcom/sa6155p-vm.dtsi b/arch/arm64/boot/dts/qcom/sa6155p-vm.dtsi index 89777b7813fc943c8cb9648acfb91b3169e46a4c..7432a67530ed89cb04279e99d7259bc8f160c5cf 100644 --- a/arch/arm64/boot/dts/qcom/sa6155p-vm.dtsi +++ b/arch/arm64/boot/dts/qcom/sa6155p-vm.dtsi @@ -41,67 +41,16 @@ }; &soc { - clock_virt: qcom,virtio-gcc { - compatible = "virtio,mmio"; - reg = <0x1c200000 0x1000>; - interrupts = <0 48 0>; + clock_virt: qcom,virt-gcc { + compatible = "qcom,virt-clk-sm6150-gcc"; #clock-cells = <1>; #reset-cells = <1>; }; - clock_virt_scc: qcom,virtio-scc { - compatible = "virtio,mmio"; - reg = <0x1c300000 0x1000>; - interrupts = <0 49 0>; + clock_virt_scc: qcom,virt-scc { + compatible = "qcom,virt-clk-sm6150-scc"; #clock-cells = <1>; - }; - - regulator_virt: virtio_regulator@1c700000 { - compatible = "virtio,mmio"; - reg = <0x1c700000 0x1000>; - interrupts = <0 42 0>; - - usb30_prim_gdsc: usb30_prim_gdsc { - regulator-name = "usb30_prim_gdsc"; - }; - - usb20_sec_gdsc: usb20_sec_gdsc { - regulator-name = "usb20_sec_gdsc"; - }; - - pcie_0_gdsc: pcie_0_gdsc { - regulator-name = "pcie_0_gdsc"; - }; - - L2A: pm6155_1_l2: regulator-pm6155-1-l2 { - regulator-name = "ldoa2"; - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <3100000>; - }; - - L5A: pm6155_1_l5: regulator-pm6155-1-l5 { - regulator-name = "ldoa5"; - regulator-min-microvolt = <875000>; - regulator-max-microvolt = <975000>; - }; - - L10A: pm6155_1_l10: regulator-pm6155-1-l10 { - regulator-name = "ldoa10"; - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <3312000>; - }; - - L12A: pm6155_1_l12: regulator-pm6155-1-l12 { - regulator-name = "ldoa12"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1890000>; - }; - - L13A: pm6155_1_l13: regulator-pm6155-1-l13 { - regulator-name = "ldoa13"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3230000>; - }; + #reset-cells = <1>; }; apps_smmu: apps-smmu@0x15000000 { @@ -191,6 +140,45 @@ status = "ok"; }; + usb30_prim_gdsc: usb30_prim_gdsc { + compatible = "qcom,stub-regulator"; + regulator-name = "usb30_prim_gdsc"; + status = "ok"; + }; + + usb20_sec_gdsc: usb20_sec_gdsc { + compatible = "qcom,stub-regulator"; + regulator-name = "usb20_sec_gdsc"; + status = "ok"; + }; + + pm6150_l11: regulator-pm6150-l11 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l11"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1890000>; + status = "ok"; + }; + + pm6150_l4: regulator-pm6150-l4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l4"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <975000>; + status = "ok"; + }; + + pm6150_l17: regulator-pm6150-l17 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l17"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3230000>; + status = "ok"; + }; + qcom_seecom: qseecom@86d00000 { compatible = "qcom,qseecom"; reg = <0x86d00000 0xe00000>; @@ -204,6 +192,38 @@ qcom,qsee-reentrancy-support = <2>; }; + pm6155_1_l10: regulator-pm6155-1-l10 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6155_1_l10"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <3312000>; + status = "ok"; + }; + + pm6155_1_l2: regulator-pm6155-1-l2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6155_1_l2"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3100000>; + status = "ok"; + }; + + pm6155_1_l12: regulator-pm6155-1-l12 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6155_1_l12"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1890000>; + status = "ok"; + }; + + pm6155_1_l5: regulator-pm6155-1-l5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6155_1_l5"; + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <975000>; + status = "ok"; + }; + VDD_CX_LEVEL: VDD_MX_LEVEL: S2A_LEVEL: pm6155_1_s2_level: regulator-pm6155-1-s2-level { compatible = "qcom,stub-regulator"; @@ -214,6 +234,12 @@ = ; }; + pcie_0_gdsc: pcie_0_gdsc { + compatible = "qcom,stub-regulator"; + regulator-name = "pcie_0_gdsc"; + status = "okay"; + }; + vreg_wlan: vreg_wlan { compatible = "qcom,stub-regulator"; regulator-name = "vreg_wlan"; @@ -315,14 +341,6 @@ status = "disabled"; }; - - bluetooth_ext: bt_qca6174 { - compatible = "qca,qca6174"; - pinctrl-names = "default"; - pinctrl-0 = <&bt_en_active>; - qca,bt-reset-gpio = <&tlmm 85 0>; /* BT_EN */ - status = "ok"; - }; }; #include "sa6155p-vm-pinctrl.dtsi" @@ -331,9 +349,3 @@ #include "sa6155p-vm-usb.dtsi" #include "sa8155-vm-audio.dtsi" #include "sa6155p-vm-pcie.dtsi" -#include "pm6155-vm.dtsi" - -&tlmm { - dirconn-list = <100 216 1>, - <99 215 1>; -}; diff --git a/arch/arm64/boot/dts/qcom/sa6155p.dtsi b/arch/arm64/boot/dts/qcom/sa6155p.dtsi index 5d233dd7021a2e588b2a702c5fc19f209c1f3ee0..48d82ceec6ba3dbb1a19c9a9d7c9e1f2dc1cf61a 100644 --- a/arch/arm64/boot/dts/qcom/sa6155p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa6155p.dtsi @@ -146,62 +146,6 @@ }; }; }; - - cpuss-0-step { - trips { - cpu45-config { - temperature = <115000>; - }; - }; - }; - - cpuss-1-step { - trips { - cpu23-config { - temperature = <115000>; - }; - }; - }; - - cpuss-2-step { - trips { - cpu01-config { - temperature = <115000>; - }; - }; - }; - - cpu-1-0-step { - trips { - cpu6-0-config { - temperature = <115000>; - }; - }; - }; - - cpu-1-1-step { - trips { - cpu6-1-config { - temperature = <115000>; - }; - }; - }; - - cpu-1-2-step { - trips { - cpu7-0-config { - temperature = <115000>; - }; - }; - }; - - cpu-1-3-step { - trips { - cpu7-1-config { - temperature = <115000>; - }; - }; - }; }; /* GPU power level overrides */ diff --git a/arch/arm64/boot/dts/qcom/sa8155-vm-audio.dtsi b/arch/arm64/boot/dts/qcom/sa8155-vm-audio.dtsi index a9480a4a430f701b345d3db0d4a08b49d472942e..e101ced50d9d8cdd2f2984897fe59af2e390057d 100644 --- a/arch/arm64/boot/dts/qcom/sa8155-vm-audio.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8155-vm-audio.dtsi @@ -351,9 +351,8 @@ qcom,msm-dai-tdm-quin-rx { compatible = "qcom,msm-dai-tdm"; qcom,msm-cpudai-tdm-group-id = <37184>; - qcom,msm-cpudai-tdm-group-num-ports = <5>; - qcom,msm-cpudai-tdm-group-port-id = <36928 36930 36932 - 36934 36942>; + qcom,msm-cpudai-tdm-group-num-ports = <4>; + qcom,msm-cpudai-tdm-group-port-id = <36928 36930 36932 36934>; qcom,msm-cpudai-tdm-clk-rate = <24576000>; qcom,msm-cpudai-tdm-clk-internal = <1>; qcom,msm-cpudai-tdm-sync-mode = <1>; @@ -384,20 +383,13 @@ qcom,msm-cpudai-tdm-dev-id = <36934>; qcom,msm-cpudai-tdm-data-align = <0>; }; - - dai_quin_tdm_rx_7: qcom,msm-dai-q6-tdm-quin-rx-7 { - compatible = "qcom,msm-dai-q6-tdm"; - qcom,msm-cpudai-tdm-dev-id = <36942>; - qcom,msm-cpudai-tdm-data-align = <0>; - }; }; qcom,msm-dai-tdm-quin-tx { compatible = "qcom,msm-dai-tdm"; qcom,msm-cpudai-tdm-group-id = <37185>; - qcom,msm-cpudai-tdm-group-num-ports = <5>; - qcom,msm-cpudai-tdm-group-port-id = <36929 36931 36933 - 36935 36943>; + qcom,msm-cpudai-tdm-group-num-ports = <4>; + qcom,msm-cpudai-tdm-group-port-id = <36929 36931 36933 36935>; qcom,msm-cpudai-tdm-clk-rate = <24576000>; qcom,msm-cpudai-tdm-clk-internal = <1>; qcom,msm-cpudai-tdm-sync-mode = <1>; @@ -428,12 +420,6 @@ qcom,msm-cpudai-tdm-dev-id = <36935>; qcom,msm-cpudai-tdm-data-align = <0>; }; - - dai_quin_tdm_tx_7: qcom,msm-dai-q6-tdm-quin-tx-7 { - compatible = "qcom,msm-dai-q6-tdm"; - qcom,msm-cpudai-tdm-dev-id = <36943>; - qcom,msm-cpudai-tdm-data-align = <0>; - }; }; qcom,avtimer@170f7000 { @@ -503,10 +489,9 @@ <&dai_quat_tdm_tx_2>, <&dai_quat_tdm_tx_3>, <&dai_quat_tdm_tx_7>, <&dai_quin_tdm_rx_0>, <&dai_quin_tdm_rx_1>, <&dai_quin_tdm_rx_2>, - <&dai_quin_tdm_rx_3>, <&dai_quin_tdm_rx_7>, - <&dai_quin_tdm_tx_0>, <&dai_quin_tdm_tx_1>, - <&dai_quin_tdm_tx_2>, <&dai_quin_tdm_tx_3>, - <&dai_quin_tdm_tx_7>; + <&dai_quin_tdm_rx_3>, <&dai_quin_tdm_tx_0>, + <&dai_quin_tdm_tx_1>, <&dai_quin_tdm_tx_2>, + <&dai_quin_tdm_tx_3>; asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.24608", "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", @@ -538,10 +523,9 @@ "msm-dai-q6-tdm.36917", "msm-dai-q6-tdm.36919", "msm-dai-q6-tdm.36927", "msm-dai-q6-tdm.36928", "msm-dai-q6-tdm.36930", "msm-dai-q6-tdm.36932", - "msm-dai-q6-tdm.36934", "msm-dai-q6-tdm.36942", - "msm-dai-q6-tdm.36929", "msm-dai-q6-tdm.36931", - "msm-dai-q6-tdm.36933", "msm-dai-q6-tdm.36935", - "msm-dai-q6-tdm.36943"; + "msm-dai-q6-tdm.36934", "msm-dai-q6-tdm.36929", + "msm-dai-q6-tdm.36931", "msm-dai-q6-tdm.36933", + "msm-dai-q6-tdm.36935"; asoc-codec = <&stub_codec>; asoc-codec-names = "msm-stub-codec.1"; qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>; diff --git a/arch/arm64/boot/dts/qcom/sa8155-vm-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/sa8155-vm-pinctrl.dtsi index 2c54f126b1260ff9414f55177eeb9da1838aca18..919fcc057493bce22d7a0515af0062052ab5c49b 100644 --- a/arch/arm64/boot/dts/qcom/sa8155-vm-pinctrl.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8155-vm-pinctrl.dtsi @@ -21,452 +21,5 @@ interrupt-controller; #interrupt-cells = <2>; }; - - hs1_i2s_mclk { - hs1_i2s_mclk_sleep: hs1_i2s_mclk_sleep { - mux { - pins = "gpio155"; - function = "gpio"; - }; - - config { - pins = "gpio155"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs1_i2s_mclk_active: hs1_i2s_mclk_active { - mux { - pins = "gpio155"; - function = "hs1_mi2s"; - }; - - config { - pins = "gpio155"; - drive-strength = <8>; /* 8 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs1_i2s_sck { - hs1_i2s_sck_sleep: hs1_i2s_sck_sleep { - mux { - pins = "gpio156"; - function = "gpio"; - }; - - config { - pins = "gpio156"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs1_i2s_sck_active: hs1_i2s_sck_active { - mux { - pins = "gpio156"; - function = "hs1_mi2s"; - }; - - config { - pins = "gpio156"; - drive-strength = <8>; /* 4 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs1_i2s_ws { - hs1_i2s_ws_sleep: hs1_i2s_ws_sleep { - mux { - pins = "gpio157"; - function = "gpio"; - }; - - config { - pins = "gpio157"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs1_i2s_ws_active: hs1_i2s_ws_active { - mux { - pins = "gpio157"; - function = "hs1_mi2s"; - }; - - config { - pins = "gpio157"; - drive-strength = <8>; /* 4 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs1_i2s_data0 { - hs1_i2s_data0_sleep: hs1_i2s_data0_sleep { - mux { - pins = "gpio158"; - function = "sleep"; - }; - - config { - pins = "gpio158"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs1_i2s_data0_active: hs1_i2s_data0_active { - mux { - pins = "gpio158"; - function = "hs1_mi2s"; - }; - - config { - pins = "gpio158"; - drive-strength = <8>; /* 4 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs1_i2s_data1 { - hs1_i2s_data1_sleep: hs1_i2s_data1_sleep { - mux { - pins = "gpio159"; - function = "gpio"; - }; - - config { - pins = "gpio159"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs1_i2s_data1_active: hs1_i2s_data1_active { - mux { - pins = "gpio159"; - function = "hs1_mi2s"; - }; - - config { - pins = "gpio159"; - drive-strength = <8>; /* 4 mA */ - bias-disable; /* NO PULL */ - }; - }; - }; - - hs2_i2s_mclk { - hs2_i2s_mclk_sleep: hs2_i2s_mclk_sleep { - mux { - pins = "gpio160"; - function = "gpio"; - }; - - config { - pins = "gpio160"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs2_i2s_mclk_active: hs2_i2s_mclk_active { - mux { - pins = "gpio160"; - function = "hs2_mi2s"; - }; - - config { - pins = "gpio160"; - drive-strength = <8>; /* 8 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs2_i2s_sck { - hs2_i2s_sck_sleep: hs2_i2s_sck_sleep { - mux { - pins = "gpio161"; - function = "gpio"; - }; - - config { - pins = "gpio161"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs2_i2s_sck_active: hs2_i2s_sck_active { - mux { - pins = "gpio161"; - function = "hs2_mi2s"; - }; - - config { - pins = "gpio161"; - drive-strength = <8>; /* 4 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs2_i2s_ws { - hs2_i2s_ws_sleep: hs2_i2s_ws_sleep { - mux { - pins = "gpio162"; - function = "gpio"; - }; - - config { - pins = "gpio162"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs2_i2s_ws_active: hs2_i2s_ws_active { - mux { - pins = "gpio162"; - function = "hs2_mi2s"; - }; - - config { - pins = "gpio162"; - drive-strength = <8>; /* 4 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs2_i2s_data0 { - hs2_i2s_data0_sleep: hs2_i2s_data0_sleep { - mux { - pins = "gpio163"; - function = "gpio"; - }; - - config { - pins = "gpio163"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs2_i2s_data0_active: hs2_i2s_data0_active { - mux { - pins = "gpio163"; - function = "hs2_mi2s"; - }; - - config { - pins = "gpio163"; - drive-strength = <8>; /* 4 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs2_i2s_data1 { - hs2_i2s_data1_sleep: hs2_i2s_data1_sleep { - mux { - pins = "gpio164"; - function = "gpio"; - }; - - config { - pins = "gpio164"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs2_i2s_data1_active: hs2_i2s_data1_active { - mux { - pins = "gpio164"; - function = "hs2_mi2s"; - }; - - config { - pins = "gpio164"; - drive-strength = <8>; /* 4 mA */ - bias-disable; /* NO PULL */ - }; - }; - }; - - hs3_i2s_mclk { - hs3_i2s_mclk_sleep: hs3_i2s_mclk_sleep { - mux { - pins = "gpio125"; - function = "gpio"; - }; - - config { - pins = "gpio125"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs3_i2s_mclk_active: hs3_i2s_mclk_active { - mux { - pins = "gpio125"; - function = "hs3_mi2s"; - }; - - config { - pins = "gpio125"; - drive-strength = <8>; /* 8 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs3_i2s_sck { - hs3_i2s_sck_sleep: hs3_i2s_sck_sleep { - mux { - pins = "gpio165"; - function = "gpio"; - }; - - config { - pins = "gpio165"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs3_i2s_sck_active: hs3_i2s_sck_active { - mux { - pins = "gpio165"; - function = "hs3_mi2s"; - }; - - config { - pins = "gpio165"; - drive-strength = <8>; /* 4 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs3_i2s_ws { - hs3_i2s_ws_sleep: hs3_i2s_ws_sleep { - mux { - pins = "gpio166"; - function = "gpio"; - }; - - config { - pins = "gpio166"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs3_i2s_ws_active: hs3_i2s_ws_active { - mux { - pins = "gpio166"; - function = "hs3_mi2s"; - }; - - config { - pins = "gpio166"; - drive-strength = <8>; /* 4 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs3_i2s_data0 { - hs3_i2s_data0_sleep: hs3_i2s_data0_sleep { - mux { - pins = "gpio167"; - function = "gpio"; - }; - - config { - pins = "gpio167"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs3_i2s_data0_active: hs3_i2s_data0_active { - mux { - pins = "gpio167"; - function = "hs3_mi2s"; - }; - - config { - pins = "gpio167"; - drive-strength = <8>; /* 4 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs3_i2s_data1 { - hs3_i2s_data1_sleep: hs3_i2s_data1_sleep { - mux { - pins = "gpio168"; - function = "gpio"; - }; - - config { - pins = "gpio168"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs3_i2s_data1_active: hs3_i2s_data1_active { - mux { - pins = "gpio168"; - function = "hs3_mi2s"; - }; - - config { - pins = "gpio168"; - drive-strength = <8>; /* 4 mA */ - bias-disable; /* NO PULL */ - }; - }; - }; }; diff --git a/arch/arm64/boot/dts/qcom/sa8155-vm-usb.dtsi b/arch/arm64/boot/dts/qcom/sa8155-vm-usb.dtsi index 90366d5cb5db66db7ce278811c14d746e11a0978..5e79647ad0f3c5ac1137e218ec82353fe776eb3c 100644 --- a/arch/arm64/boot/dts/qcom/sa8155-vm-usb.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8155-vm-usb.dtsi @@ -118,9 +118,9 @@ reg-names = "hsusb_phy_base", "phy_rcal_reg"; - vdd-supply = <&pm8150_1_l5>; - vdda18-supply = <&pm8150_1_l12>; - vdda33-supply = <&pm8150_1_l2>; + vdd-supply = <&pm8150_l5>; + vdda18-supply = <&pm8150_l12>; + vdda33-supply = <&pm8150_l2>; qcom,vdd-voltage-level = <0 880000 880000>; clocks = <&clock_gcc RPMH_CXO_CLK>; @@ -140,10 +140,10 @@ reg = <0x88e8000 0x3000>; reg-names = "qmp_phy_base"; - vdd-supply = <&pm8150_1_l5>; + vdd-supply = <&pm8150_l5>; qcom,vdd-voltage-level = <0 880000 880000>; qcom,vdd-max-load-uA = <47000>; - core-supply = <&pm8150_2_l8>; + core-supply = <&pm8150l_l3>; qcom,vbus-valid-override; qcom,link-training-reset; qcom,qmp-phy-init-seq = @@ -394,9 +394,9 @@ reg-names = "hsusb_phy_base", "phy_rcal_reg"; - vdd-supply = <&pm8150_1_l5>; - vdda18-supply = <&pm8150_1_l12>; - vdda33-supply = <&pm8150_1_l2>; + vdd-supply = <&pm8150_l5>; + vdda18-supply = <&pm8150_l12>; + vdda33-supply = <&pm8150_l2>; qcom,vdd-voltage-level = <0 880000 880000>; clocks = <&clock_gcc RPMH_CXO_CLK>; @@ -417,10 +417,10 @@ reg-names = "qmp_phy_base", "pcs_clamp_enable_reg"; - vdd-supply = <&pm8150_1_l5>; + vdd-supply = <&pm8150_l5>; qcom,vdd-voltage-level = <0 880000 880000>; qcom,vdd-max-load-uA = <47000>; - core-supply = <&pm8150_2_l8>; + core-supply = <&pm8150l_l3>; qcom,vbus-valid-override; qcom,qmp-phy-init-seq = /* */ diff --git a/arch/arm64/boot/dts/qcom/sa8155-vm.dtsi b/arch/arm64/boot/dts/qcom/sa8155-vm.dtsi index c51daecfce59afa6a044781aa3df36c3d58da40b..8ec724d101ace9e57c14ae36f23cf8b7e69bcb7f 100644 --- a/arch/arm64/boot/dts/qcom/sa8155-vm.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8155-vm.dtsi @@ -29,53 +29,6 @@ }; &soc { - hsi2s: qcom,hsi2s { - compatible = "qcom,sa8155-hsi2s", "qcom,hsi2s"; - number-of-interfaces = <3>; - reg = <0x172C0000 0x28000>, - <0x17080000 0xE000>; - reg-names = "lpa_if", "lpass_tcsr"; - interrupts = ; - bit-clock-hz = <20000000>; - interrupt-interval-ms = <10>; - - sdr0: qcom,hs0_i2s { - compatible = "qcom,hsi2s-interface"; - minor-number = <0>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&hs1_i2s_mclk_active &hs1_i2s_sck_active - &hs1_i2s_ws_active &hs1_i2s_data0_active - &hs1_i2s_data1_active>; - pinctrl-1 = <&hs1_i2s_mclk_sleep &hs1_i2s_sck_sleep - &hs1_i2s_ws_sleep &hs1_i2s_data0_sleep - &hs1_i2s_data1_sleep>; - }; - - sdr1: qcom,hs1_i2s { - compatible = "qcom,hsi2s-interface"; - minor-number = <1>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&hs2_i2s_mclk_active &hs2_i2s_sck_active - &hs2_i2s_ws_active &hs2_i2s_data0_active - &hs2_i2s_data1_active>; - pinctrl-1 = <&hs2_i2s_mclk_sleep &hs2_i2s_sck_sleep - &hs2_i2s_ws_sleep &hs2_i2s_data0_sleep - &hs2_i2s_data1_sleep>; - }; - - sdr2: qcom,hs2_i2s { - compatible = "qcom,hsi2s-interface"; - minor-number = <2>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&hs3_i2s_mclk_active &hs3_i2s_sck_active - &hs3_i2s_ws_active &hs3_i2s_data0_active - &hs3_i2s_data1_active>; - pinctrl-1 = <&hs3_i2s_mclk_sleep &hs3_i2s_sck_sleep - &hs3_i2s_ws_sleep &hs3_i2s_data0_sleep - &hs3_i2s_data1_sleep>; - }; - }; - clock_virt: qcom,virtio-gcc { compatible = "virtio,mmio"; reg = <0x1c200000 0x1000>; @@ -92,96 +45,6 @@ #reset-cells = <1>; }; - regulator_virt: virtio_regulator@1c700000 { - compatible = "virtio,mmio"; - reg = <0x1c700000 0x1000>; - interrupts = <0 42 0>; - - usb30_prim_gdsc: usb30_prim_gdsc { - regulator-name = "usb30_prim_gdsc"; - }; - - usb30_sec_gdsc: usb30_sec_gdsc { - regulator-name = "usb30_sec_gdsc"; - }; - - pcie_0_gdsc: pcie_0_gdsc { - regulator-name = "pcie_0_gdsc"; - }; - - pcie_1_gdsc: pcie_1_gdsc { - regulator-name = "pcie_1_gdsc"; - }; - - L2A: pm8150_1_l2: regulator-pm8150-1-l2 { - regulator-name = "ldoa2"; - regulator-min-microvolt = <3072000>; - regulator-max-microvolt = <3072000>; - }; - - L5A: pm8150_1_l5: regulator-pm8150-1-l5 { - regulator-name = "ldoa5"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - }; - - L12A: pm8150_1_l12: regulator-pm8150-1-l12 { - regulator-name = "ldoa12"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - L17A: pm8150_1_l17: regulator-pm8150-1-l17 { - regulator-name = "ldoa17"; - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2960000>; - }; - - L8C: pm8150_2_l8: regulator-pm8150-2-l8 { - regulator-name = "ldoc8"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-allow-set-load; - }; - - L13C: pm8150_2_l13: regulator-pm8150-2-l13 { - regulator-name = "ldoc13"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2960000>; - }; - - L15C: pm8150_2_l15: regulator-pm8150-2-l15 { - regulator-name = "ldoc15"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1904000>; - }; - - L18C: pm8150_2_l18: regulator-pm8150-2-l18 { - regulator-name = "ldoc18"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-allow-set-load; - }; - - S6A: pm8150_1_s6: regulator-pm8150-1-s6 { - regulator-name = "smpa6"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1352000>; - }; - - S4C: pm8150_2_s4: regulator-pm8150-2-s4 { - regulator-name = "smpc4"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - }; - - S5C: pm8150_2_s5: regulator-pm8150-2-s5 { - regulator-name = "smpc5"; - regulator-min-microvolt = <1824000>; - regulator-max-microvolt = <2040000>; - }; - }; - apps_smmu: apps-smmu@0x15000000 { compatible = "qcom,qsmmu-v500"; reg = <0x15000000 0x100000>, @@ -286,6 +149,38 @@ status = "disabled"; }; + S6A: pm8150_1_s6: regulator-pm8150-1-s6 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8150_1_s6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1352000>; + qcom,init-voltage = <600000>; + }; + + S4C: pm8150_2_s4: regulator-pm8150-2-s4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8150_2_s4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + qcom,init-voltage = <800000>; + }; + + S5C: pm8150_2_s5: regulator-pm8150-2-s5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8150_2_s5"; + regulator-min-microvolt = <1824000>; + regulator-max-microvolt = <2040000>; + qcom,init-voltage = <1824000>; + }; + + L15C: pm8150_2_l15: regulator-pm8150-2-l15 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8150_2_l15"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1904000>; + qcom,init-voltage = <1800000>; + }; + vreg_wlan: vreg_wlan { compatible = "qcom,stub-regulator"; regulator-name = "vreg_wlan"; @@ -313,6 +208,62 @@ gpio = <&tlmm 174 0>; }; + pm8150_l2: regulator-pm8150-l2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8150_l2"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + qcom,init-voltage = <3072000>; + status = "okay"; + }; + + pm8150_l5: regulator-pm8150-l5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8150_l5"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <23800>; + qcom,init-voltage = <880000>; + status = "okay"; + }; + + pm8150_l12: regulator-pm8150-l12 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8150_l12"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + + pm8150l_l3: regulator-pm8150l-l3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8150l_l3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <51800>; + qcom,init-voltage = <1200000>; + status = "okay"; + }; + + pm8150_2_l8: regulator-pm8150-2-l8 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8150_2_l8"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + status = "okay"; + }; + + pm8150_2_l18: regulator-pm8150-2-l18 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8150_2_l18"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + status = "okay"; + }; + VDD_CX_LEVEL: VDD_MMCX_LEVEL: S9C_LEVEL: pm8150_2_s9_level: regulator-pm8150-2-s9-level { compatible = "qcom,stub-regulator"; @@ -323,6 +274,24 @@ = ; }; + pcie_0_gdsc: pcie_0_gdsc { + compatible = "qcom,stub-regulator"; + regulator-name = "pcie_0_gdsc"; + status = "okay"; + }; + + usb30_prim_gdsc: usb30_prim_gdsc { + compatible = "qcom,stub-regulator"; + regulator-name = "usb30_prim_gdsc"; + status = "okay"; + }; + + usb30_sec_gdsc: usb30_sec_gdsc { + compatible = "qcom,stub-regulator"; + regulator-name = "usb30_sec_gdsc"; + status = "okay"; + }; + qcom_seecom: qseecom@87900000 { compatible = "qcom,qseecom"; reg = <0x87900000 0x2200000>; @@ -521,7 +490,6 @@ #include "sa8155-vm-audio.dtsi" #include "sa8155-vm-pcie.dtsi" #include "sa8155-vm-mhi.dtsi" -#include "pm8150-vm.dtsi" &tlmm { dirconn-list = <37 216 1>; diff --git a/arch/arm64/boot/dts/qcom/sa8155.dtsi b/arch/arm64/boot/dts/qcom/sa8155.dtsi index 0e7494be74eda15ef9ef90cf0481debb394f9954..9e1752d2f128b0c91a51fdfc3b7b7d53798485bf 100644 --- a/arch/arm64/boot/dts/qcom/sa8155.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8155.dtsi @@ -94,13 +94,11 @@ qcom,no-l1-supported; qcom,no-l1ss-supported; qcom,no-aux-clk-sync; - qcom,core-preset = <0x77777777>; }; &pcie1 { vreg-1.8-supply = <&pm8150_2_l8>; vreg-0.9-supply = <&pm8150_2_l18>; - qcom,core-preset = <0x77777777>; }; &pcie_ep { @@ -501,62 +499,6 @@ #include &soc { - hsi2s: qcom,hsi2s { - compatible = "qcom,sa8155-hsi2s", "qcom,hsi2s"; - number-of-interfaces = <3>; - reg = <0x172C0000 0x28000>, - <0x17080000 0xE000>; - reg-names = "lpa_if", "lpass_tcsr"; - interrupts = ; - bit-clock-hz = <20000000>; - interrupt-interval-ms = <10>; - - sdr0: qcom,hs0_i2s { - compatible = "qcom,hsi2s-interface"; - minor-number = <0>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&hs1_i2s_mclk_active &hs1_i2s_sck_active - &hs1_i2s_ws_active &hs1_i2s_data0_active - &hs1_i2s_data1_active>; - pinctrl-1 = <&hs1_i2s_mclk_sleep &hs1_i2s_sck_sleep - &hs1_i2s_ws_sleep &hs1_i2s_data0_sleep - &hs1_i2s_data1_sleep>; - iommus = <&apps_smmu 0x1B5C 0x0>; - qcom,smmu-s1-bypass; - qcom,iova-mapping = <0x0 0xFFFFFFFF>; - }; - - sdr1: qcom,hs1_i2s { - compatible = "qcom,hsi2s-interface"; - minor-number = <1>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&hs2_i2s_mclk_active &hs2_i2s_sck_active - &hs2_i2s_ws_active &hs2_i2s_data0_active - &hs2_i2s_data1_active>; - pinctrl-1 = <&hs2_i2s_mclk_sleep &hs2_i2s_sck_sleep - &hs2_i2s_ws_sleep &hs2_i2s_data0_sleep - &hs2_i2s_data1_sleep>; - iommus = <&apps_smmu 0x1B5D 0x0>; - qcom,smmu-s1-bypass; - qcom,iova-mapping = <0x0 0xFFFFFFFF>; - }; - - sdr2: qcom,hs2_i2s { - compatible = "qcom,hsi2s-interface"; - minor-number = <2>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&hs3_i2s_mclk_active &hs3_i2s_sck_active - &hs3_i2s_ws_active &hs3_i2s_data0_active - &hs3_i2s_data1_active>; - pinctrl-1 = <&hs3_i2s_mclk_sleep &hs3_i2s_sck_sleep - &hs3_i2s_ws_sleep &hs3_i2s_data0_sleep - &hs3_i2s_data1_sleep>; - iommus = <&apps_smmu 0x1B5E 0x0>; - qcom,smmu-s1-bypass; - qcom,iova-mapping = <0x0 0xFFFFFFFF>; - }; - }; - emac_hw: qcom,emac@00020000 { compatible = "qcom,emac-dwc-eqos"; qcom,arm-smmu; diff --git a/arch/arm64/boot/dts/qcom/sa8195-pmic.dtsi b/arch/arm64/boot/dts/qcom/sa8195-pmic.dtsi index c19adc024a9d982179da8f0e78bd9ec17fdcd8f0..2cdf7df42ed99af67da3b5c239cff682ee08b7c4 100644 --- a/arch/arm64/boot/dts/qcom/sa8195-pmic.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8195-pmic.dtsi @@ -75,16 +75,40 @@ /delete-property/ vdda33-supply; }; -&lmh_dcvs1 { - isens_vref_0p8-supply = <&pm8195_3_l5>; - isens-vref-0p8-settings = <880000 880000 20000>; - isens_vref_1p8-supply = <&pm8195_1_l12>; - isens-vref-1p8-settings = <1800000 1800000 20000>; +&mdss_dsi0 { + vdda-1p2-supply = <&pm8195_1_l9>; }; -&clock_camcc { - vdd_mx-supply = <&VDD_MX_LEVEL>; - vdd_mm-supply = <&VDD_MMCX_LEVEL>; +&mdss_dsi1 { + vdda-1p2-supply = <&pm8195_1_l9>; +}; + +&mdss_dsi_phy0 { + vdda-0p9-supply = <&pm8195_3_l5>; +}; + +&mdss_dsi_phy1 { + vdda-0p9-supply = <&pm8195_3_l5>; +}; + +&clock_cpucc { + lmh_dcvs1: qcom,limits-dcvs@18350800 { + isens_vref_0p8-supply = <&pm8195_3_l5>; + isens-vref-0p8-settings = <880000 880000 20000>; + isens_vref_1p8-supply = <&pm8195_1_l12>; + isens-vref-1p8-settings = <1800000 1800000 20000>; + }; +}; + + +&soc { + qcom,lpass@17300000 { + vdd_cx-supply = <&VDD_CX_LEVEL>; + }; + clock_camcc: qcom,camcc@ad00000 { + vdd_mx-supply = <&VDD_MX_LEVEL>; + vdd_mm-supply = <&VDD_MMCX_LEVEL>; + }; }; &gpu_gx_gdsc { diff --git a/arch/arm64/boot/dts/qcom/sa8195-vm.dts b/arch/arm64/boot/dts/qcom/sa8195-vm.dts index 5c7ef0257b31790a8bd0695c0453f3fe0b89a5ca..12807e33cf4ee204257b3d77e2e1357f90c8e185 100644 --- a/arch/arm64/boot/dts/qcom/sa8195-vm.dts +++ b/arch/arm64/boot/dts/qcom/sa8195-vm.dts @@ -36,11 +36,3 @@ &usb2_phy0 { status = "ok"; }; - -&spmi_bus { - status = "disabled"; -}; - -&viospmi { - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/qcom/sa8195-vm.dtsi b/arch/arm64/boot/dts/qcom/sa8195-vm.dtsi index 1f0c3ded4e0f98c8b65db8e51678d6a1b5199e91..12c910533271f50bfb8354ba40524efd5e42d09f 100644 --- a/arch/arm64/boot/dts/qcom/sa8195-vm.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8195-vm.dtsi @@ -11,7 +11,7 @@ */ #include "skeleton64.dtsi" -#include +#include #include #include #include "quin-vm-common.dtsi" @@ -31,19 +31,16 @@ }; &soc { - clock_virt: qcom,virtio-gcc { - compatible = "virtio,mmio"; - reg = <0x1c200000 0x1000>; - interrupts = <0 48 0>; + clock_virt: qcom,virt-gcc { + compatible = "qcom,virt-clk-sm8150-gcc"; #clock-cells = <1>; #reset-cells = <1>; }; - clock_virt_scc: qcom,virtio-scc { - compatible = "virtio,mmio"; - reg = <0x1c300000 0x1000>; - interrupts = <0 49 0>; + clock_virt_scc: qcom,virt-scc { + compatible = "qcom,virt-clk-sm8150-scc"; #clock-cells = <1>; + #reset-cells = <1>; }; apps_smmu: apps-smmu@0x15000000 { @@ -139,55 +136,7 @@ , , , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; + ; status = "disabled"; }; @@ -198,31 +147,44 @@ status = "disabled"; }; - pm8195_3_l5: regulator-pm8195-3-l5 { + pm8150_l2: regulator-pm8150-l2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8150_l2"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + qcom,init-voltage = <3072000>; + status = "okay"; + }; + + pm8150_l5: regulator-pm8150-l5 { compatible = "qcom,stub-regulator"; - regulator-name = "pm8195_3_l5"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <920000>; - qcom,init-voltage = <800000>; - status = "ok"; + regulator-name = "pm8150_l5"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <23800>; + qcom,init-voltage = <880000>; + status = "okay"; }; - pm8195_1_l12: regulator-pm8195-1-l12 { + pm8150_l12: regulator-pm8150-l12 { compatible = "qcom,stub-regulator"; - regulator-name = "pm8195_1_l12"; + regulator-name = "pm8150_l12"; regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1890000>; + regulator-max-microvolt = <1800000>; qcom,init-voltage = <1800000>; - status = "ok"; + status = "okay"; }; - pm8195_3_l16: regulator-pm8195-3-l16 { + pm8150l_l3: regulator-pm8150l-l3 { compatible = "qcom,stub-regulator"; - regulator-name = "pm8195_3_l16"; - regulator-min-microvolt = <2921000>; - regulator-max-microvolt = <3300000>; - qcom,init-voltage = <2921000>; - status = "ok"; + regulator-name = "pm8150l_l3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <51800>; + qcom,init-voltage = <1200000>; + status = "okay"; }; usb30_prim_gdsc: usb30_prim_gdsc { @@ -241,5 +203,5 @@ #include "sdmshrike-pinctrl.dtsi" #include "sm8150-slpi-pinctrl.dtsi" #include "sa8155-vm-qupv3.dtsi" -#include "sa8195-vm-usb.dtsi" +#include "sa8155-vm-usb.dtsi" #include "sa8155-vm-audio.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sa8195p-adp-star-display.dtsi b/arch/arm64/boot/dts/qcom/sa8195p-adp-star-display.dtsi index b2eca5ab8c46e4e1f2ca42a4e995f503dc1f2c7b..24262a3a9614e17900ef1307e256cb2c8e82d77a 100644 --- a/arch/arm64/boot/dts/qcom/sa8195p-adp-star-display.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8195p-adp-star-display.dtsi @@ -302,9 +302,5 @@ }; &mdss_mdp { - qcom,sde-ctl-display-pref = "primary", "none", "none", - "none", "none"; - qcom,sde-mixer-display-pref = "primary", "none", "none", - "none", "none", "none"; connectors = <&dsi_dp1 &dsi_dp2 &sde_dp &sde_wb>; }; diff --git a/arch/arm64/boot/dts/qcom/sa8195p-adp-star.dtsi b/arch/arm64/boot/dts/qcom/sa8195p-adp-star.dtsi index 260046900f354788b3034493ff85f78ba4fd2ba9..02e46d98694911dbcf59ac5bb21596442ba84d5b 100644 --- a/arch/arm64/boot/dts/qcom/sa8195p-adp-star.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8195p-adp-star.dtsi @@ -11,7 +11,6 @@ */ #include -#include "sa8195p-adp-star-display.dtsi" &qupv3_se0_spi { status = "ok"; @@ -35,55 +34,3 @@ &qupv3_se12_2uart { status = "ok"; }; - -&sdhc_2 { - vdd-supply = <&pm8195_1_l10>; - qcom,vdd-voltage-level = <2950000 2960000>; - qcom,vdd-current-level = <200 800000>; - - vdd-io-supply = <&pm8195_1_l2>; - qcom,vdd-io-voltage-level = <1808000 2960000>; - qcom,vdd-io-current-level = <200 22000>; - - pinctrl-names = "active", "sleep"; - pinctrl-0 = <&sdc2_clk_on - &sdc2_cmd_on &sdc2_data_on &storage_cd_default>; - pinctrl-1 = <&sdc2_clk_off - &sdc2_cmd_off &sdc2_data_off &storage_cd_default>; - - cd-gpios = <&pm8195_1_gpios 4 GPIO_ACTIVE_LOW>; - - status = "ok"; -}; - -&pil_lpass { - status = "ok"; -}; - -&pil_ssc { - status = "disabled"; -}; - -&pil_spss { - status = "ok"; -}; - -&pil_turing { - status = "ok"; -}; - -&pil_venus { - status = "ok"; -}; - -&pil_npu { - status = "ok"; -}; - -&glink_modem { - status = "disabled"; -}; - -&ssc_sensors { - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/qcom/sa8195p.dtsi b/arch/arm64/boot/dts/qcom/sa8195p.dtsi index 6fae09a904b5234cd4f62a3ebd972526c4d4bee3..237ab398e218416c2cc536df1911026c72848892 100644 --- a/arch/arm64/boot/dts/qcom/sa8195p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8195p.dtsi @@ -10,14 +10,8 @@ * GNU General Public License for more details. */ -#include #include "sdmshrike-v2.dtsi" #include "sa8155-audio.dtsi" -#include "sa8195-pmic.dtsi" -#include "sm8150-camera.dtsi" -#include "sm8150-v2-camera.dtsi" -#include "sa8155-camera-sensor.dtsi" -#include "sa8195p-pcie.dtsi" / { model = "Qualcomm Technologies, Inc. SA8195P"; @@ -25,6 +19,7 @@ qcom,msm-id = <405 0x20000>; }; +#include &soc { emac_hw: qcom,emac@00020000 { compatible = "qcom,emac-dwc-eqos"; @@ -110,220 +105,4 @@ qcom,iova-mapping = <0x80000000 0x40000000>; }; }; - - qcom,cam_smmu { - msm_cam_smmu_ife { - iommus = <&apps_smmu 0xAA0 0x4E0>, - <&apps_smmu 0xA20 0x4E0>, - <&apps_smmu 0xA00 0x4E0>, - <&apps_smmu 0xA80 0x4E0>, - <&apps_smmu 0xEA0 0x4E0>, - <&apps_smmu 0xE20 0x4E0>, - <&apps_smmu 0xE00 0x4E0>, - <&apps_smmu 0xE80 0x4E0>; - }; - - msm_cam_smmu_jpeg { - iommus = <&apps_smmu 0x2100 0x20>, - <&apps_smmu 0x2120 0x20>; - }; - - msm_cam_smmu_icp { - iommus = <&apps_smmu 0x2042 0x0>, - <&apps_smmu 0x2080 0x320>, - <&apps_smmu 0x20A0 0x320>, - <&apps_smmu 0x2380 0x320>, - <&apps_smmu 0x23A0 0x320>, - <&apps_smmu 0x20C0 0x300>, - <&apps_smmu 0x23C0 0x300>; - }; - - msm_cam_smmu_fd { - iommus = <&apps_smmu 0x2140 0x20>, - <&apps_smmu 0x2160 0x20>; - }; - - msm_cam_smmu_lrme { - iommus = <&apps_smmu 0x20e0 0x300>, - <&apps_smmu 0x23E0 0x300>; - }; - }; - - cam_csid0 { - clock-rates = - <400000000 0 0 0 400000000 0 0>, - <400000000 0 0 0 558000000 0 0>, - <480000000 0 0 0 637000000 0 0>, - <600000000 0 0 0 760000000 0 0>; - clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; - }; - - cam_csid1 { - clock-rates = - <400000000 0 0 0 400000000 0 0>, - <400000000 0 0 0 558000000 0 0>, - <480000000 0 0 0 637000000 0 0>, - <600000000 0 0 0 760000000 0 0>; - clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; - }; - - cam_vfe0 { - clock-rates = - <400000000 0 0>, - <558000000 0 0>, - <637000000 0 0>, - <760000000 0 0>; - clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; - }; - - cam_vfe1 { - clock-rates = - <400000000 0 0>, - <558000000 0 0>, - <637000000 0 0>, - <760000000 0 0>; - clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; - }; -}; - -&usb1 { - qcom,default-mode-host; - status = "ok"; -}; - -&slpi_tlmm { - status = "ok"; -}; - -&pil_ssc { - vdd_cx-supply = <&VDD_CX_LEVEL>; - vdd_mx-supply = <&VDD_MX_LEVEL>; - status = "ok"; -}; - -&ssc_sensors { - status = "disabled"; -}; - -&clock_rpmh { - compatible = "qcom,rpmh-clk-sm8150"; -}; - -&clock_scc { - compatible = "qcom,scc-sa8195"; -}; - -&ufsphy_mem { - compatible = "qcom,ufs-phy-qmp-v4"; - vdda-phy-supply = <&pm8195_3_l5>; - vdda-pll-supply = <&pm8195_1_l9>; - vdda-phy-max-microamp = <138000>; - vdda-pll-max-microamp = <65100>; - - status = "ok"; -}; - -&ufshc_mem { - vdd-hba-supply = <&ufs_phy_gdsc>; - vdd-hba-fixed-regulator; - vcc-supply = <&pm8195_3_l10>; - vcc-voltage-level = <2894000 2904000>; - vcc-low-voltage-sup; - vccq-supply = <&pm8195_1_l11>; - vccq2-supply = <&pm8195_3_l7>; - vcc-max-microamp = <750000>; - vccq-max-microamp = <750000>; - vccq2-max-microamp = <750000>; - - status= "ok"; -}; - -&usb2_phy0 { - vdd-supply = <&pm8195_3_l5>; - vdda18-supply = <&pm8195_1_l12>; - vdda33-supply = <&pm8195_3_l16>; -}; - -&usb2_phy1 { - vdd-supply = <&pm8195_3_l5>; - vdda18-supply = <&pm8195_1_l12>; - vdda33-supply = <&pm8195_3_l16>; - status = "ok"; -}; - -&mdss_dsi_phy0 { - vdda-0p9-supply = <&pm8195_3_l5>; -}; - -&mdss_dsi_phy1 { - vdda-0p9-supply = <&pm8195_3_l5>; -}; - -&mdss_dsi0 { - vdda-1p2-supply = <&pm8195_1_l9>; -}; - -&mdss_dsi1 { - vdda-1p2-supply = <&pm8195_1_l9>; -}; - -&sde_dp { - vdda-1p2-supply = <&pm8195_1_l9>; - vdda-0p9-supply = <&pm8195_3_l5>; -}; - -&pil_lpass { - vdd_cx-supply = <&VDD_CX_LEVEL>; - status = "ok"; -}; - -&clock_scc { - vdd_scc_cx-supply = <&pm8195_3_l8_level>; - status = "ok"; -}; - -&cam_csiphy0 { - mipi-csi-vdd-supply = <&pm8195_1_l9>; -}; - -&cam_csiphy1 { - mipi-csi-vdd-supply = <&pm8195_1_l9>; -}; - -&cam_csiphy2 { - mipi-csi-vdd-supply = <&pm8195_1_l9>; -}; - -&cam_csiphy3 { - mipi-csi-vdd-supply = <&pm8195_1_l9>; -}; - -&cam_cci0 { - qcom,cam-sensor@0 { - cam_vio-supply = <&pm8195_s4>; - cam_bob-supply = <&pm8195_s4>; - cam_vana-supply = <&pm8195_s4>; - cam_vdig-supply = <&pm8195_s4>; - }; - - qcom,cam-sensor@1 { - cam_vio-supply = <&pm8195_s4>; - cam_bob-supply = <&pm8195_s4>; - cam_vana-supply = <&pm8195_s4>; - cam_vdig-supply = <&pm8195_s4>; - }; - - qcom,cam-sensor@2 { - cam_vio-supply = <&pm8195_s4>; - cam_bob-supply = <&pm8195_s4>; - cam_vana-supply = <&pm8195_s4>; - cam_vdig-supply = <&pm8195_s4>; - }; - - qcom,cam-sensor@3 { - cam_vio-supply = <&pm8195_s4>; - cam_bob-supply = <&pm8195_s4>; - cam_vana-supply = <&pm8195_s4>; - cam_vdig-supply = <&pm8195_s4>; - }; }; diff --git a/arch/arm64/boot/dts/qcom/sdmmagpie-idp.dtsi b/arch/arm64/boot/dts/qcom/sdmmagpie-idp.dtsi index 27c0b7a148225903c04776422440e55045b51306..5b7a01baa270506d90e3921c831f869dfd21103a 100644 --- a/arch/arm64/boot/dts/qcom/sdmmagpie-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sdmmagpie-idp.dtsi @@ -258,48 +258,6 @@ qcom,platform-te-gpio = <&tlmm 11 0>; }; -&dsi_sharp_qsync_wqhd_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 10 0>; - qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; - qcom,platform-en-gpio = <&pm6150l_gpios 4 0>; - qcom,platform-bklight-en-gpio = <&pm6150l_gpios 5 0>; -}; - -&dsi_sharp_qsync_wqhd_video { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; - qcom,platform-en-gpio = <&pm6150l_gpios 4 0>; - qcom,platform-bklight-en-gpio = <&pm6150l_gpios 5 0>; -}; - -&dsi_sharp_qsync_fhd_video { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; - qcom,platform-en-gpio = <&pm6150l_gpios 4 0>; - qcom,platform-bklight-en-gpio = <&pm6150l_gpios 5 0>; -}; - -&dsi_sharp_qsync_fhd_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 10 0>; - qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; - qcom,platform-en-gpio = <&pm6150l_gpios 4 0>; - qcom,platform-bklight-en-gpio = <&pm6150l_gpios 5 0>; -}; - &sde_dp { qcom,dp-aux-switch = <&fsa4480>; }; diff --git a/arch/arm64/boot/dts/qcom/sdmmagpie-sde-display.dtsi b/arch/arm64/boot/dts/qcom/sdmmagpie-sde-display.dtsi index f39f94baa14c606ca687e1ca84db9e212b1f4a0d..4bbb187fa85b0f68c5195d4099fddc3558e08f4f 100644 --- a/arch/arm64/boot/dts/qcom/sdmmagpie-sde-display.dtsi +++ b/arch/arm64/boot/dts/qcom/sdmmagpie-sde-display.dtsi @@ -26,10 +26,6 @@ #include "dsi-panel-rm69299-visionox-amoled-fhd-plus-video.dtsi" #include "dsi-panel-nt35695b-truly-fhd-video.dtsi" #include "dsi-panel-nt35695b-truly-fhd-cmd.dtsi" -#include "dsi-panel-sharp-qsync-wqhd-cmd.dtsi" -#include "dsi-panel-sharp-qsync-wqhd-video.dtsi" -#include "dsi-panel-sharp-qsync-fhd-video.dtsi" -#include "dsi-panel-sharp-qsync-fhd-cmd.dtsi" #include &soc { @@ -303,50 +299,6 @@ qcom,dsi-panel = <&dsi_rm69299_visionox_amoled_video>; }; - dsi_sharp_qsync_wqhd_cmd_display: qcom,dsi-display@18 { - label = "dsi_sharp_qsync_wqhd_cmd_display"; - qcom,display-type = "primary"; - - qcom,dsi-ctrl-num = <0 1>; - qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - - qcom,dsi-panel = <&dsi_sharp_qsync_wqhd_cmd>; - }; - - dsi_sharp_qsync_wqhd_video_display: qcom,dsi-display@19 { - label = "dsi_sharp_qsync_wqhd_video_display"; - qcom,display-type = "primary"; - - qcom,dsi-ctrl-num = <0 1>; - qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - - qcom,dsi-panel = <&dsi_sharp_qsync_wqhd_video>; - }; - - dsi_sharp_qsync_fhd_video_display: qcom,dsi-display@20 { - label = "dsi_sharp_qsync_fhd_video_display"; - qcom,display-type = "primary"; - - qcom,dsi-ctrl-num = <0 1>; - qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - - qcom,dsi-panel = <&dsi_sharp_qsync_fhd_video>; - }; - - dsi_sharp_qsync_fhd_cmd_display: qcom,dsi-display@21 { - label = "dsi_sharp_qsync_fhd_cmd_display"; - qcom,display-type = "primary"; - - qcom,dsi-ctrl-num = <0 1>; - qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - - qcom,dsi-panel = <&dsi_sharp_qsync_fhd_cmd>; - }; - sde_dsi: qcom,dsi-display { compatible = "qcom,dsi-display"; @@ -395,11 +347,7 @@ &dsi_rm69298_truly_amoled_cmd_display &dsi_nt35695b_truly_fhd_video_display &dsi_nt35695b_truly_fhd_cmd_display - &dsi_rm69299_visionox_amoled_vid_display - &dsi_sharp_qsync_wqhd_cmd_display - &dsi_sharp_qsync_wqhd_video_display - &dsi_sharp_qsync_fhd_video_display - &dsi_sharp_qsync_fhd_cmd_display>; + &dsi_rm69299_visionox_amoled_vid_display>; }; @@ -788,91 +736,6 @@ qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08 08 05 02 04 00]; qcom,display-topology = <1 0 1>; - }; - }; -}; - -&dsi_sharp_qsync_wqhd_cmd { - qcom,mdss-dsi-t-clk-post = <0x0B>; - qcom,mdss-dsi-t-clk-pre = <0x24>; - qcom,mdss-dsi-display-timings { - timing@0{ /* 2k */ - qcom,mdss-dsi-panel-phy-timings = [00 0B 03 02 1D 1C 03 - 03 01 02 04 00]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - timing@1{ /* fhd */ - qcom,mdss-dsi-panel-phy-timings = [00 0A 01 02 1B 1B 02 - 02 00 02 04 00]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - timing@2{ - qcom,mdss-dsi-panel-phy-timings = [00 11 04 04 1E 1E 04 - 04 02 02 04 00]; - qcom,mdss-mdp-transfer-time-us = <8500>; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - timing@3{ - qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06 - 06 03 02 04 00]; - qcom,mdss-mdp-transfer-time-us = <5800>; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_sharp_qsync_wqhd_video { - qcom,mdss-dsi-t-clk-post = <0x0A>; - qcom,mdss-dsi-t-clk-pre = <0x1E>; - qcom,mdss-dsi-display-timings { - timing@0{ - qcom,mdss-dsi-panel-phy-timings = [00 12 04 04 1E 1E 04 - 04 02 02 04 00]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_sharp_qsync_fhd_video { - qcom,mdss-dsi-t-clk-post = <0x0A>; - qcom,mdss-dsi-t-clk-pre = <0x20>; - qcom,mdss-dsi-display-timings { - timing@0{ - qcom,mdss-dsi-panel-phy-timings = [00 13 04 04 1F 1F 04 - 05 03 02 04 00]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_sharp_qsync_fhd_cmd { - qcom,mdss-dsi-t-clk-post = <0x09>; - qcom,mdss-dsi-t-clk-pre = <0x12>; - qcom,mdss-dsi-display-timings { - timing@0{ - qcom,mdss-dsi-panel-phy-timings = [00 0A 01 02 1B 1B 02 - 02 00 02 04 00]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - timing@1{ - qcom,mdss-dsi-panel-phy-timings = [00 0C 02 02 1D 1C 03 - 03 01 02 04 00]; - qcom,mdss-mdp-transfer-time-us = <8500>; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - timing@2{ - qcom,mdss-dsi-panel-phy-timings = [00 0F 03 03 1E 1D 04 - 04 02 02 04 00]; - qcom,mdss-mdp-transfer-time-us = <5800>; - qcom,display-topology = <2 2 2>; qcom,default-topology-index = <0>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdmmagpie-thermal-overlay.dtsi b/arch/arm64/boot/dts/qcom/sdmmagpie-thermal-overlay.dtsi index 37c22bca3baf872b585b444e55e3433db6f548cc..f47d16937319f90936558fff5b4e5a3a6c7e578e 100644 --- a/arch/arm64/boot/dts/qcom/sdmmagpie-thermal-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/sdmmagpie-thermal-overlay.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -125,16 +125,16 @@ }; }; - pm6150-bcl-lvl0 { + pm6150-vbat-lvl0 { cooling-maps { vbat_cpu6 { - trip = <&bcl_lvl0>; + trip = <&vbat_lvl0>; cooling-device = <&CPU6 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; vbat_cpu7 { - trip = <&bcl_lvl0>; + trip = <&vbat_lvl0>; cooling-device = <&CPU7 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; @@ -142,33 +142,16 @@ }; }; - pm6150-bcl-lvl1 { + pm6150-ibat-lvl0 { cooling-maps { ibat_cpu6 { - trip = <&bcl_lvl1>; + trip = <&ibat_lvl0>; cooling-device = <&CPU6 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; ibat_cpu7 { - trip = <&bcl_lvl1>; - cooling-device = - <&CPU7 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - }; - }; - - pm6150-bcl-lvl2 { - cooling-maps { - ibat_cpu6 { - trip = <&bcl_lvl2>; - cooling-device = - <&CPU6 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - ibat_cpu7 { - trip = <&bcl_lvl2>; + trip = <&ibat_lvl0>; cooling-device = <&CPU7 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; diff --git a/arch/arm64/boot/dts/qcom/sdmmagpie-usb.dtsi b/arch/arm64/boot/dts/qcom/sdmmagpie-usb.dtsi index 28103989d07d2521b655fe7e167937c859fae572..367be23a8c81730c43e7f4e6ce43e15f83adc3e0 100644 --- a/arch/arm64/boot/dts/qcom/sdmmagpie-usb.dtsi +++ b/arch/arm64/boot/dts/qcom/sdmmagpie-usb.dtsi @@ -19,8 +19,6 @@ reg = <0x0a600000 0x100000>; reg-names = "core_base"; - iommus = <&apps_smmu 0x540 0x0>; - qcom,smmu-s1-bypass; #address-cells = <1>; #size-cells = <1>; ranges; @@ -54,7 +52,6 @@ 0x130 /* GSI_RING_BASE_ADDR_L */ 0x144 /* GSI_RING_BASE_ADDR_H */ 0x1a4>; /* GSI_IF_STS */ - qcom,gsi-disable-io-coherency; qcom,dwc-usb3-msm-tx-fifo-size = <21288>; qcom,pm-qos-latency = <62>; diff --git a/arch/arm64/boot/dts/qcom/sdmshrike-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/sdmshrike-pinctrl.dtsi index cbc0a8078a3107548ab255ac07f9fa777e4cd20c..36a98fc4fbc019c65bcb5310f9fec67f212e4493 100644 --- a/arch/arm64/boot/dts/qcom/sdmshrike-pinctrl.dtsi +++ b/arch/arm64/boot/dts/qcom/sdmshrike-pinctrl.dtsi @@ -1819,77 +1819,6 @@ }; }; - ap2mdm { - ap2mdm_active: ap2mdm_active { - mux { - /* ap2mdm-status - * ap2mdm-errfatal - * ap2mdm-vddmin - */ - pins = "gpio135", "gpio139"; - function = "gpio"; - }; - - config { - pins = "gpio135", "gpio139"; - drive-strength = <16>; - bias-disable; - }; - }; - ap2mdm_sleep: ap2mdm_sleep { - mux { - /* ap2mdm-status - * ap2mdm-errfatal - * ap2mdm-vddmin - */ - pins = "gpio135", "gpio139"; - function = "gpio"; - }; - - config { - pins = "gpio135", "gpio139"; - drive-strength = <8>; - bias-disable; - }; - - }; - }; - - mdm2ap { - mdm2ap_active: mdm2ap_active { - mux { - /* mdm2ap-status - * mdm2ap-errfatal - * mdm2ap-vddmin - */ - pins = "gpio81", "gpio53"; - function = "gpio"; - }; - - config { - pins = "gpio81", "gpio53"; - drive-strength = <8>; - bias-disable; - }; - }; - mdm2ap_sleep: mdm2ap_sleep { - mux { - /* mdm2ap-status - * mdm2ap-errfatal - * mdm2ap-vddmin - */ - pins = "gpio81", "gpio53"; - function = "gpio"; - }; - - config { - pins = "gpio81", "gpio53"; - drive-strength = <8>; - bias-disable; - }; - }; - }; - cam_sensor_mclk0_active: cam_sensor_mclk0_active { /* MCLK0 */ mux { diff --git a/arch/arm64/boot/dts/qcom/sdmshrike-v2.dtsi b/arch/arm64/boot/dts/qcom/sdmshrike-v2.dtsi index ee52993f54815d098b1723585ba6d8ae2587ae8d..13c41d54eb87a445cb5742aba014638aa26219ef 100644 --- a/arch/arm64/boot/dts/qcom/sdmshrike-v2.dtsi +++ b/arch/arm64/boot/dts/qcom/sdmshrike-v2.dtsi @@ -260,134 +260,3 @@ iommus = <&apps_smmu 0x1009 0x0460>; }; }; - -&soc { - /delete-node/ llcc-bw-opp-table; - /delete-node/ ddr-bw-opp-table; - /delete-node/ suspendable-ddr-bw-opp-table; - - llcc_bw_opp_table: llcc-bw-opp-table { - compatible = "operating-points-v2"; - BW_OPP_ENTRY( 150, 16); /* 2288 MB/s */ - BW_OPP_ENTRY( 300, 16); /* 4577 MB/s */ - BW_OPP_ENTRY( 466, 16); /* 7110 MB/s */ - BW_OPP_ENTRY( 600, 16); /* 9155 MB/s */ - BW_OPP_ENTRY( 806, 16); /* 12298 MB/s */ - BW_OPP_ENTRY( 933, 16); /* 14236 MB/s */ - BW_OPP_ENTRY(1000, 16); /* 15258 MB/s */ - }; - - ddr_bw_opp_table: ddr-bw-opp-table { - compatible = "operating-points-v2"; - BW_OPP_ENTRY( 200, 4); /* 762 MB/s */ - BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */ - BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */ - BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */ - BW_OPP_ENTRY( 681, 4); /* 2597 MB/s */ - BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */ - BW_OPP_ENTRY(1017, 4); /* 3879 MB/s */ - BW_OPP_ENTRY(1353, 4); /* 5161 MB/s */ - BW_OPP_ENTRY(1555, 4); /* 5931 MB/s */ - BW_OPP_ENTRY(1804, 4); /* 6881 MB/s */ - BW_OPP_ENTRY(2092, 4); /* 7980 MB/s */ - }; - - suspendable_ddr_bw_opp_table: suspendable-ddr-bw-opp-table { - compatible = "operating-points-v2"; - BW_OPP_ENTRY( 0, 4); /* 0 MB/s */ - BW_OPP_ENTRY( 200, 4); /* 762 MB/s */ - BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */ - BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */ - BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */ - BW_OPP_ENTRY( 681, 4); /* 2597 MB/s */ - BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */ - BW_OPP_ENTRY(1017, 4); /* 3879 MB/s */ - BW_OPP_ENTRY(1353, 4); /* 5161 MB/s */ - BW_OPP_ENTRY(1555, 4); /* 5931 MB/s */ - BW_OPP_ENTRY(1804, 4); /* 6881 MB/s */ - BW_OPP_ENTRY(2092, 4); /* 7980 MB/s */ - }; -}; - -&gpubw { - /delete-property/ qcom,bw-tbl; - operating-points-v2 = <&suspendable_ddr_bw_opp_table>; -}; - -&cpu4_computemon { - qcom,core-dev-table = - < 1920000 MHZ_TO_MBPS( 200, 4) >, - < 2793600 MHZ_TO_MBPS(1017, 4) >, - < 3000000 MHZ_TO_MBPS(2092, 4) >; -}; - -&cpu0_llcc_ddr_latmon { - qcom,core-dev-table = - < 300000 MHZ_TO_MBPS( 200, 4) >, - < 768000 MHZ_TO_MBPS( 451, 4) >, - < 1113600 MHZ_TO_MBPS( 547, 4) >, - < 1478400 MHZ_TO_MBPS( 768, 4) >, - < 1632000 MHZ_TO_MBPS(1017, 4) >; -}; - -&cpu4_llcc_ddr_latmon { - qcom,core-dev-table = - < 300000 MHZ_TO_MBPS( 200, 4) >, - < 710400 MHZ_TO_MBPS( 451, 4) >, - < 825600 MHZ_TO_MBPS( 547, 4) >, - < 1056000 MHZ_TO_MBPS( 768, 4) >, - < 1286400 MHZ_TO_MBPS(1017, 4) >, - < 1612800 MHZ_TO_MBPS(1353, 4) >, - < 1804800 MHZ_TO_MBPS(1555, 4) >, - < 2649600 MHZ_TO_MBPS(1804, 4) >, - < 3000000 MHZ_TO_MBPS(2092, 4) >; -}; - -&cpu0_cpu_l3_latmon { - qcom,core-dev-table = - < 300000 300000000 >, - < 499200 403200000 >, - < 576000 499200000 >, - < 672000 614400000 >, - < 768000 710400000 >, - < 940800 806400000 >, - < 1036800 902400000 >, - < 1113600 998400000 >, - < 1209600 1075280000 >, - < 1305600 1171200000 >, - < 1382400 1267200000 >, - < 1478400 1344000000 >, - < 1632000 1536000000 >, - < 1785600 1612800000 >; -}; - -&cpu4_cpu_l3_latmon { - qcom,core-dev-table = - < 300000 300000000 >, - < 825600 614400000 >, - < 1171200 806400000 >, - < 1401600 998400000 >, - < 1708800 1267200000 >, - < 2016000 1344000000 >, - < 2419200 1536000000 >, - < 2841600 1612800000 >; -}; - -&cpu0_cpu_llcc_latmon { - qcom,core-dev-table = - < 300000 MHZ_TO_MBPS( 150, 16) >, - < 768000 MHZ_TO_MBPS( 300, 16) >, - < 1478400 MHZ_TO_MBPS( 466, 16) >, - < 1632000 MHZ_TO_MBPS( 600, 16) >; -}; - -&cpu4_cpu_llcc_latmon { - qcom,core-dev-table = - < 300000 MHZ_TO_MBPS( 150, 16) >, - < 710400 MHZ_TO_MBPS( 300, 16) >, - < 1056000 MHZ_TO_MBPS( 466, 16) >, - < 1286400 MHZ_TO_MBPS( 600, 16) >, - < 1804800 MHZ_TO_MBPS( 806, 16) >, - < 2649600 MHZ_TO_MBPS( 933, 16) >, - < 3000000 MHZ_TO_MBPS(1000, 16) >; -}; diff --git a/arch/arm64/boot/dts/qcom/sdmshrike.dtsi b/arch/arm64/boot/dts/qcom/sdmshrike.dtsi index 6444e2578bed9b432127a99e444840c2ddb9a894..50372a88962a2653f3ff2cf272ee356823ae0703 100644 --- a/arch/arm64/boot/dts/qcom/sdmshrike.dtsi +++ b/arch/arm64/boot/dts/qcom/sdmshrike.dtsi @@ -2298,11 +2298,6 @@ }; }; - aop-msg-client { - compatible = "qcom,debugfs-qmp-client"; - mboxes = <&qmp_aop 0>; - mbox-names = "aop"; - }; }; &emac_gdsc { diff --git a/arch/arm64/boot/dts/qcom/sdxprairie-pcie-ep-mtp.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie-pcie-ep-mtp.dtsi index 8fbf342620c16fa7be1a438665780ebd4e9d1c19..f0dfb1eb9a01be40da9bca589d49056a6ee1b841 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie-pcie-ep-mtp.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie-pcie-ep-mtp.dtsi @@ -40,7 +40,3 @@ &mhi_device { status = "ok"; }; - -&mhi_net_device { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/qcom/sdxprairie-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie-pinctrl.dtsi index a5addb26df0ed57ba802fcbc3e9c3017148132df..841e1675dc7a0b3bf4667e2b49206063d58a040b 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie-pinctrl.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie-pinctrl.dtsi @@ -708,7 +708,7 @@ config { pins = "gpio17"; drive-strength = <2>; /* 2 mA */ - bias-disable; /* NO PULL */ + bias-pull-down; /* PULL DOWN */ input-enable; }; }; @@ -1473,32 +1473,5 @@ }; }; - a2b_cdc_sel { - a2b_cdc_sel_default: a2b_cdc_sel_default { - mux { - pins = "gpio97"; - function = "gpio"; - }; - - config { - pins = "gpio97"; - drive-strength = <8>; - bias-disable; - output-high; - }; - }; - }; - - pinctrl_pps: ppsgrp { - mux { - pins = "gpio32"; - function = "nav_gpio"; - }; - - config { - pins = "gpio32"; - bias-pull-down; - }; - }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdxprairie-regulator.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie-regulator.dtsi index 99a5d9774dbd1e5ceceea1ca87f0413aa3503d87..817bef3db90ad5a49e965409b53440a551ff329f 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie-regulator.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie-regulator.dtsi @@ -508,13 +508,4 @@ gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>; enable-active-high; }; - - /* PWR_CTR1_VDD_PA supply */ - vreg_conn_pa: vreg_conn_pa { - compatible = "regulator-fixed"; - regulator-name = "vreg_conn_pa"; - startup-delay-us = <4000>; - enable-active-high; - gpio = <&pmxprairie_gpios 2 GPIO_ACTIVE_HIGH>; - }; }; diff --git a/arch/arm64/boot/dts/qcom/sdxprairie-usb.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie-usb.dtsi index a09c1c50e69a848b0e0789a91737a8d306e906d9..a250c6c4fb7414da5010431ffba92a8cc940b79c 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie-usb.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie-usb.dtsi @@ -54,7 +54,6 @@ 0x240 /* GSI_RING_BASE_ADDR_L */ 0x25c /* GSI_RING_BASE_ADDR_H */ 0x1a4>; /* GSI_IF_STS */ - qcom,gsi-disable-io-coherency; qcom,dwc-usb3-msm-tx-fifo-size = <27696>; qcom,msm-bus,name = "usb"; diff --git a/arch/arm64/boot/dts/qcom/sdxprairie-v2.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie-v2.dtsi index 68f2731612e2d10fe1daf0007e7fd856d720b481..a58b88f7b13df744c71b7889cee74cd0c79758eb 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie-v2.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie-v2.dtsi @@ -26,129 +26,6 @@ status = "okay"; }; -&pcie0 { - qcom,pcie-phy-ver = <2100>; - qcom,phy-sequence = <0x1240 0x03 0x0 - 0x1010 0x00 0x0 - 0x101c 0x31 0x0 - 0x1020 0x01 0x0 - 0x1024 0xce 0x0 - 0x1028 0x0b 0x0 - 0x1030 0x97 0x0 - 0x1034 0x0c 0x0 - 0x1044 0x18 0x0 - 0x1048 0x90 0x0 - 0x1058 0x0f 0x0 - 0x1074 0x06 0x0 - 0x1078 0x06 0x0 - 0x107c 0x16 0x0 - 0x1080 0x16 0x0 - 0x1084 0x36 0x0 - 0x1088 0x36 0x0 - 0x1094 0x08 0x0 - 0x10a4 0x46 0x0 - 0x10a8 0x04 0x0 - 0x10ac 0x04 0x0 - 0x10b0 0x0d 0x0 - 0x10b4 0x0a 0x0 - 0x10b8 0x1a 0x0 - 0x10bc 0xc3 0x0 - 0x10c4 0xd0 0x0 - 0x10d4 0x05 0x0 - 0x10d8 0x55 0x0 - 0x10dc 0x55 0x0 - 0x10e0 0x05 0x0 - 0x110c 0x02 0x0 - 0x1154 0x34 0x0 - 0x1158 0x12 0x0 - 0x115c 0x00 0x0 - 0x1168 0x05 0x0 - 0x116c 0x04 0x0 - 0x119c 0x88 0x0 - 0x11a0 0x03 0x0 - 0x11ac 0xca 0x0 - 0x11b0 0x1e 0x0 - 0x11b4 0xd8 0x0 - 0x11b8 0x20 0x0 - 0x11bc 0x22 0x0 - 0x106c 0x0a 0x0 - 0x1070 0x10 0x0 - 0x11a4 0x17 0x0 - 0x11a8 0x0b 0x0 - 0x0088 0x05 0x0 - 0x008c 0xf6 0x0 - 0x0090 0x13 0x0 - 0x00e0 0x00 0x0 - 0x00c4 0x00 0x0 - 0x0208 0x0c 0x0 - 0x0258 0x16 0x0 - 0x0378 0x44 0x0 - 0x03c8 0x1a 0x0 - 0x03cc 0x5a 0x0 - 0x03d0 0x09 0x0 - 0x03d4 0x37 0x0 - 0x03d8 0xbd 0x0 - 0x03dc 0xf9 0x0 - 0x03e0 0xbf 0x0 - 0x03e4 0xce 0x0 - 0x03e8 0x62 0x0 - 0x03ec 0xbf 0x0 - 0x03f0 0x7d 0x0 - 0x03f4 0xbf 0x0 - 0x03f8 0xcf 0x0 - 0x03fc 0xd6 0x0 - 0x02ac 0x7f 0x0 - 0x0310 0x55 0x0 - 0x0334 0x0c 0x0 - 0x0338 0x00 0x0 - 0x0350 0x08 0x0 - 0x0400 0xa0 0x0 - 0x043c 0x02 0x0 - 0x0888 0x05 0x0 - 0x088c 0xf6 0x0 - 0x0890 0x13 0x0 - 0x08e0 0x00 0x0 - 0x08c4 0x00 0x0 - 0x0a08 0x0c 0x0 - 0x0a58 0x16 0x0 - 0x0b78 0x44 0x0 - 0x0bc8 0x1a 0x0 - 0x0bcc 0x5a 0x0 - 0x0bd0 0x09 0x0 - 0x0bd4 0x37 0x0 - 0x0bd8 0xbd 0x0 - 0x0bdc 0xf9 0x0 - 0x0be0 0xbf 0x0 - 0x0be4 0xce 0x0 - 0x0be8 0x62 0x0 - 0x0bec 0xbf 0x0 - 0x0bf0 0x7d 0x0 - 0x0bf4 0xbf 0x0 - 0x0bf8 0xcf 0x0 - 0x0bfc 0xd6 0x0 - 0x0aac 0x7f 0x0 - 0x0b10 0x55 0x0 - 0x0b34 0x0c 0x0 - 0x0b38 0x00 0x0 - 0x0b50 0x08 0x0 - 0x0c00 0xa0 0x0 - 0x0c3c 0x02 0x0 - 0x161c 0xc1 0x0 - 0x1690 0x00 0x0 - 0x13e0 0x16 0x0 - 0x13e4 0x02 0x0 - 0x1708 0x02 0x0 - 0x16a0 0x17 0x0 - 0x13d8 0x01 0x0 - 0x16fc 0x01 0x0 - 0x16f0 0x13 0x0 - 0x16f4 0x13 0x0 - 0x1e24 0x00 0x0 - 0x1e28 0x00 0x0 - 0x1200 0x00 0x0 - 0x1244 0x03 0x0>; -}; - &clock_gcc { compatible = "qcom,gcc-sdxprairie-v2", "syscon"; }; diff --git a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi index 9da6d91ab44f3597e559560b5668bb0e16bd01a1..9ca2c95b20c8faa3d30857de67bc2cb494021279 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi @@ -691,11 +691,6 @@ }; }; - qcom,mhi_dev_qrtr { - compatible = "qcom,qrtr-mhi-dev"; - qcom,net-id = <3>; - }; - qcom,glinkpkt { compatible = "qcom,glinkpkt"; @@ -1044,9 +1039,9 @@ qcom,cpulist = <&CPU0>; qcom,target-dev = <&cpubw>; qcom,core-dev-table = - < 576000 MHZ_TO_MBPS( 300, 4) >, - < 1497600 MHZ_TO_MBPS(1017, 4) >, - < 1555200 MHZ_TO_MBPS(1804, 4)>; + < 153600 MHZ_TO_MBPS( 300, 4) >, + < 576000 MHZ_TO_MBPS(1017, 4) >, + < 1497600 MHZ_TO_MBPS(1804, 4)>; }; cnss_qca6390: qcom,cnss-qca6390@a0000000 { @@ -1361,12 +1356,6 @@ status = "disabled"; }; - mhi_net_device: qcom,mhi_net_dev { - compatible = "qcom,msm-mhi-dev-net"; - qcom,mhi-ethernet-interface; - status = "disabled"; - }; - sdhc_1: sdhci@8804000 { compatible = "qcom,sdhci-msm-v5"; reg = <0x8804000 0x1000>; @@ -1417,7 +1406,7 @@ qcom,arm-smmu; reg = <0x20000 0x10000>, <0x36000 0x100>, - <0xf100000 0x300000>; + <0x3900000 0x300000>; reg-names = "emac-base", "rgmii-base", "tlmm-central-base"; interrupts-extended = <&pdc 0 62 4>, <&pdc 0 60 4>, <&tlmm 90 2>, <&pdc 0 49 4>, diff --git a/arch/arm64/boot/dts/qcom/sm6150-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/sm6150-pinctrl.dtsi index 037e57511850cd928a9010f5e30595b6d3a41b9b..df5960c939e95c977e070e3420e8f89ccb5a5f1d 100644 --- a/arch/arm64/boot/dts/qcom/sm6150-pinctrl.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150-pinctrl.dtsi @@ -1821,7 +1821,7 @@ pins = "gpio38"; drive-strength = <4>; /* 4 mA */ bias-no-pull; - output-high; + input-enable; }; }; }; @@ -1849,7 +1849,7 @@ pins = "gpio39"; drive-strength = <4>; /* 4 mA */ bias-no-pull; - input-enable; + output-high; }; }; }; @@ -1905,7 +1905,7 @@ pins = "gpio26"; drive-strength = <4>; /* 4 mA */ bias-no-pull; - output-high; + input-enable; }; }; }; @@ -1933,7 +1933,7 @@ pins = "gpio27"; drive-strength = <4>; /* 4 mA */ bias-no-pull; - input-enable; + output-high; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm6150-thermal-overlay.dtsi b/arch/arm64/boot/dts/qcom/sm6150-thermal-overlay.dtsi index 37c22bca3baf872b585b444e55e3433db6f548cc..f47d16937319f90936558fff5b4e5a3a6c7e578e 100644 --- a/arch/arm64/boot/dts/qcom/sm6150-thermal-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150-thermal-overlay.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -125,16 +125,16 @@ }; }; - pm6150-bcl-lvl0 { + pm6150-vbat-lvl0 { cooling-maps { vbat_cpu6 { - trip = <&bcl_lvl0>; + trip = <&vbat_lvl0>; cooling-device = <&CPU6 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; vbat_cpu7 { - trip = <&bcl_lvl0>; + trip = <&vbat_lvl0>; cooling-device = <&CPU7 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; @@ -142,33 +142,16 @@ }; }; - pm6150-bcl-lvl1 { + pm6150-ibat-lvl0 { cooling-maps { ibat_cpu6 { - trip = <&bcl_lvl1>; + trip = <&ibat_lvl0>; cooling-device = <&CPU6 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; ibat_cpu7 { - trip = <&bcl_lvl1>; - cooling-device = - <&CPU7 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - }; - }; - - pm6150-bcl-lvl2 { - cooling-maps { - ibat_cpu6 { - trip = <&bcl_lvl2>; - cooling-device = - <&CPU6 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - ibat_cpu7 { - trip = <&bcl_lvl2>; + trip = <&ibat_lvl0>; cooling-device = <&CPU7 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; diff --git a/arch/arm64/boot/dts/qcom/sm6150-usb.dtsi b/arch/arm64/boot/dts/qcom/sm6150-usb.dtsi index f8a5554f5bee7ecb7bb3347842c11e9a52493aae..29f8858201567720bd58599ba16a657745ea2aba 100644 --- a/arch/arm64/boot/dts/qcom/sm6150-usb.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150-usb.dtsi @@ -55,7 +55,6 @@ 0x130 /* GSI_RING_BASE_ADDR_L */ 0x144 /* GSI_RING_BASE_ADDR_H */ 0x1a4>; /* GSI_IF_STS */ - qcom,gsi-disable-io-coherency; qcom,dwc-usb3-msm-tx-fifo-size = <21288>; qcom,pm-qos-latency = <61>; diff --git a/arch/arm64/boot/dts/qcom/sm8150-audio.dtsi b/arch/arm64/boot/dts/qcom/sm8150-audio.dtsi index 32e1ec1a75b7f676203f9145d4beb464247b2f2b..a94883687fdf9504d007eaae60b789c366ec3c56 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-audio.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-audio.dtsi @@ -157,9 +157,9 @@ &qupv3_se4_i2c { status = "ok"; - fsa4480: fsa4480@43 { + fsa4480: fsa4480@42 { compatible = "qcom,fsa4480-i2c"; - reg = <0x43>; + reg = <0x42>; pinctrl-names = "default"; pinctrl-0 = <&fsa_usbc_ana_en>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8150-camera-sensor-mtp.dtsi b/arch/arm64/boot/dts/qcom/sm8150-camera-sensor-mtp.dtsi index 2bd902951c542ff1e100b4979b615e55c8947e79..7de91fecbd1c757381ee26c5123b9275a724781d 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-camera-sensor-mtp.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-camera-sensor-mtp.dtsi @@ -112,6 +112,7 @@ actuator_triple_rear_aux2_regulator: gpio-regulator@6 { compatible = "regulator-fixed"; + status = "disable"; reg = <0x06 0x00>; regulator-name = "actuator_triple_rear_aux2_regulator"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm64/boot/dts/qcom/sm8150-camera.dtsi b/arch/arm64/boot/dts/qcom/sm8150-camera.dtsi index c20f5a7b7eebac7ac59b25a4d19727daedd1b8f5..51944ac4c0cbddee54de4657ecdc2bf57bcf8e60 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-camera.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-camera.dtsi @@ -387,10 +387,10 @@ }; iova-mem-region-shared { - /* Shared region is 100MB long */ + /* Shared region is 200MB long */ iova-region-name = "shared"; iova-region-start = <0x7400000>; - iova-region-len = <0x6400000>; + iova-region-len = <0xc800000>; iova-region-id = <0x1>; status = "ok"; }; @@ -398,7 +398,7 @@ iova-mem-region-secondary-heap { /* Secondary heap region is 1MB long */ iova-region-name = "secheap"; - iova-region-start = <0xd800000>; + iova-region-start = <0x13C00000>; iova-region-len = <0x100000>; iova-region-id = <0x4>; status = "ok"; @@ -407,8 +407,8 @@ iova-mem-region-io { /* IO region is approximately 3 GB */ iova-region-name = "io"; - iova-region-start = <0xda00000>; - iova-region-len = <0xace00000>; + iova-region-start = <0x13E00000>; + iova-region-len = <0xa6a00000>; iova-region-id = <0x3>; status = "ok"; }; @@ -416,7 +416,7 @@ iova-mem-qdss-region { /* QDSS region is appropriate 1MB */ iova-region-name = "qdss"; - iova-region-start = <0xd900000>; + iova-region-start = <0x13D00000>; iova-region-len = <0x100000>; iova-region-id = <0x5>; qdss-phy-addr = <0x16790000>; diff --git a/arch/arm64/boot/dts/qcom/sm8150-mhi.dtsi b/arch/arm64/boot/dts/qcom/sm8150-mhi.dtsi index ee8c5a375547a7e335d8b7672408ce2f01ed4205..9f53e564ccdffd48229c50ee476312a5c02e35ba 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-mhi.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-mhi.dtsi @@ -546,11 +546,6 @@ mhi,mru = <0x8000>; mhi,rsc-parent = <&mhi_netdev_0>; }; - - mhi_qrtr { - mhi,chan = "IPCR"; - mhi,early-notify; - }; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dtsi b/arch/arm64/boot/dts/qcom/sm8150-mtp.dtsi index fa4cc5656e30c62f4a9be41c04bf17688a8cdf32..54c520d0981d1e3256121f585bfb344f8d9a15c5 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-mtp.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-mtp.dtsi @@ -53,7 +53,8 @@ extcon_usb1: extcon_usb1 { compatible = "linux,extcon-usb-gpio"; - vbus-gpio = <&pm8150_gpios 10 GPIO_ACTIVE_HIGH>; + /*pm8150_gpios 10 is for step motor, use the dummy gpio 165 for driver probe */ + vbus-gpio = <&tlmm 165 GPIO_ACTIVE_HIGH>; id-gpio = <&tlmm 101 GPIO_ACTIVE_HIGH>; vbus-out-gpio = <&pm8150_gpios 9 GPIO_ACTIVE_HIGH>; @@ -95,7 +96,7 @@ }; }; - qcom,qbt1000 { + qcomqbt1000:qcom,qbt1000 { compatible = "qcom,qbt1000"; clock-names = "core", "iface"; clock-frequency = <25000000>; @@ -323,8 +324,9 @@ qcom,fg-esr-timer-dischg-fast = <0 7>; qcom,fg-esr-timer-chg-slow = <0 96>; qcom,fg-esr-timer-dischg-slow = <0 96>; - qcom,fg-esr-cal-soc-thresh = <26 230>; - qcom,fg-esr-cal-temp-thresh = <10 40>; + /*op disable ers calibration*/ + /*qcom,fg-esr-cal-soc-thresh = <26 230>;*/ + /*qcom,fg-esr-cal-temp-thresh = <10 40>;*/ }; &sdhc_2 { @@ -602,18 +604,10 @@ }; skin-msm-therm { - polling-delay-passive = <0>; + polling-delay-passive = <2000>; polling-delay = <0>; - thermal-governor = "user_space"; + thermal-governor = "step_wise"; thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM2_PU2>; - wake-capable-sensor; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - }; }; pa-therm2 { @@ -649,7 +643,7 @@ "usb_in_voltage"; qcom,battery-data = <&mtp_batterydata>; qcom,step-charging-enable; - qcom,sw-jeita-enable; + //qcom,sw-jeita-enable; qcom,wd-bark-time-secs = <16>; qcom,suspend-input-on-debug-batt; }; diff --git a/arch/arm64/boot/dts/qcom/sm8150-oem-camera-guacamoleb.dtsi b/arch/arm64/boot/dts/qcom/sm8150-oem-camera-guacamoleb.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..0647e8ebf67743795536d3a2617c6606ab98b828 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8150-oem-camera-guacamoleb.dtsi @@ -0,0 +1,889 @@ +/*this is for camera dtsi*/ +&pm8150l_gpios{ + cam_sensor_pmi_gpio { + + cam_sensor_rear_1_dvdd_active: cam_sensor_rear_1_dvdd_active { + pins = "gpio2"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_rear_1_dvdd_suspend: cam_sensor_rear_1_dvdd_suspend { + pins = "gpio2"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + + }; + + cam_sensor_front_0_ana { + cam_sensor_front_0_ana_active: cam_sensor_front_0_ana_active { + pins = "gpio12"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_front_0_ana_suspend: cam_sensor_front_0_ana_suspend { + pins = "gpio12"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; + + cam_sensor_front_0_dvdd { + cam_sensor_front_0_dvdd_active: cam_sensor_front_0_dvdd_active { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_front_0_dvdd_suspend: cam_sensor_front_0_dvdd_suspend { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; + +}; + +&soc { + led_flash_rear_0: qcom,camera-flash@0 { + cell-index = <0>; + reg = <0x00 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + + led_flash_rear_1: qcom,camera-flash@1 { + cell-index = <1>; + reg = <0x01 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; +}; + +&cam_cci0 { + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + shared-gpios = <14 13>; + pinctrl-names = "cam_res_mgr_default", "cam_res_mgr_suspend"; + status = "ok"; + pinctrl-0 = <&cam_sensor_rear_0_mclk_active + &cam_sensor_rear_1_mclk_active>; + pinctrl-1 = <&cam_sensor_rear_0_mclk_suspend + &cam_sensor_rear_1_mclk_suspend>; + }; + + actuator_rear_0: qcom,actuator@7 { + cell-index = <7>; + reg = <0x7>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <1>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_vaf_active>; + pinctrl-1 = <&cam_sensor_rear_0_vaf_suspend>; + gpios = <&tlmm 35 0>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_0"; + }; + + actuator_rear_1: qcom,actuator@8 { + cell-index = <8>; + reg = <0x8>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <0>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_vaf_active>; + pinctrl-1 = <&cam_sensor_rear_0_vaf_suspend>; + gpios = <&tlmm 35 0>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_1"; + }; + + ois_rear_0: qcom,ois@2 { + cell-index = <2>; + reg = <2>; + compatible = "qcom,ois"; + cam_vio-supply = <&pm8150l_l1>; + cam_vdig-supply = <&pm8150l_s8>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vio", "cam_vdig", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1352000 3300000>; + rgltr-max-voltage = <0 1352000 3300000>; + rgltr-load-current = <0 1100000 0>; + gpio-no-mux = <0>; + use-shared-clk; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_ois_active + &cam_sensor_rear_0_dvdd_active>; + pinctrl-1 = <&cam_sensor_rear_0_ois_suspend + &cam_sensor_rear_0_dvdd_suspend>; + gpios = <&tlmm 87 0>, + <&tlmm 24 0>; + gpio-vaf = <0>; + gpio-vdig = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <0 0>; + gpio-req-tbl-label = "OIS_REAR_0", + "CAM_VDIG"; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + }; + + ois_rear_1: qcom,ois@1 { + }; + + eeprom_rear_0: qcom,eeprom@7 { + cell-index = <7>; + reg = <7>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_s8>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1352000 0>; + rgltr-max-voltage = <0 3300000 1352000 0>; + rgltr-load-current = <0 80000 1100000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_rest_active + &cam_sensor_rear_0_ana_active + &cam_sensor_rear_0_dvdd_active>; + pinctrl-1 = <&cam_sensor_rear_0_rest_suspend + &cam_sensor_rear_0_ana_suspend + &cam_sensor_rear_0_dvdd_suspend>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 11 0>, + <&tlmm 24 0>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET0", + "CAM_VANA_0", + "CAM_VDIG_0"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_rear_1: qcom,eeprom@8 { + cell-index = <8>; + reg = <8>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150_s4>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1800000 0>; + rgltr-max-voltage = <0 3300000 1800000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_rest_active + &cam_sensor_rear_1_ana_active + &cam_sensor_rear_1_dvdd_active + &cam_sensor_rear_0_ois_active>; + pinctrl-1 = <&cam_sensor_rear_1_rest_suspend + &cam_sensor_rear_1_ana_suspend + &cam_sensor_rear_1_dvdd_suspend + &cam_sensor_rear_0_ois_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>, + <&tlmm 148 0>, + <&pm8150l_gpios 2 GPIO_ACTIVE_HIGH>, + <&tlmm 87 0>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-custom1 = <4>; + gpio-req-tbl-num = <0 1 2 3 0>; + gpio-req-tbl-flags = <1 0 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET1", + "CAM_VANA_1", + "CAM_VDIG_1", + "OIS_REAR_0"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_front_0: qcom,eeprom@9 { + cell-index = <9>; + reg = <9>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_s8>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1352000 0>; + rgltr-max-voltage = <0 3300000 1352000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_front_0_mclk_active + &cam_sensor_front_0_rest_active + &cam_sensor_front_0_ana_active + &cam_sensor_front_0_dvdd_active>; + pinctrl-1 = <&cam_sensor_front_0_mclk_suspend + &cam_sensor_front_0_rest_suspend + &cam_sensor_front_0_ana_suspend + &cam_sensor_front_0_dvdd_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>, + <&pm8150l_gpios 12 GPIO_ACTIVE_HIGH>, + <&pm8150l_gpios 1 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA_2", + "CAM_VDIG_2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear_0>; + actuator-src = <&actuator_rear_0>; + ois-src = <&ois_rear_0>; + eeprom-src = <&eeprom_rear_0>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_s8>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1352000 0>; + rgltr-max-voltage = <0 3300000 1352000 0>; + rgltr-load-current = <0 80000 1100000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_rest_active + &cam_sensor_rear_0_ana_active + &cam_sensor_rear_0_ana2_active + &cam_sensor_rear_0_pvdd_active + &cam_sensor_rear_0_dvdd_active>; + pinctrl-1 = <&cam_sensor_rear_0_rest_suspend + &cam_sensor_rear_0_ana_suspend + &cam_sensor_rear_0_ana2_suspend + &cam_sensor_rear_0_pvdd_suspend + &cam_sensor_rear_0_dvdd_suspend>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 11 0>, + <&tlmm 29 0>, + <&tlmm 25 0>, + <&tlmm 24 0>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-custom1 = <3>; + gpio-custom2 = <4>; + gpio-vdig = <5>; + gpio-req-tbl-num = <0 1 2 3 4 5>; + gpio-req-tbl-flags = <1 0 0 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET0", + "CAM_VANA_0", + "CAM_VANA2_0", + "CAM_PVDD", + "CAM_VDIG"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + reg = <0x1>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear_1>; + eeprom-src = <&eeprom_rear_1>;//for imx586&s5k3m5 use same eeprom located on master imx586 + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150_s4>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1800000 0>; + rgltr-max-voltage = <0 3300000 1800000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_rest_active + &cam_sensor_rear_1_ana_active + &cam_sensor_rear_1_dvdd_active>; + pinctrl-1 = <&cam_sensor_rear_1_rest_suspend + &cam_sensor_rear_1_ana_suspend + &cam_sensor_rear_1_dvdd_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>, + <&tlmm 148 0>, + <&pm8150l_gpios 2 GPIO_ACTIVE_HIGH>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET1", + "CAM_VANA_1", + "CAM_VDIG_1"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front_0>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_s8>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1352000 0>; + rgltr-max-voltage = <0 3300000 1352000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_front_0_mclk_active + &cam_sensor_front_0_rest_active + &cam_sensor_front_0_ana_active + &cam_sensor_front_0_dvdd_active>; + pinctrl-1 = <&cam_sensor_front_0_mclk_suspend + &cam_sensor_front_0_rest_suspend + &cam_sensor_front_0_ana_suspend + &cam_sensor_front_0_dvdd_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>, + <&pm8150l_gpios 12 GPIO_ACTIVE_HIGH>, + <&pm8150l_gpios 1 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA_2", + "CAM_VDIG_2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; +}; +&tlmm { + cam_sensor_rear_0_mclk_active: cam_sensor_rear_0_mclk_active { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_mclk_suspend: cam_sensor_rear_0_mclk_suspend { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_rest_active: cam_sensor_rear_0_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_rest_suspend: cam_sensor_rear_0_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana_active: cam_sensor_rear_0_ana_active { + /* VANA */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana_suspend: cam_sensor_rear_0_ana_suspend { + /* VANA */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana2_active: cam_sensor_rear_0_ana2_active { + /* VANA */ + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana2_suspend: cam_sensor_rear_0_ana2_suspend { + /* VANA */ + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_pvdd_active: cam_sensor_rear_0_pvdd_active { + /* PVDD */ + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_pvdd_suspend: cam_sensor_rear_0_pvdd_suspend { + /* PVDD */ + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_dvdd_active: cam_sensor_rear_0_dvdd_active { + /* VDIG */ + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_dvdd_suspend: cam_sensor_rear_0_dvdd_suspend { + /* VDIG */ + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + + cam_sensor_rear_0_vaf_active: cam_sensor_rear_0_vaf_active { + /* AF */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_vaf_suspend: cam_sensor_rear_0_vaf_suspend { + /* AF */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ois_active: cam_sensor_rear_0_ois_active { + /* OIS */ + mux { + pins = "gpio87"; + function = "gpio"; + }; + + config { + pins = "gpio87"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ois_suspend: cam_sensor_rear_0_ois_suspend { + /* OIS */ + mux { + pins = "gpio87"; + function = "gpio"; + }; + + config { + pins = "gpio87"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + + cam_sensor_rear_1_mclk_active: cam_sensor_rear_1_mclk_active { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_mclk_suspend: cam_sensor_rear_1_mclk_suspend { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_rest_active: cam_sensor_rear_1_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_rest_suspend: cam_sensor_rear_1_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_ana_active: cam_sensor_rear_1_ana_active { + /* VANA */ + mux { + pins = "gpio148"; + function = "gpio"; + }; + + config { + pins = "gpio148"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_ana_suspend: cam_sensor_rear_1_ana_suspend { + /* VANA */ + mux { + pins = "gpio148"; + function = "gpio"; + }; + + config { + pins = "gpio148"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_vaf_active: cam_sensor_rear_1_vaf_active { + /* ACTUATOR POWER */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_vaf_suspend: cam_sensor_rear_1_vaf_suspend { + /* ACTUATOR POWER */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_mclk_active: cam_sensor_front_0_mclk_active { + /* MCLK2 */ + mux { + /* CLK, DATA */ + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_mclk_suspend: cam_sensor_front_0_mclk_suspend { + /* MCLK2 */ + mux { + /* CLK, DATA */ + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_rest_active: cam_sensor_front_0_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_rest_suspend: cam_sensor_front_0_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + +}; diff --git a/arch/arm64/boot/dts/qcom/sm8150-oem-camera-hotdogb-t0.dtsi b/arch/arm64/boot/dts/qcom/sm8150-oem-camera-hotdogb-t0.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..3063851271b0c764370b50d20546f98a0f662bb0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8150-oem-camera-hotdogb-t0.dtsi @@ -0,0 +1,999 @@ +&pm8150l_gpios{ + cam_sensor_pmi_gpio { + cam_sensor_rear_0_dvdd_active: cam_sensor_rear_0_dvdd_active { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_rear_0_dvdd_suspend: cam_sensor_rear_0_dvdd_suspend { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + + cam_sensor_rear_2_ana_active: cam_sensor_rear_2_ana_active { + pins = "gpio2"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_rear_2_ana_suspend: cam_sensor_rear_2_ana_suspend { + pins = "gpio2"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + + cam_sensor_rear_2_af_active: cam_sensor_rear_2_af_active { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_rear_2_af_suspend: cam_sensor_rear_2_af_suspend { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; + + cam_sensor_front_0_ana { + cam_sensor_front_0_ana_active: cam_sensor_front_0_ana_active { + pins = "gpio12"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_front_0_ana_suspend: cam_sensor_front_0_ana_suspend { + pins = "gpio12"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; +}; + +&soc { + led_flash_rear_0: qcom,camera-flash@7 { + cell-index = <7>; + reg = <0x07 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_rear_1: qcom,camera-flash@8 { + cell-index = <8>; + reg = <0x08 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_rear_2: qcom,camera-flash@9 { + cell-index = <9>; + reg = <0x09 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; +}; + +&cam_cci0 { + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + shared-gpios = <14 13>; + pinctrl-names = "cam_res_mgr_default", "cam_res_mgr_suspend"; + status = "ok"; + pinctrl-0 = <&cam_sensor_rear_0_mclk_active + &cam_sensor_rear_1_mclk_active>; + pinctrl-1 = <&cam_sensor_rear_0_mclk_suspend + &cam_sensor_rear_1_mclk_suspend>; + }; + + actuator_rear_0: qcom,actuator@7 { + cell-index = <7>; + reg = <0x7>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <1>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_vaf_active>; + pinctrl-1 = <&cam_sensor_rear_0_vaf_suspend>; + gpios = <&tlmm 25 0>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_0"; + }; + + actuator_rear_1: qcom,actuator@8 { + cell-index = <8>; + reg = <0x8>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <0>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_vaf_active>; + pinctrl-1 = <&cam_sensor_rear_1_vaf_suspend>; + gpios = <&tlmm 35 0>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_1"; + }; + + actuator_rear_2: qcom,actuator@9 { + cell-index = <9>; + reg = <0x9>; + compatible = "qcom,actuator"; + cci-device = <1>; + cci-master = <1>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_2_af_active>; + pinctrl-1 = <&cam_sensor_rear_2_af_suspend>; + gpios = <&pm8150l_gpios 4 GPIO_ACTIVE_HIGH>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_1"; + }; + + ois_rear_0: qcom,ois@2 { + cell-index = <2>; + reg = <2>; + compatible = "qcom,ois"; + cam_vio-supply = <&pm8150l_l1>; + cam_vdig-supply = <&pm8009_l6>; + cam_vaf-supply = <&pm8009_l5>; + regulator-names = "cam_vio", "cam_vdig", "cam_vaf", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 2856000 2800000 0>; + rgltr-max-voltage = <0 2856000 2800000 0>; + rgltr-load-current = <0 80000 0 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_front_0_mclk_active>; + pinctrl-1 = <&cam_sensor_front_0_mclk_suspend>; + gpios = <&tlmm 15 0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <1>; + gpio-req-tbl-label = "CAMIF_MCLK2"; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + ois_rear_1: qcom,ois@3 { + cell-index = <3>; + reg = <3>; + compatible = "qcom,ois"; + cam_vio-supply = <&pm8150l_l1>; + cam_vdig-supply = <&pm8009_l5>;//imx586 ois + cam_vaf-supply = <&pm8009_l6>; + regulator-names = "cam_vio", "cam_vdig", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 2800000 2856000>; + rgltr-max-voltage = <0 2800000 2856000>; + rgltr-load-current = <0 80000 0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + }; + + eeprom_rear_0: qcom,eeprom@7 { + cell-index = <7>; + reg = <7>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1104000 0>; + rgltr-max-voltage = <0 3300000 1104000 0>; + rgltr-load-current = <0 80000 1100000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_rest_active + &cam_sensor_rear_0_ana_active>; + pinctrl-1 = <&cam_sensor_rear_0_rest_suspend + &cam_sensor_rear_0_ana_suspend>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 11 0>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET0", + "CAM_VANA_0"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_rear_1: qcom,eeprom@8 { + cell-index = <8>; + reg = <8>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1056000 0>; + rgltr-max-voltage = <0 3300000 1056000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_rest_active + &cam_sensor_rear_1_ana_active>; + pinctrl-1 = <&cam_sensor_rear_1_rest_suspend + &cam_sensor_rear_1_ana_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>, + <&tlmm 148 0>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET1", + "CAM_VANA_1"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_front_0: qcom,eeprom@9 { + cell-index = <9>; + reg = <9>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l3>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1056000 0>; + rgltr-max-voltage = <0 3300000 1056000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_front_0_mclk_active + &cam_sensor_front_0_rest_active + &cam_sensor_front_0_ana_active>; + pinctrl-1 = <&cam_sensor_front_0_mclk_suspend + &cam_sensor_front_0_rest_suspend + &cam_sensor_front_0_ana_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>, + <&pm8150l_gpios 12 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA_2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_rear_2: qcom,eeprom@10 { + cell-index = <10>; + reg = <0xA>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l4>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1056000 0>; + rgltr-max-voltage = <0 3300000 1056000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_2_mclk_active + &cam_sensor_rear_2_rest_active + &cam_sensor_rear_2_ana_active>; + pinctrl-1 = <&cam_sensor_rear_2_mclk_suspend + &cam_sensor_rear_2_rest_suspend + &cam_sensor_rear_2_ana_suspend>; + gpios = <&tlmm 16 0>, + <&tlmm 23 0>, + <&pm8150l_gpios 2 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2 >; + gpio-req-tbl-flags = <1 0 0 >; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3", + "CAM_VANA_3"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear_0>; + actuator-src = <&actuator_rear_0>; + ois-src = <&ois_rear_0>; + eeprom-src = <&eeprom_rear_0>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1104000 0>; + rgltr-max-voltage = <0 3300000 1104000 0>; + rgltr-load-current = <0 80000 1100000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_rest_active + &cam_sensor_rear_0_ana_active + &cam_sensor_rear_0_ana2_active + &cam_sensor_rear_0_dvdd_active>; + pinctrl-1 = <&cam_sensor_rear_0_rest_suspend + &cam_sensor_rear_0_ana_suspend + &cam_sensor_rear_0_ana2_suspend + &cam_sensor_rear_0_dvdd_suspend>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 11 0>, + <&tlmm 29 0>, + <&pm8150l_gpios 1 GPIO_ACTIVE_HIGH>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-custom1 = <3>; + gpio-custom2 = <4>; + gpio-req-tbl-num = <0 1 2 3 4>; + gpio-req-tbl-flags = <1 0 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET0", + "CAM_VANA_0", + "CAM_VANA2_0", + "CAM_PVDD"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + reg = <0x1>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear_1>; + led-flash-src = <&led_flash_rear_1>; + eeprom-src = <&eeprom_rear_1>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1056000 0>; + rgltr-max-voltage = <0 3300000 1056000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_rest_active + &cam_sensor_rear_1_ana_active>; + pinctrl-1 = <&cam_sensor_rear_1_rest_suspend + &cam_sensor_rear_1_ana_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>, + <&tlmm 148 0>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET1", + "CAM_VANA_1"; + sensor-mode = <0>; + sensor-eeprom-same-cci = <1>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front_0>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l3>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1056000 0>; + rgltr-max-voltage = <0 3300000 1056000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_front_0_mclk_active + &cam_sensor_front_0_rest_active + &cam_sensor_front_0_ana_active>; + pinctrl-1 = <&cam_sensor_front_0_mclk_suspend + &cam_sensor_front_0_rest_suspend + &cam_sensor_front_0_ana_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>, + <&pm8150l_gpios 12 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA_2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + reg = <0x03>; + csiphy-sd-index = <3>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + led-flash-src = <&led_flash_rear_2>; + eeprom-src = <&eeprom_rear_2>; + actuator-src = <&actuator_rear_2>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l4>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1056000 0>; + rgltr-max-voltage = <0 3300000 1056000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_2_mclk_active + &cam_sensor_rear_2_rest_active + &cam_sensor_rear_2_ana_active>; + pinctrl-1 = <&cam_sensor_rear_2_mclk_suspend + &cam_sensor_rear_2_rest_suspend + &cam_sensor_rear_2_ana_suspend>; + gpios = <&tlmm 16 0>, + <&tlmm 23 0>, + <&pm8150l_gpios 2 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2 >; + gpio-req-tbl-flags = <1 0 0 >; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3", + "CAM_VANA_3"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; +}; + +&tlmm { + cam_sensor_rear_0_mclk_active: cam_sensor_rear_0_mclk_active { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_mclk_suspend: cam_sensor_rear_0_mclk_suspend { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_rest_active: cam_sensor_rear_0_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_rest_suspend: cam_sensor_rear_0_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana_active: cam_sensor_rear_0_ana_active { + /* VANA */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana_suspend: cam_sensor_rear_0_ana_suspend { + /* VANA */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana2_active: cam_sensor_rear_0_ana2_active { + /* VANA */ + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana2_suspend: cam_sensor_rear_0_ana2_suspend { + /* VANA */ + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_vaf_active: cam_sensor_rear_0_vaf_active { + /* AF */ + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_vaf_suspend: cam_sensor_rear_0_vaf_suspend { + /* AF */ + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_mclk_active: cam_sensor_rear_1_mclk_active { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_mclk_suspend: cam_sensor_rear_1_mclk_suspend { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_rest_active: cam_sensor_rear_1_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_rest_suspend: cam_sensor_rear_1_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_ana_active: cam_sensor_rear_1_ana_active { + /* VANA */ + mux { + pins = "gpio148"; + function = "gpio"; + }; + + config { + pins = "gpio148"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_ana_suspend: cam_sensor_rear_1_ana_suspend { + /* VANA */ + mux { + pins = "gpio148"; + function = "gpio"; + }; + + config { + pins = "gpio148"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_vaf_active: cam_sensor_rear_1_vaf_active { + /* ACTUATOR POWER */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_vaf_suspend: cam_sensor_rear_1_vaf_suspend { + /* ACTUATOR POWER */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_mclk_active: cam_sensor_front_0_mclk_active { + /* MCLK2 */ + mux { + /* CLK, DATA */ + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_mclk_suspend: cam_sensor_front_0_mclk_suspend { + /* MCLK2 */ + mux { + /* CLK, DATA */ + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_rest_active: cam_sensor_front_0_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_rest_suspend: cam_sensor_front_0_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_2_mclk_active: cam_sensor_rear_2_mclk_active { + /* MCLK3 */ + mux { + /* CLK, DATA */ + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_2_mclk_suspend: cam_sensor_rear_2_mclk_suspend { + /* MCLK3 */ + mux { + /* CLK, DATA */ + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_2_rest_active: cam_sensor_rear_2_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_2_rest_suspend: cam_sensor_rear_2_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_laser_pwren_active: cam_sensor_laser_pwren_active { + /* RESET, STANDBY */ + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_laser_pwren_suspend: cam_sensor_laser_pwren_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8150-oem-camera-ov.dtsi b/arch/arm64/boot/dts/qcom/sm8150-oem-camera-ov.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..c8f15fd08a0784df96e81203b1c2e57784a5b3a8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8150-oem-camera-ov.dtsi @@ -0,0 +1,854 @@ +&pm8150_gpios{ + cam_sensor_front_0_dig { + cam_sensor_front_0_dig_active: cam_sensor_front_0_dig_active { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_front_0_dig_suspend: cam_sensor_front_0_dig_suspend{ + pins = "gpio1"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; +}; + +&pm8150l_gpios{ + cam_sensor_tof_pmi_gpio { + cam_sensor_tof_ana_active: cam_sensor_tof_ana_active { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_tof_ana_suspend: cam_sensor_tof_ana_suspend { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + + cam_sensor_tof_dig_active: cam_sensor_tof_dig_active { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_tof_dig_suspend: cam_sensor_tof_dig_suspend { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + + cam_sensor_tof_vcc_active: cam_sensor_tof_vcc_active { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_tof_vcc_suspend: cam_sensor_tof_vcc_suspend { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + + cam_sensor_tof_lvcc_active: cam_sensor_tof_lvcc_active { + pins = "gpio2"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_tof_lvcc_suspend: cam_sensor_tof_lvcc_suspend { + pins = "gpio2"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; + + cam_sensor_front_0_ana { + cam_sensor_front_0_ana_active: cam_sensor_front_0_ana_active { + pins = "gpio12"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_front_0_ana_suspend: cam_sensor_front_0_ana_suspend { + pins = "gpio12"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; +}; + +&soc { + actuator_rear_1: qcom,actuator@8 { + cell-index = <8>; + reg = <0x8>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <0>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_vaf_active>; + pinctrl-1 = <&cam_sensor_rear_1_vaf_suspend>; + gpios = <&tlmm 35 0>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_1"; + }; + + actuator_rear_0: qcom,actuator@7 { + cell-index = <7>; + reg = <0x7>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <1>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_vaf_active>; + pinctrl-1 = <&cam_sensor_rear_0_vaf_suspend>; + gpios = <&tlmm 29 0>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_0"; + }; + + eeprom_rear_0: qcom,eeprom@7 { + cell-index = <7>; + reg = <7>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1000000 0>; + rgltr-max-voltage = <0 3300000 1200000 0>; + rgltr-load-current = <0 80000 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_mclk_active + &cam_sensor_rear_0_rest_active + &cam_sensor_rear_0_ana_active + &cam_sensor_rear_0_dig_active>; + pinctrl-1 = <&cam_sensor_rear_0_mclk_suspend + &cam_sensor_rear_0_rest_suspend + &cam_sensor_rear_0_ana_suspend + &cam_sensor_rear_0_dig_suspend>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 11 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET0", + "CAM_VANA_0", + "CAM_DIG_0"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_rear_1: qcom,eeprom@8 { + cell-index = <8>; + reg = <8>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1000000 0>; + rgltr-max-voltage = <0 3300000 1200000 0>; + rgltr-load-current = <0 80000 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_mclk_active + &cam_sensor_rear_1_rest_active + &cam_sensor_rear_1_ana_active + &cam_sensor_rear_1_dig_active>; + pinctrl-1 = <&cam_sensor_rear_1_mclk_suspend + &cam_sensor_rear_1_rest_suspend + &cam_sensor_rear_1_ana_suspend + &cam_sensor_rear_1_dig_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>, + <&tlmm 148 0>, + <&tlmm 26 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET1", + "CAM_VANA_1", + "CAM_DIG_1"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_front_0: qcom,eeprom@9 { + cell-index = <9>; + reg = <9>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l3>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1000000 0>; + rgltr-max-voltage = <0 3300000 1200000 0>; + rgltr-load-current = <0 80000 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_front_0_mclk_active + &cam_sensor_front_0_rest_active + &cam_sensor_front_0_ana_active + &cam_sensor_front_0_dig_active>; + pinctrl-1 = <&cam_sensor_front_0_mclk_suspend + &cam_sensor_front_0_rest_suspend + &cam_sensor_front_0_ana_suspend + &cam_sensor_front_0_dig_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>, + <&pm8150l_gpios 12 GPIO_ACTIVE_HIGH>, + <&pm8150_gpios 1 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA_2", + "CAM_DIG_2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_rear_tof: qcom,eeprom@10 { + cell-index = <10>; + reg = <0xA>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 0>; + rgltr-max-voltage = <0 0>; + rgltr-load-current = <0 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_tof_mclk_active + &cam_sensor_tof_rest_active>; + pinctrl-1 = <&cam_sensor_tof_mclk_suspend + &cam_sensor_tof_rest_suspend>; + gpios = <&tlmm 16 0>, + <&tlmm 23 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear>; + actuator-src = <&actuator_rear_0>; + //ois-src = <&ois_rear>; + //eeprom-src = <&eeprom_rear>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_bob>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 3300000 0>; + rgltr-max-voltage = <0 3300000 3300000 0>; + rgltr-load-current = <0 80000 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_mclk_active + &cam_sensor_rear_0_rest_active + &cam_sensor_rear_0_ana_active + &cam_sensor_rear_0_dig_active>; + pinctrl-1 = <&cam_sensor_rear_0_mclk_suspend + &cam_sensor_rear_0_rest_suspend + &cam_sensor_rear_0_ana_suspend + &cam_sensor_rear_0_dig_suspend>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&pm8150l_gpios 4 GPIO_ACTIVE_HIGH>, + <&pm8150l_gpios 2 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET0", + "CAM_VANA_0", + "CAM_DIG_0"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + //eeprom-src = <&eeprom_front>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_bob>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 3300000 0>; + rgltr-max-voltage = <0 3300000 3300000 0>; + rgltr-load-current = <0 80000 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_front_0_mclk_active + &cam_sensor_front_0_rest_active + &cam_sensor_front_0_ana_active + &cam_sensor_front_0_dig_active>; + pinctrl-1 = <&cam_sensor_front_0_mclk_suspend + &cam_sensor_front_0_rest_suspend + &cam_sensor_front_0_ana_suspend + &cam_sensor_front_0_dig_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>, + <&pm8150l_gpios 4 GPIO_ACTIVE_HIGH>, + <&pm8150l_gpios 1 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA_2", + "CAM_DIG_2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + //laser start + stmvl53l1: st,stmvl53l1@0 { + compatible = "st,stmvl53l1"; + //reg = <0x29>; + //avdd-supply = <&pm8150l_bob>; + laser_vdd-supply = <&pm8150l_l1>; + //pinctrl-names = "laser_default", "laser_suspend"; + //pinctrl-0 = <&stm_laser_pwren_active>; + //pinctrl-1 = <&stm_laser_pwren_suspend>; + xsdn-gpio = <24>; + pwren-gpio = <26>; + intr-gpio = <131>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + }; +//laser end +}; + +&tlmm { + cam_sensor_rear_0_mclk_active: cam_sensor_rear_0_mclk_active { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_mclk_suspend: cam_sensor_rear_0_mclk_suspend { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_rest_active: cam_sensor_rear_0_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_rest_suspend: cam_sensor_rear_0_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana_active: cam_sensor_rear_0_ana_active { + /* VANA */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana_suspend: cam_sensor_rear_0_ana_suspend { + /* VANA */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_dig_active: cam_sensor_rear_0_dig_active { + /* DIG */ + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_dig_suspend: cam_sensor_rear_0_dig_suspend { + /* DIG */ + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_vaf_active: cam_sensor_rear_0_vaf_active { + /* DIG */ + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_vaf_suspend: cam_sensor_rear_0_vaf_suspend { + /* DIG */ + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_mclk_active: cam_sensor_rear_1_mclk_active { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_mclk_suspend: cam_sensor_rear_1_mclk_suspend { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_rest_active: cam_sensor_rear_1_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_rest_suspend: cam_sensor_rear_1_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_ana_active: cam_sensor_rear_1_ana_active { + /* VANA */ + mux { + pins = "gpio148"; + function = "gpio"; + }; + + config { + pins = "gpio148"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_ana_suspend: cam_sensor_rear_1_ana_suspend { + /* VANA */ + mux { + pins = "gpio148"; + function = "gpio"; + }; + + config { + pins = "gpio148"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_vaf_active: cam_sensor_rear_1_vaf_active { + /* ACTUATOR POWER */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_vaf_suspend: cam_sensor_rear_1_vaf_suspend { + /* ACTUATOR POWER */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_dig_active: cam_sensor_rear_1_dig_active { + /* DIG */ + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_dig_suspend: cam_sensor_rear_1_dig_suspend { + /* DIG */ + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_mclk_active: cam_sensor_front_0_mclk_active { + /* MCLK2 */ + mux { + /* CLK, DATA */ + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_mclk_suspend: cam_sensor_front_0_mclk_suspend { + /* MCLK2 */ + mux { + /* CLK, DATA */ + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_rest_active: cam_sensor_front_0_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_rest_suspend: cam_sensor_front_0_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_tof_mclk_active: cam_sensor_tof_mclk_active { + /* MCLK3 */ + mux { + /* CLK, DATA */ + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_tof_mclk_suspend: cam_sensor_tof_mclk_suspend { + /* MCLK3 */ + mux { + /* CLK, DATA */ + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_tof_rest_active: cam_sensor_tof_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_tof_rest_suspend: cam_sensor_tof_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8150-oem-camera-t0.dtsi b/arch/arm64/boot/dts/qcom/sm8150-oem-camera-t0.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..137c6903ebca56732ed2c72e1dd731582954918d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8150-oem-camera-t0.dtsi @@ -0,0 +1,1055 @@ +&pm8150_gpios{ + cam_sensor_laser { + cam_sensor_laser_xsdn_active: cam_sensor_laser_xsdn_active { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_laser_xsdn_suspend: cam_sensor_laser_xsdn_suspend{ + pins = "gpio4"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; +}; + +&pm8150b_gpios{ + cam_sensor_laser { + cam_sensor_laser_intr_active: cam_sensor_laser_intr_active { + pins = "gpio10"; + function = "normal"; + power-source = <0>; + //bias-pull-up; + bias-disable; + output-high; + input-enable; + }; + + cam_sensor_laser_intr_suspend: cam_sensor_laser_intr_suspend{ + pins = "gpio10"; + function = "normal"; + power-source = <0>; + //bias-pull-down; + bias-disable; + output-low; + input-enable; + }; + }; +}; + +&pm8150l_gpios{ + cam_sensor_pmi_gpio { + cam_sensor_rear_0_dvdd_active: cam_sensor_rear_0_dvdd_active { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_rear_0_dvdd_suspend: cam_sensor_rear_0_dvdd_suspend { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + + cam_sensor_rear_2_ana_active: cam_sensor_rear_2_ana_active { + pins = "gpio2"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_rear_2_ana_suspend: cam_sensor_rear_2_ana_suspend { + pins = "gpio2"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + + cam_sensor_rear_2_af_active: cam_sensor_rear_2_af_active { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_rear_2_af_suspend: cam_sensor_rear_2_af_suspend { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; + + cam_sensor_front_0_ana { + cam_sensor_front_0_ana_active: cam_sensor_front_0_ana_active { + pins = "gpio12"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_front_0_ana_suspend: cam_sensor_front_0_ana_suspend { + pins = "gpio12"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; +}; + +&soc { +//laser start + stmvl53l1: st,stmvl53l1@0 { + compatible = "st,stmvl53l1"; + //reg = <0x29>; + //avdd-supply = <&pm8150l_bob>; + laser_vdd-supply = <&pm8150l_l1>; + pinctrl-names = "laser_default", "laser_suspend"; + pinctrl-0 = <&cam_sensor_laser_xsdn_active + &cam_sensor_laser_pwren_active + &cam_sensor_laser_intr_active>; + pinctrl-1 = <&cam_sensor_laser_xsdn_suspend + &cam_sensor_laser_pwren_suspend + &cam_sensor_laser_intr_suspend>; + xsdn-gpio = <&pm8150_gpios 4 GPIO_ACTIVE_HIGH>; + pwren-gpio = <&tlmm 26 0>; + intr-gpio = <&pm8150b_gpios 10 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&spmi_bus>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + }; +//laser end + + led_flash_rear_0: qcom,camera-flash@7 { + cell-index = <7>; + reg = <0x07 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_rear_1: qcom,camera-flash@8 { + cell-index = <8>; + reg = <0x08 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_rear_2: qcom,camera-flash@9 { + cell-index = <9>; + reg = <0x09 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; +}; + +&cam_cci0 { + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + shared-gpios = <14 13>; + pinctrl-names = "cam_res_mgr_default", "cam_res_mgr_suspend"; + status = "ok"; + pinctrl-0 = <&cam_sensor_rear_0_mclk_active + &cam_sensor_rear_1_mclk_active>; + pinctrl-1 = <&cam_sensor_rear_0_mclk_suspend + &cam_sensor_rear_1_mclk_suspend>; + }; + + actuator_rear_0: qcom,actuator@7 { + cell-index = <7>; + reg = <0x7>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <1>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_vaf_active>; + pinctrl-1 = <&cam_sensor_rear_0_vaf_suspend>; + gpios = <&tlmm 25 0>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_0"; + }; + + actuator_rear_1: qcom,actuator@8 { + cell-index = <8>; + reg = <0x8>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <0>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_vaf_active>; + pinctrl-1 = <&cam_sensor_rear_1_vaf_suspend>; + gpios = <&tlmm 35 0>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_1"; + }; + + actuator_rear_2: qcom,actuator@9 { + cell-index = <9>; + reg = <0x9>; + compatible = "qcom,actuator"; + cci-device = <1>; + cci-master = <1>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_2_af_active>; + pinctrl-1 = <&cam_sensor_rear_2_af_suspend>; + gpios = <&pm8150l_gpios 4 GPIO_ACTIVE_HIGH>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_1"; + }; + + ois_rear_0: qcom,ois@02{ + cell-index = <2>; + reg = <2>; + compatible = "qcom,ois"; + cam_vio-supply = <&pm8150l_l1>; + cam_vdig-supply = <&pm8009_l6>;//s5k3m5 ois + cam_vaf-supply = <&pm8009_l5>; + regulator-names = "cam_vio", "cam_vdig", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 2856000 2800000>; + rgltr-max-voltage = <0 2856000 2800000>; + rgltr-load-current = <0 80000 0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + }; + + ois_rear_1: qcom,ois@3 { + cell-index = <3>; + reg = <3>; + compatible = "qcom,ois"; + cam_vio-supply = <&pm8150l_l1>; + cam_vdig-supply = <&pm8009_l5>;//imx586 ois + cam_vaf-supply = <&pm8009_l6>; + regulator-names = "cam_vio", "cam_vdig", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 2800000 2856000>; + rgltr-max-voltage = <0 2800000 2856000>; + rgltr-load-current = <0 80000 0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + }; + + eeprom_rear_0: qcom,eeprom@7 { + cell-index = <7>; + reg = <7>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1104000 0>; + rgltr-max-voltage = <0 3300000 1104000 0>; + rgltr-load-current = <0 80000 1100000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_rest_active + &cam_sensor_rear_0_ana_active>; + pinctrl-1 = <&cam_sensor_rear_0_rest_suspend + &cam_sensor_rear_0_ana_suspend>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 11 0>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET0", + "CAM_VANA_0"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_rear_1: qcom,eeprom@8 { + cell-index = <8>; + reg = <8>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1056000 0>; + rgltr-max-voltage = <0 3300000 1056000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_rest_active + &cam_sensor_rear_1_ana_active>; + pinctrl-1 = <&cam_sensor_rear_1_rest_suspend + &cam_sensor_rear_1_ana_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>, + <&tlmm 148 0>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET1", + "CAM_VANA_1"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_front_0: qcom,eeprom@9 { + cell-index = <9>; + reg = <9>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l3>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1056000 0>; + rgltr-max-voltage = <0 3300000 1056000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_front_0_mclk_active + &cam_sensor_front_0_rest_active + &cam_sensor_front_0_ana_active>; + pinctrl-1 = <&cam_sensor_front_0_mclk_suspend + &cam_sensor_front_0_rest_suspend + &cam_sensor_front_0_ana_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>, + <&pm8150l_gpios 12 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA_2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_rear_2: qcom,eeprom@10 { + cell-index = <10>; + reg = <0xA>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l4>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1056000 0>; + rgltr-max-voltage = <0 3300000 1056000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_2_mclk_active + &cam_sensor_rear_2_rest_active + &cam_sensor_rear_2_ana_active>; + pinctrl-1 = <&cam_sensor_rear_2_mclk_suspend + &cam_sensor_rear_2_rest_suspend + &cam_sensor_rear_2_ana_suspend>; + gpios = <&tlmm 16 0>, + <&tlmm 23 0>, + <&pm8150l_gpios 2 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2 >; + gpio-req-tbl-flags = <1 0 0 >; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3", + "CAM_VANA_3"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear_0>; + actuator-src = <&actuator_rear_0>; + ois-src = <&ois_rear_0>; + eeprom-src = <&eeprom_rear_0>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1104000 0>; + rgltr-max-voltage = <0 3300000 1104000 0>; + rgltr-load-current = <0 80000 1100000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_rest_active + &cam_sensor_rear_0_ana_active + &cam_sensor_rear_0_ana2_active + &cam_sensor_rear_0_dvdd_active>; + pinctrl-1 = <&cam_sensor_rear_0_rest_suspend + &cam_sensor_rear_0_ana_suspend + &cam_sensor_rear_0_ana2_suspend + &cam_sensor_rear_0_dvdd_suspend>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 11 0>, + <&tlmm 29 0>, + <&pm8150l_gpios 1 GPIO_ACTIVE_HIGH>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-custom1 = <3>; + gpio-custom2 = <4>; + gpio-req-tbl-num = <0 1 2 3 4>; + gpio-req-tbl-flags = <1 0 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET0", + "CAM_VANA_0", + "CAM_VANA2_0", + "CAM_PVDD"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + reg = <0x1>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear_1>; + led-flash-src = <&led_flash_rear_1>; + eeprom-src = <&eeprom_rear_0>;//for imx586&s5k3m5 use same eeprom located on master imx586 + ois-src = <&ois_rear_1>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1056000 0>; + rgltr-max-voltage = <0 3300000 1056000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_rest_active + &cam_sensor_rear_1_ana_active>; + pinctrl-1 = <&cam_sensor_rear_1_rest_suspend + &cam_sensor_rear_1_ana_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>, + <&tlmm 148 0>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET1", + "CAM_VANA_1"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front_0>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l3>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1056000 0>; + rgltr-max-voltage = <0 3300000 1056000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_front_0_mclk_active + &cam_sensor_front_0_rest_active + &cam_sensor_front_0_ana_active>; + pinctrl-1 = <&cam_sensor_front_0_mclk_suspend + &cam_sensor_front_0_rest_suspend + &cam_sensor_front_0_ana_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>, + <&pm8150l_gpios 12 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA_2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + reg = <0x03>; + csiphy-sd-index = <3>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + led-flash-src = <&led_flash_rear_2>; + eeprom-src = <&eeprom_rear_2>; + actuator-src = <&actuator_rear_2>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l4>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1056000 0>; + rgltr-max-voltage = <0 3300000 1056000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_2_mclk_active + &cam_sensor_rear_2_rest_active + &cam_sensor_rear_2_ana_active>; + pinctrl-1 = <&cam_sensor_rear_2_mclk_suspend + &cam_sensor_rear_2_rest_suspend + &cam_sensor_rear_2_ana_suspend>; + gpios = <&tlmm 16 0>, + <&tlmm 23 0>, + <&pm8150l_gpios 2 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2 >; + gpio-req-tbl-flags = <1 0 0 >; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3", + "CAM_VANA_3"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; +}; + +&tlmm { + cam_sensor_rear_0_mclk_active: cam_sensor_rear_0_mclk_active { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_mclk_suspend: cam_sensor_rear_0_mclk_suspend { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_rest_active: cam_sensor_rear_0_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_rest_suspend: cam_sensor_rear_0_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana_active: cam_sensor_rear_0_ana_active { + /* VANA */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana_suspend: cam_sensor_rear_0_ana_suspend { + /* VANA */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana2_active: cam_sensor_rear_0_ana2_active { + /* VANA */ + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana2_suspend: cam_sensor_rear_0_ana2_suspend { + /* VANA */ + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_vaf_active: cam_sensor_rear_0_vaf_active { + /* AF */ + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_vaf_suspend: cam_sensor_rear_0_vaf_suspend { + /* AF */ + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_mclk_active: cam_sensor_rear_1_mclk_active { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_mclk_suspend: cam_sensor_rear_1_mclk_suspend { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_rest_active: cam_sensor_rear_1_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_rest_suspend: cam_sensor_rear_1_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_ana_active: cam_sensor_rear_1_ana_active { + /* VANA */ + mux { + pins = "gpio148"; + function = "gpio"; + }; + + config { + pins = "gpio148"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_ana_suspend: cam_sensor_rear_1_ana_suspend { + /* VANA */ + mux { + pins = "gpio148"; + function = "gpio"; + }; + + config { + pins = "gpio148"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_vaf_active: cam_sensor_rear_1_vaf_active { + /* ACTUATOR POWER */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_vaf_suspend: cam_sensor_rear_1_vaf_suspend { + /* ACTUATOR POWER */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_mclk_active: cam_sensor_front_0_mclk_active { + /* MCLK2 */ + mux { + /* CLK, DATA */ + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_mclk_suspend: cam_sensor_front_0_mclk_suspend { + /* MCLK2 */ + mux { + /* CLK, DATA */ + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_rest_active: cam_sensor_front_0_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_rest_suspend: cam_sensor_front_0_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_2_mclk_active: cam_sensor_rear_2_mclk_active { + /* MCLK3 */ + mux { + /* CLK, DATA */ + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_2_mclk_suspend: cam_sensor_rear_2_mclk_suspend { + /* MCLK3 */ + mux { + /* CLK, DATA */ + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_2_rest_active: cam_sensor_rear_2_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_2_rest_suspend: cam_sensor_rear_2_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_laser_pwren_active: cam_sensor_laser_pwren_active { + /* RESET, STANDBY */ + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_laser_pwren_suspend: cam_sensor_laser_pwren_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8150-oem-camera-v2.dtsi b/arch/arm64/boot/dts/qcom/sm8150-oem-camera-v2.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..e80107dee1c10dbca329b7305dce8f95d5cb1395 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8150-oem-camera-v2.dtsi @@ -0,0 +1,1035 @@ +&pm8150l_gpios{ + cam_sensor_pmi_gpio { + cam_sensor_rear_0_dvdd_active: cam_sensor_rear_0_dvdd_active { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_rear_0_dvdd_suspend: cam_sensor_rear_0_dvdd_suspend { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + + cam_sensor_rear_2_ana_active: cam_sensor_rear_2_ana_active { + pins = "gpio2"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_rear_2_ana_suspend: cam_sensor_rear_2_ana_suspend { + pins = "gpio2"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + + cam_sensor_rear_2_af_active: cam_sensor_rear_2_af_active { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_rear_2_af_suspend: cam_sensor_rear_2_af_suspend { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; + + cam_sensor_front_0_ana { + cam_sensor_front_0_ana_active: cam_sensor_front_0_ana_active { + pins = "gpio12"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_front_0_ana_suspend: cam_sensor_front_0_ana_suspend { + pins = "gpio12"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; +}; + +&soc { +//laser start + stmvl53l1: st,stmvl53l1@0 { + compatible = "st,stmvl53l1"; + //reg = <0x29>; + //avdd-supply = <&pm8150l_bob>; + laser_vdd-supply = <&pm8150l_l1>; + pinctrl-names = "laser_default", "laser_suspend"; + pinctrl-0 = <&cam_sensor_laser_xsdn_active + &cam_sensor_laser_pwren_active + &cam_sensor_laser_intr_active>; + pinctrl-1 = <&cam_sensor_laser_xsdn_suspend + &cam_sensor_laser_pwren_suspend + &cam_sensor_laser_intr_suspend>; + xsdn-gpio = <&tlmm 24 0>; + pwren-gpio = <&tlmm 26 0>; + intr-gpio = <&tlmm 131 0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + }; +//laser end +}; + +&cam_cci0 { + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + shared-gpios = <14 13>; + pinctrl-names = "cam_res_mgr_default", "cam_res_mgr_suspend"; + status = "ok"; + pinctrl-0 = <&cam_sensor_rear_0_mclk_active + &cam_sensor_rear_1_mclk_active>; + pinctrl-1 = <&cam_sensor_rear_0_mclk_suspend + &cam_sensor_rear_1_mclk_suspend>; + }; + + actuator_rear_0: qcom,actuator@7 { + cell-index = <7>; + reg = <0x7>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <1>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_vaf_active>; + pinctrl-1 = <&cam_sensor_rear_0_vaf_suspend>; + gpios = <&tlmm 25 0>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_0"; + }; + + actuator_rear_1: qcom,actuator@8 { + cell-index = <8>; + reg = <0x8>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <0>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_vaf_active>; + pinctrl-1 = <&cam_sensor_rear_1_vaf_suspend>; + gpios = <&tlmm 35 0>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_1"; + }; + + actuator_rear_2: qcom,actuator@9 { + cell-index = <9>; + reg = <0x9>; + compatible = "qcom,actuator"; + cci-device = <1>; + cci-master = <1>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_2_af_active>; + pinctrl-1 = <&cam_sensor_rear_2_af_suspend>; + gpios = <&pm8150l_gpios 4 GPIO_ACTIVE_HIGH>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_1"; + }; + + ois_rear_0: qcom,ois@2 { + cell-index = <2>; + reg = <2>; + compatible = "qcom,ois"; + cam_vio-supply = <&pm8150l_l1>; + cam_vdig-supply = <&pm8009_l6>;//s5k3m5 ois + cam_vaf-supply = <&pm8009_l5>; + regulator-names = "cam_vio", "cam_vdig", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 2856000 2800000>; + rgltr-max-voltage = <0 2856000 2800000>; + rgltr-load-current = <0 80000 0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + }; + + ois_rear_1: qcom,ois@3 { + cell-index = <3>; + reg = <3>; + compatible = "qcom,ois"; + cam_vio-supply = <&pm8150l_l1>; + cam_vdig-supply = <&pm8009_l5>;//imx586 ois + cam_vaf-supply = <&pm8009_l6>; + regulator-names = "cam_vio", "cam_vdig", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 2800000 2856000>; + rgltr-max-voltage = <0 2800000 2856000>; + rgltr-load-current = <0 80000 0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + }; + + eeprom_rear_0: qcom,eeprom@7 { + cell-index = <7>; + reg = <7>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1104000 0>; + rgltr-max-voltage = <0 3300000 1104000 0>; + rgltr-load-current = <0 80000 1100000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_rest_active + &cam_sensor_rear_0_ana_active>; + pinctrl-1 = <&cam_sensor_rear_0_rest_suspend + &cam_sensor_rear_0_ana_suspend>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 11 0>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET0", + "CAM_VANA_0"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_rear_1: qcom,eeprom@8 { + cell-index = <8>; + reg = <8>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1050000 0>; + rgltr-max-voltage = <0 3300000 1050000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_rest_active + &cam_sensor_rear_1_ana_active>; + pinctrl-1 = <&cam_sensor_rear_1_rest_suspend + &cam_sensor_rear_1_ana_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>, + <&tlmm 148 0>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET1", + "CAM_VANA_1"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_front_0: qcom,eeprom@9 { + cell-index = <9>; + reg = <9>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l3>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1056000 0>; + rgltr-max-voltage = <0 3300000 1056000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_front_0_mclk_active + &cam_sensor_front_0_rest_active + &cam_sensor_front_0_ana_active>; + pinctrl-1 = <&cam_sensor_front_0_mclk_suspend + &cam_sensor_front_0_rest_suspend + &cam_sensor_front_0_ana_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>, + <&pm8150l_gpios 12 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA_2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_rear_2: qcom,eeprom@10 { + cell-index = <10>; + reg = <0xA>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l4>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1050000 0>; + rgltr-max-voltage = <0 3300000 1050000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_2_mclk_active + &cam_sensor_rear_2_rest_active + &cam_sensor_rear_2_ana_active>; + pinctrl-1 = <&cam_sensor_rear_2_mclk_suspend + &cam_sensor_rear_2_rest_suspend + &cam_sensor_rear_2_ana_suspend>; + gpios = <&tlmm 16 0>, + <&tlmm 23 0>, + <&pm8150l_gpios 2 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2 >; + gpio-req-tbl-flags = <1 0 0 >; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3", + "CAM_VANA_3"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear>; + actuator-src = <&actuator_rear_0>; + ois-src = <&ois_rear_0>; + eeprom-src = <&eeprom_rear_1>;//for imx586&s5k3m5 use same eeprom located on slave s5k3m5 + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1104000 0>; + rgltr-max-voltage = <0 3300000 1104000 0>; + rgltr-load-current = <0 80000 1100000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_rest_active + &cam_sensor_rear_0_ana_active + &cam_sensor_rear_0_ana2_active + &cam_sensor_rear_0_dvdd_active>; + pinctrl-1 = <&cam_sensor_rear_0_rest_suspend + &cam_sensor_rear_0_ana_suspend + &cam_sensor_rear_0_ana2_suspend + &cam_sensor_rear_0_dvdd_suspend>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 11 0>, + <&tlmm 29 0>, + <&pm8150l_gpios 1 GPIO_ACTIVE_HIGH>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-custom1 = <3>; + gpio-custom2 = <4>; + gpio-req-tbl-num = <0 1 2 3 4>; + gpio-req-tbl-flags = <1 0 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET0", + "CAM_VANA_0", + "CAM_VANA2_0", + "CAM_PVDD"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + reg = <0x1>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear_1>; + led-flash-src = <&led_flash_rear_aux>; + eeprom-src = <&eeprom_rear_1>; + ois-src = <&ois_rear_1>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1050000 0>; + rgltr-max-voltage = <0 3300000 1050000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_rest_active + &cam_sensor_rear_1_ana_active>; + pinctrl-1 = <&cam_sensor_rear_1_rest_suspend + &cam_sensor_rear_1_ana_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>, + <&tlmm 148 0>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET1", + "CAM_VANA_1"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front_0>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l3>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1056000 0>; + rgltr-max-voltage = <0 3300000 1056000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_front_0_mclk_active + &cam_sensor_front_0_rest_active + &cam_sensor_front_0_ana_active>; + pinctrl-1 = <&cam_sensor_front_0_mclk_suspend + &cam_sensor_front_0_rest_suspend + &cam_sensor_front_0_ana_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>, + <&pm8150l_gpios 12 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA_2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + reg = <0x03>; + csiphy-sd-index = <3>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_rear_2>; + actuator-src = <&actuator_rear_2>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l4>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1050000 0>; + rgltr-max-voltage = <0 3300000 1050000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_2_mclk_active + &cam_sensor_rear_2_rest_active + &cam_sensor_rear_2_ana_active>; + pinctrl-1 = <&cam_sensor_rear_2_mclk_suspend + &cam_sensor_rear_2_rest_suspend + &cam_sensor_rear_2_ana_suspend>; + gpios = <&tlmm 16 0>, + <&tlmm 23 0>, + <&pm8150l_gpios 2 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2 >; + gpio-req-tbl-flags = <1 0 0 >; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3", + "CAM_VANA_3"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; +}; + +&tlmm { + cam_sensor_rear_0_mclk_active: cam_sensor_rear_0_mclk_active { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_mclk_suspend: cam_sensor_rear_0_mclk_suspend { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_rest_active: cam_sensor_rear_0_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_rest_suspend: cam_sensor_rear_0_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana_active: cam_sensor_rear_0_ana_active { + /* VANA */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana_suspend: cam_sensor_rear_0_ana_suspend { + /* VANA */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana2_active: cam_sensor_rear_0_ana2_active { + /* VANA */ + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana2_suspend: cam_sensor_rear_0_ana2_suspend { + /* VANA */ + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_vaf_active: cam_sensor_rear_0_vaf_active { + /* AF */ + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_vaf_suspend: cam_sensor_rear_0_vaf_suspend { + /* AF */ + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_mclk_active: cam_sensor_rear_1_mclk_active { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_mclk_suspend: cam_sensor_rear_1_mclk_suspend { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_rest_active: cam_sensor_rear_1_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_rest_suspend: cam_sensor_rear_1_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_ana_active: cam_sensor_rear_1_ana_active { + /* VANA */ + mux { + pins = "gpio148"; + function = "gpio"; + }; + + config { + pins = "gpio148"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_ana_suspend: cam_sensor_rear_1_ana_suspend { + /* VANA */ + mux { + pins = "gpio148"; + function = "gpio"; + }; + + config { + pins = "gpio148"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_vaf_active: cam_sensor_rear_1_vaf_active { + /* ACTUATOR POWER */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_vaf_suspend: cam_sensor_rear_1_vaf_suspend { + /* ACTUATOR POWER */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_mclk_active: cam_sensor_front_0_mclk_active { + /* MCLK2 */ + mux { + /* CLK, DATA */ + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_mclk_suspend: cam_sensor_front_0_mclk_suspend { + /* MCLK2 */ + mux { + /* CLK, DATA */ + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_rest_active: cam_sensor_front_0_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_rest_suspend: cam_sensor_front_0_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_2_mclk_active: cam_sensor_rear_2_mclk_active { + /* MCLK3 */ + mux { + /* CLK, DATA */ + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_2_mclk_suspend: cam_sensor_rear_2_mclk_suspend { + /* MCLK3 */ + mux { + /* CLK, DATA */ + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_2_rest_active: cam_sensor_rear_2_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_2_rest_suspend: cam_sensor_rear_2_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_laser_xsdn_active: cam_sensor_laser_xsdn_active { + /* RESET, STANDBY */ + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_laser_xsdn_suspend: cam_sensor_laser_xsdn_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_laser_pwren_active: cam_sensor_laser_pwren_active { + /* RESET, STANDBY */ + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_laser_pwren_suspend: cam_sensor_laser_pwren_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_laser_intr_active: cam_sensor_laser_intr_active { + /* RESET, STANDBY */ + mux { + pins = "gpio131"; + function = "gpio"; + }; + + config { + pins = "gpio131"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_laser_intr_suspend: cam_sensor_laser_intr_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio131"; + function = "gpio"; + }; + + config { + pins = "gpio131"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8150-oem-camera.dtsi b/arch/arm64/boot/dts/qcom/sm8150-oem-camera.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..08f12def4458da02746470c2b73dd2edaacc0b5f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8150-oem-camera.dtsi @@ -0,0 +1,968 @@ +&pm8150_gpios{ + cam_sensor_front_0_dig { + cam_sensor_front_0_dig_active: cam_sensor_front_0_dig_active { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_front_0_dig_suspend: cam_sensor_front_0_dig_suspend{ + pins = "gpio1"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; +}; + +&pm8150l_gpios{ + cam_sensor_tof_pmi_gpio { + cam_sensor_tof_ana_active: cam_sensor_tof_ana_active { + pins = "gpio3"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_tof_ana_suspend: cam_sensor_tof_ana_suspend { + pins = "gpio3"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + + cam_sensor_tof_dig_active: cam_sensor_tof_dig_active { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_tof_dig_suspend: cam_sensor_tof_dig_suspend { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + + cam_sensor_tof_vcc_active: cam_sensor_tof_vcc_active { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_tof_vcc_suspend: cam_sensor_tof_vcc_suspend { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + + cam_sensor_tof_lvcc_active: cam_sensor_tof_lvcc_active { + pins = "gpio2"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_tof_lvcc_suspend: cam_sensor_tof_lvcc_suspend { + pins = "gpio2"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; + + cam_sensor_front_0_ana { + cam_sensor_front_0_ana_active: cam_sensor_front_0_ana_active { + pins = "gpio12"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_front_0_ana_suspend: cam_sensor_front_0_ana_suspend { + pins = "gpio12"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; +}; +&soc { + actuator_rear_0: qcom,actuator@7 { + cell-index = <7>; + reg = <0x7>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <1>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_vaf_active>; + pinctrl-1 = <&cam_sensor_rear_0_vaf_suspend>; + gpios = <&tlmm 24 0>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_0"; + }; + + actuator_rear_1: qcom,actuator@8 { + cell-index = <8>; + reg = <0x8>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <0>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_vaf_active>; + pinctrl-1 = <&cam_sensor_rear_1_vaf_suspend>; + gpios = <&tlmm 35 0>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_1"; + }; + + eeprom_rear_0: qcom,eeprom@7 { + cell-index = <7>; + reg = <7>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_bob>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 3300000 0>; + rgltr-max-voltage = <0 3300000 3300000 0>; + rgltr-load-current = <0 80000 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_mclk_active + &cam_sensor_rear_0_rest_active + &cam_sensor_rear_0_ana_active + &cam_sensor_rear_0_dig_active>; + pinctrl-1 = <&cam_sensor_rear_0_mclk_suspend + &cam_sensor_rear_0_rest_suspend + &cam_sensor_rear_0_ana_suspend + &cam_sensor_rear_0_dig_suspend>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 11 0>, + <&tlmm 29 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET0", + "CAM_VANA_0", + "CAM_DIG_0"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_rear_1: qcom,eeprom@8 { + cell-index = <8>; + reg = <8>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_bob>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 3300000 0>; + rgltr-max-voltage = <0 3300000 3300000 0>; + rgltr-load-current = <0 80000 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_mclk_active + &cam_sensor_rear_1_rest_active + &cam_sensor_rear_1_ana_active + &cam_sensor_rear_1_dig_active>; + pinctrl-1 = <&cam_sensor_rear_1_mclk_suspend + &cam_sensor_rear_1_rest_suspend + &cam_sensor_rear_1_ana_suspend + &cam_sensor_rear_1_dig_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>, + <&tlmm 148 0>, + <&tlmm 26 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET1", + "CAM_VANA_1", + "CAM_DIG_1"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_front_0: qcom,eeprom@9 { + cell-index = <9>; + reg = <9>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_bob>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 3300000 0>; + rgltr-max-voltage = <0 3300000 3300000 0>; + rgltr-load-current = <0 80000 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_front_0_mclk_active + &cam_sensor_front_0_rest_active + &cam_sensor_front_0_ana_active + &cam_sensor_front_0_dig_active>; + pinctrl-1 = <&cam_sensor_front_0_mclk_suspend + &cam_sensor_front_0_rest_suspend + &cam_sensor_front_0_ana_suspend + &cam_sensor_front_0_dig_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>, + <&pm8150l_gpios 12 GPIO_ACTIVE_HIGH>, + <&pm8150_gpios 1 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA_2", + "CAM_DIG_2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_rear_tof: qcom,eeprom@10 { + cell-index = <10>; + reg = <0xA>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 0>; + rgltr-max-voltage = <0 0>; + rgltr-load-current = <0 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_tof_mclk_active + &cam_sensor_tof_rest_active>; + pinctrl-1 = <&cam_sensor_tof_mclk_suspend + &cam_sensor_tof_rest_suspend>; + gpios = <&tlmm 16 0>, + <&tlmm 23 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear>; + actuator-src = <&actuator_rear_0>; + //ois-src = <&ois_rear>; + eeprom-src = <&eeprom_rear_0>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_bob>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 3300000 0>; + rgltr-max-voltage = <0 3300000 3300000 0>; + rgltr-load-current = <0 80000 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_mclk_active + &cam_sensor_rear_0_rest_active + &cam_sensor_rear_0_ana_active + &cam_sensor_rear_0_dig_active>; + pinctrl-1 = <&cam_sensor_rear_0_mclk_suspend + &cam_sensor_rear_0_rest_suspend + &cam_sensor_rear_0_ana_suspend + &cam_sensor_rear_0_dig_suspend>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 11 0>, + <&tlmm 29 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET0", + "CAM_VANA_0", + "CAM_DIG_0"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + reg = <0x1>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear_1>; + led-flash-src = <&led_flash_rear_aux>; + eeprom-src = <&eeprom_rear_1>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_bob>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 3300000 0>; + rgltr-max-voltage = <0 3300000 3300000 0>; + rgltr-load-current = <0 80000 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_mclk_active + &cam_sensor_rear_1_rest_active + &cam_sensor_rear_1_ana_active + &cam_sensor_rear_1_dig_active>; + pinctrl-1 = <&cam_sensor_rear_1_mclk_suspend + &cam_sensor_rear_1_rest_suspend + &cam_sensor_rear_1_ana_suspend + &cam_sensor_rear_1_dig_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>, + <&tlmm 148 0>, + <&tlmm 26 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET1", + "CAM_VANA_1", + "CAM_DIG_1"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front_0>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_bob>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 3300000 0>; + rgltr-max-voltage = <0 3300000 3300000 0>; + rgltr-load-current = <0 80000 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_front_0_mclk_active + &cam_sensor_front_0_rest_active + &cam_sensor_front_0_ana_active + &cam_sensor_front_0_dig_active>; + pinctrl-1 = <&cam_sensor_front_0_mclk_suspend + &cam_sensor_front_0_rest_suspend + &cam_sensor_front_0_ana_suspend + &cam_sensor_front_0_dig_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>, + <&pm8150l_gpios 12 GPIO_ACTIVE_HIGH>, + <&pm8150_gpios 1 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA_2", + "CAM_DIG_2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + reg = <0x03>; + csiphy-sd-index = <3>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_rear_tof>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_bob>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 3300000 0>; + rgltr-max-voltage = <0 3300000 3300000 0>; + rgltr-load-current = <0 80000 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_tof_mclk_active + &cam_sensor_tof_rest_active + &cam_sensor_tof_ana_active + &cam_sensor_tof_dig_active + &cam_sensor_tof_vcc_active + &cam_sensor_tof_lvcc_active>; + pinctrl-1 = <&cam_sensor_tof_mclk_suspend + &cam_sensor_tof_rest_suspend + &cam_sensor_tof_ana_suspend + &cam_sensor_tof_dig_suspend + &cam_sensor_tof_vcc_suspend + &cam_sensor_tof_lvcc_suspend>; + gpios = <&tlmm 16 0>, + <&tlmm 23 0>, + <&pm8150l_gpios 3 GPIO_ACTIVE_HIGH>, + <&pm8150l_gpios 4 GPIO_ACTIVE_HIGH>, + <&pm8150l_gpios 1 GPIO_ACTIVE_HIGH>, + <&pm8150l_gpios 2 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-custom1 = <4>; + gpio-custom2 = <5>; + gpio-req-tbl-num = <0 1 2 3 4 5>; + gpio-req-tbl-flags = <1 0 0 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3", + "CAM_VANA_3", + "CAM_DIG_3", + "CAM_VCC_3", + "CAM_LVCC_3"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +//laser start + stmvl53l1: st,stmvl53l1@0 { + compatible = "st,stmvl53l1"; + //reg = <0x29>; + //avdd-supply = <&pm8150l_bob>; + laser_vdd-supply = <&pm8150l_l1>; + //pinctrl-names = "laser_default", "laser_suspend"; + //pinctrl-0 = <&stm_laser_pwren_active>; + //pinctrl-1 = <&stm_laser_pwren_suspend>; + xsdn-gpio = <30>; + pwren-gpio = <11>; + intr-gpio = <131>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + }; +//laser end +}; + +&tlmm { + cam_sensor_rear_0_mclk_active: cam_sensor_rear_0_mclk_active { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_mclk_suspend: cam_sensor_rear_0_mclk_suspend { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_rest_active: cam_sensor_rear_0_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_rest_suspend: cam_sensor_rear_0_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana_active: cam_sensor_rear_0_ana_active { + /* VANA */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana_suspend: cam_sensor_rear_0_ana_suspend { + /* VANA */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_dig_active: cam_sensor_rear_0_dig_active { + /* DIG */ + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_dig_suspend: cam_sensor_rear_0_dig_suspend { + /* DIG */ + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_vaf_active: cam_sensor_rear_0_vaf_active { + /* DIG */ + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_vaf_suspend: cam_sensor_rear_0_vaf_suspend { + /* DIG */ + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_mclk_active: cam_sensor_rear_1_mclk_active { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_mclk_suspend: cam_sensor_rear_1_mclk_suspend { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_rest_active: cam_sensor_rear_1_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_rest_suspend: cam_sensor_rear_1_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_ana_active: cam_sensor_rear_1_ana_active { + /* VANA */ + mux { + pins = "gpio148"; + function = "gpio"; + }; + + config { + pins = "gpio148"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_ana_suspend: cam_sensor_rear_1_ana_suspend { + /* VANA */ + mux { + pins = "gpio148"; + function = "gpio"; + }; + + config { + pins = "gpio148"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_vaf_active: cam_sensor_rear_1_vaf_active { + /* ACTUATOR POWER */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_vaf_suspend: cam_sensor_rear_1_vaf_suspend { + /* ACTUATOR POWER */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_dig_active: cam_sensor_rear_1_dig_active { + /* DIG */ + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_dig_suspend: cam_sensor_rear_1_dig_suspend { + /* DIG */ + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_mclk_active: cam_sensor_front_0_mclk_active { + /* MCLK2 */ + mux { + /* CLK, DATA */ + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_mclk_suspend: cam_sensor_front_0_mclk_suspend { + /* MCLK2 */ + mux { + /* CLK, DATA */ + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_rest_active: cam_sensor_front_0_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_rest_suspend: cam_sensor_front_0_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_tof_mclk_active: cam_sensor_tof_mclk_active { + /* MCLK3 */ + mux { + /* CLK, DATA */ + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_tof_mclk_suspend: cam_sensor_tof_mclk_suspend { + /* MCLK3 */ + mux { + /* CLK, DATA */ + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_tof_rest_active: cam_sensor_tof_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_tof_rest_suspend: cam_sensor_tof_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8150-oem.dtsi b/arch/arm64/boot/dts/qcom/sm8150-oem.dtsi new file mode 100755 index 0000000000000000000000000000000000000000..d6ca1ce406e8abd464d8bebc1f310229f19be660 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8150-oem.dtsi @@ -0,0 +1,1353 @@ +/* Display */ +&soc { + dsi_samsung_oneplus_dsc_cmd_display: qcom,dsi-display@23 { + label = "dsi_samsung_oneplus_dsc_cmd_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-panel = <&dsi_samsung_oneplus_dsc_cmd>; + }; + + dsi_samsung_s6e3fc2x01_cmd_display: qcom,dsi-display@24 { + label = "dsi_samsung_s6e3fc2x01_cmd_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-panel = <&dsi_samsung_s6e3fc2x01_cmd>; + }; + + dsi_samsung_sofef03f_m_fhd_dsc_cmd_display: qcom,dsi-display@25 { + label = "dsi_samsung_sofef03f_m_fhd_dsc_cmd_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-panel = <&dsi_samsung_sofef03f_m_fhd_dsc_cmd>; + }; + + dsi_samsung_sofef00_m_video_display: qcom,dsi-display@27 { + label = "dsi_samsung_sofef00_m_video_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-panel = <&dsi_samsung_sofef00_m_video>; + }; + + + tri_state_key:tri_state_key { + compatible = "oneplus, tri-state-key"; + status = "okay"; + interrupt-parent = <&tlmm>; + tristate,gpio_key1 = <&tlmm 27 0x00>; + tristate,gpio_key2 = <&tlmm 134 0x00>; + tristate,gpio_key3 = <&tlmm 125 0x00>; + pinctrl-names = + "pmx_tri_state_key_active", + "pmx_tri_state_key_suspend"; + pinctrl-0 = <&tri_state_key_active>; + pinctrl-1 = <&tri_state_key_suspend>; + }; + + fingerprint_detect:fingerprint_detect { + compatible = "oneplus,fpdetect"; + fp-gpio-id0 = <&tlmm 90 0>; + fp-gpio-id1 = <&pm8150_gpios 3 0>; + pinctrl-names = "fp_id_init"; + pinctrl-0 = <&fp_id0_init &fp_id1_init>; + }; + + goodix_fp { + compatible = "goodix,fingerprint"; + interrupt-parent = <&tlmm>; + //vdd-3v2-supply = <&pm8998_l22>; + //vdd-voltage = <3200000 3200000>; + //vdd-current = <50000>; + fp-gpio-irq = <&tlmm 118 0x00>; + fp-gpio-reset = <&tlmm 131 0x00>; + fp-gpio-enable = <&tlmm 101 0x00>; + pinctrl-names = "fp_en_init", "fp_dis_init"; + pinctrl-0 = <&fp_vdd_init &fp_irq_init>; + pinctrl-1 = <&fp_vdd_dis_init>; + status = "okay"; + }; +}; + +&qcomqbt1000{ + /delete-property/ pinctrl-names; + /delete-property/ pinctrl-0; + qfp-int2 = <&tlmm 131 0x00>; + qcom,finger-detect-gpio = <&tlmm 101 0>; +}; + +&sde_dsi { + pinctrl-names = "panel_active", "panel_suspend","default"; + pinctrl-0 = <&sde_dsi_active &sde_te_active &display_panel_avdd_eldo_default>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend &display_panel_avdd_eldo_off>; + /delete-property/ lab-supply; + /delete-property/ ibb-supply; + /delete-property/ vdd-supply; + qcom,dsi-display-list = + <&dsi_samsung_oneplus_dsc_cmd_display + &dsi_samsung_s6e3fc2x01_cmd_display + &dsi_samsung_sofef03f_m_fhd_dsc_cmd_display + &dsi_samsung_sofef00_m_video_display>; +}; + +&tlmm{ + display_panel_avdd_eldo_off: display_panel_avdd_eldo_off { + mux { + pins = "gpio130"; + function = "gpio"; + }; + config { + pins = "gpio130"; + drive-strength = <8>; + bias-disable = <0>; + output-low; + }; + }; + + tri_state_key_active: tri_state_key_active { + mux { + pins = "gpio125", "gpio134", "gpio27"; + function = "gpio"; + }; + config { + pins = "gpio125", "gpio134", "gpio27"; + drive-strength = <2>; + bias-disable; + }; + }; + + tri_state_key_suspend: tri_state_key_suspend { + mux { + pins = "gpio125", "gpio134", "gpio27"; + function = "gpio"; + }; + config { + pins = "gpio125", "gpio134", "gpio27"; + drive-strength = <2>; + bias-disable; + }; + }; + +}; + +//wangdongdong@AudioDrv, add for 4M memory increase of adsp begain +&pil_adsp_mem { + reg = <0x0 0x8be00000 0x0 0x1e00000>; +}; + +&pil_modem_mem { + reg = <0x0 0x8dc00000 0x0 0x9600000>; +}; + +&pil_video_mem { + reg = <0x0 0x97200000 0x0 0x500000>; +}; + +&pil_slpi_mem { + reg = <0x0 0x97700000 0x0 0x1400000>; +}; + +&pil_ipa_fw_mem { + reg = <0x0 0x98b00000 0x0 0x10000>; +}; + +&pil_ipa_gsi_mem { + reg = <0x0 0x98b10000 0x0 0x5000>; +}; + +&pil_gpu_mem { + reg = <0x0 0x98b15000 0x0 0x2000>; +}; + +&pil_spss_mem { + reg = <0x0 0x98c00000 0x0 0x100000>; +}; + +&pil_cdsp_mem { + reg = <0x0 0x98d00000 0x0 0x1400000>; +}; +//wangdongdong@AudioDrv, add for 4M memory increase of adsp end + +//dujie@MM.Audio add begain +/* #if OP_FEATURE_MM_RECORDING_SCREEN == 1*/ +/* zhanglixia@MM.Audio, 2019/07/13, add for screen record*/ + +&snd_934x { + qcom,afe-rxtx-lb = <1>; + asoc-cpu = <&dai_hdmi>, <&dai_dp>, + <&dai_mi2s0>, <&dai_mi2s1>, + <&dai_mi2s2>, <&dai_mi2s3>, + <&dai_mi2s4>, <&dai_pri_auxpcm>, + <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, + <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, + <&sb_0_rx>, <&sb_0_tx>, <&sb_1_rx>, <&sb_1_tx>, + <&sb_2_rx>, <&sb_2_tx>, <&sb_3_rx>, <&sb_3_tx>, + <&sb_4_rx>, <&sb_4_tx>, <&sb_5_tx>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&incall_music_2_rx>, <&sb_5_rx>, <&sb_6_rx>, + <&sb_7_rx>, <&sb_7_tx>, <&sb_8_tx>, + <&usb_audio_rx>, <&usb_audio_tx>, + <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>, + <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>, + <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>, + <&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>, + <&dai_quat_tdm_rx_1>, + <&dai_quin_tdm_rx_0>, <&dai_quin_tdm_tx_0>, + <&afe_loopback_tx>; + asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.24608", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-mi2s.4", "msm-dai-q6-auxpcm.1", + "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", + "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", + "msm-dai-q6-dev.16384", "msm-dai-q6-dev.16385", + "msm-dai-q6-dev.16386", "msm-dai-q6-dev.16387", + "msm-dai-q6-dev.16388", "msm-dai-q6-dev.16389", + "msm-dai-q6-dev.16390", "msm-dai-q6-dev.16391", + "msm-dai-q6-dev.16392", "msm-dai-q6-dev.16393", + "msm-dai-q6-dev.16395", "msm-dai-q6-dev.224", + "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", + "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", + "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", + "msm-dai-q6-dev.32770", "msm-dai-q6-dev.16394", + "msm-dai-q6-dev.16396", "msm-dai-q6-dev.16398", + "msm-dai-q6-dev.16399", "msm-dai-q6-dev.16401", + "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", + "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", + "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", + "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897", + "msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913", + "msm-dai-q6-tdm.36914", + "msm-dai-q6-tdm.36928", "msm-dai-q6-tdm.36929", + "msm-dai-q6-dev.24577"; +}; +/* #endif*/ +&snd_9360 { + status = "disabled"; +}; +&wcd9360_cdc { + status = "disabled"; +}; +&clock_audio { + status = "disabled"; +}; + +&snd_934x { + qcom,audio-routing = + "AIF4 VI", "MCLK", + "RX_BIAS", "MCLK", + "MADINPUT", "MCLK", + "hifi amp", "LINEOUT1", + "hifi amp", "LINEOUT2", + "AMIC1", "MIC BIAS1", + "AMIC2", "MIC BIAS2", + "MIC BIAS2", "Headset Mic", + "AMIC3", "MIC BIAS4", + "MIC BIAS4", "ANCRight Headset Mic", + "AMIC4", "MIC BIAS1", + "MIC BIAS1", "ANCLeft Headset Mic", + "AMIC5", "MIC BIAS1", + "MIC BIAS1", "Handset Mic", + "DMIC0", "MIC BIAS1", + "MIC BIAS1", "Digital Mic0", + "DMIC1", "MIC BIAS1", + "MIC BIAS1", "Digital Mic1", + "DMIC2", "MIC BIAS3", + "MIC BIAS3", "Digital Mic2", + "DMIC3", "MIC BIAS3", + "MIC BIAS3", "Digital Mic3", + "DMIC4", "MIC BIAS4", + "MIC BIAS4", "Digital Mic4", + "DMIC5", "MIC BIAS4", + "MIC BIAS4", "Digital Mic5", + "SpkrLeft IN", "SPK1 OUT", + "SpkrRight IN", "SPK2 OUT"; + + qcom,wsa-max-devs = <0>; + qcom,msm-mbhc-usbc-audio-supported = <1>; + qcom,msm-mbhc-hs-mic-max-threshold-mv = <2550>; + pinctrl-names = "quat_mi2s_enable","quat_mi2s_disable", + "quat_tdm_enable","quat_tdm_disable"; + pinctrl-0 = <&quat_mi2s_active + &quat_mi2s_sd0_active &quat_mi2s_sd1_active>; + pinctrl-1 = <&quat_mi2s_sleep + &quat_mi2s_sd0_sleep &quat_mi2s_sd1_sleep>; + pinctrl-2 = <&quat_tdm_active + &quat_tdm_din_active &quat_tdm_dout_active>; + pinctrl-3 = <&quat_tdm_sleep + &quat_tdm_din_sleep &quat_tdm_dout_sleep>; + + // yewenliang@MM.Audio, 2019/06/07, fix cap noise issues in handset mode + vreg_ldo-supply = <&pm8150l_l10>; + vreg_bob-supply = <&pm8150l_bob>; +}; + +&wcd934x_cdc { + qcom,cdc-micbias1-mv = <2700>; + qcom,cdc-micbias2-mv = <2700>; + qcom,cdc-micbias4-mv = <2700>; +}; + +&wsa881x_70211{ + status = "disabled"; +}; + +&wsa881x_70212{ + status = "disabled"; +}; + +&wsa881x_70213{ + status = "disabled"; +}; + +&wsa881x_70214{ + status = "disabled"; +}; + +&qupv3_se4_i2c { + tfa98xx_right: tfa98xx_right@34 { + compatible = "nxp,tfa98xx"; + reg = <0x34>; + reset-gpio = <&tlmm 37 0>; + status = "ok"; + }; + + tfa98xx_left: tfa98xx_left@35 { + compatible = "nxp,tfa98xx"; + reg = <0x35>; + reset-gpio = <&tlmm 100 0>; + status = "ok"; + }; +}; + +&dai_mi2s3 { + qcom,msm-mi2s-rx-lines = <2>; + qcom,msm-mi2s-tx-lines = <1>; +}; + +//Because pcie0 wakeup-gpio is same pa-gpio, so disabled it +&pcie0 { + status = "disabled"; +}; +//dujie@MM.Audio add end + +&sde_dsi_active { + mux { + pins = "gpio78"; + function = "gpio"; + }; + + config { + pins = "gpio78"; + drive-strength = <8>; + bias-disable = <0>; + }; +}; +&sde_dsi_suspend { + mux { + pins = "gpio78"; + function = "gpio"; + }; + + config { + pins = "gpio78"; + drive-strength = <2>; + bias-pull-down; + }; +}; + +/*for aw haptic start*/ +&qupv3_se7_i2c { + status = "ok"; + aw8697_haptic:aw8697_haptic@5A { + compatible = "awinic,aw8697_haptic"; + reg = <0x5A>; + reset-gpio = <&tlmm 116 0x00>; + irq-gpio = <&tlmm 24 0x00>; + pinctrl-names = "default"; + pinctrl-0 = <&aw_irq &aw_reset>; + status = "okay"; + }; +}; +/*for aw haptic end*/ + +/* Touch */ +&qupv3_se17_i2c { + status = "ok"; + sec-s6sy761@48 { + compatible = "sec-s6sy761"; + reg = <0x48>; + project-name = "18821"; + chip-name = "SY761"; + module_id = <7>; + reset-gpio = <&tlmm 54 0x00>; + irq-gpio = <&tlmm 122 0x2008>; + vdd_2v8-supply = <&pm8150_l17>; //set 3.3 by ldo + vdd_2v8_volt = <3008000>; + //enable1v8_gpio = <&tlmm 119 0x00>; //set 1.8v by gpio + touchpanel,display-coords = <1439 3119>; + touchpanel,panel-coords = <1439 3119>; + touchpanel,tx-rx-num = <17 37>; + //edge_limit_support = <1>; + //spurious_fingerprint_support = <1>; + //charger_pump_support = <1>; + charge_detect_support = <1>; + black_gesture_support = <1>; + //black_gesture_test_support = <1>; + game_switch_support = <1>; + face_detect_support = <1>; + lcd_refresh_rate_switch = <1>; + touch_hold_support = <1>; + //lcd_trigger_fp_check = <1>; + pinctrl-names = "pin_set_high", "pin_set_low"; + pinctrl-0 = <&tp_1v8_active &tp_irq_active &tp_rst_active>; + pinctrl-1 = <&tp_rst_suspend &tp_1v8_suspend>; + }; +}; +&qupv3_se17_i2c { + status = "ok"; + synaptics-s3706@20 { + compatible = "synaptics-s3706"; + reg = <0x20>; + //project-name = "18857"; + chip-name = "S3706"; + //reset-gpio = <&tlmm 54 0x00>; + irq-gpio = <&tlmm 122 0x2008>; + vdd_2v8-supply = <&pm8150_l17>; //set 3.3 by ldo + vdd_2v8_volt = <3008000>; + //enable1v8_gpio = <&tlmm 59 0x00>; //set 1.8v by gpio + //touchpanel,display-coords = <1080 2340>; + //touchpanel,panel-coords = <1080 2340>; + //touchpanel,tx-rx-num = <16 33>; + black_gesture_support = <1>; + face_detect_support = <1>; + touch_hold_support = <1>; + charge_detect_support = <1>; + module_id = <7>; + pinctrl-names = "pin_set_high", "pin_set_low"; + pinctrl-0 = <&tp_irq_active &tp_rst_active &tp_1v8_active>; + pinctrl-1 = <&tp_rst_suspend &tp_1v8_suspend>; + }; +}; + +/* Add for NXP NFCC */ +&qupv3_se9_i2c { + nq@28 { + status = "disabled"; + }; + + pn5xx@28 { + compatible = "nxp,pn544"; + reg = <0x28>; + nxp,pn544-irq = <&tlmm 47 0x00>; + nxp,pn544-ven = <&tlmm 41 0x00>; + nxp,pn544-fw-dwnld = <&tlmm 48 0x00>; + nxp,pn544-clk-gpio = <&tlmm 113 0x00>; + nxp,pn544-ese-pwr = <&tlmm 49 0x00>; + nfc_voltage_s4-supply = <&pm8150_s4>; + interrupt-parent = <&tlmm>; + qcom,clk-src = "BBCLK3"; + interrupts = <47 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; + }; +}; + +/* Add for NXP eSE */ +&qupv3_se0_spi { + status = "ok"; + qcom,disable-autosuspend; + + ese@0 { + compatible = "nxp,p61"; + reg = <0>; + spi-max-frequency = <8000000>; + nxp,nfcc = "4-0028"; + }; +}; + +&tlmm { + +aw_irq: aw_irq { + mux { + pins = "gpio116"; + function = "gpio"; + }; + + config { + pins = "gpio116"; + drive-strength = <2>; + }; + }; + +aw_reset: aw_reset { + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + drive-strength = <2>; + bias-disable; + }; + }; + +tp_irq_active: tp_irq_active { + mux { + pins = "gpio122"; + function = "gpio"; + }; + config { + pins = "gpio122"; + drive-strength = <8>; + bias-disable; + input-enable; + }; + }; + tp_rst_active: tp_rst_active { + mux { + pins = "gpio54"; + function = "gpio"; + }; + config { + pins = "gpio54"; + drive-strength = <8>; + bias-disable; + }; + }; + tp_1v8_active: tp_1v8_active { + mux { + pins = "gpio119"; + function = "gpio"; + }; + config { + pins = "gpio119"; + drive-strength = <8>; + bias-pull-up; + }; + }; + tp_rst_suspend: tp_rst_suspend { + mux { + pins = "gpio54"; + function = "gpio"; + }; + config { + pins = "gpio54"; + drive-strength = <8>; + bias-pull-down; + }; + }; + tp_1v8_suspend: tp_1v8_suspend { + mux { + pins = "gpio119"; + function = "gpio"; + }; + config { + pins = "gpio119"; + drive-strength = <8>; + bias-pull-down; + }; + }; + + fp_irq_init: fp_irq_init { + mux { + pins = "gpio118"; + function = "gpio"; + }; + + config { + pins = "gpio118"; + drive-strength = <2>; + bias-disable; + input-enable; + }; + }; + + fp_reset_init: fp_reset_init { + mux { + pins = "gpio131"; + function = "gpio"; + }; + + config { + pins = "gpio131"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + fp_vdd_init: fp_vdd_init { + mux { + pins = "gpio101"; + function = "gpio"; + }; + + config { + pins = "gpio101"; + drive-strength = <8>; + bias-pull-up; + output-high; + }; + }; + + fp_vdd_dis_init: fp_vdd_dis_init { + mux { + pins = "gpio101"; + function = "gpio"; + }; + + config { + pins = "gpio101"; + drive-strength = <8>; + bias-pull-down; + output-low; + }; + }; + + fp_id0_init: fp_id0_init { + mux { + pins = "gpio90"; + function = "gpio"; + }; + + config { + pins = "gpio90"; + drive-strength = <2>; + bias-disable; /* No Pull */ + input-enable; + }; + }; +}; + +&vendor { + infrared_pl: infrared_pl { + compatible = "oneplus-infrared"; + vdd-supply = <&pm8150l_l9>; + }; +}; + + +//quentin.lin add 2018/11/07 +&vendor { + motor_pl: motor_pl { + compatible = "oneplus-motor"; + interrupt-parent = <&tlmm>; + interrupts = <163 0x2>; + motor,irq-gpio = <&tlmm 163 0x2008>; + pinctrl-names = "free_fall_input"; + pinctrl-0 = <&free_fall_input>; + structure,id = <0>; + }; +}; + + +// quentin.lin@oneplus.com 2018/11/26 edit for free fall +&tlmm { + free_fall_input: free_fall_input { + mux { + pins = "gpio163"; + function = "gpio"; + }; + config { + pins = "gpio163"; + drive-strength = <2>; + input-enable; + bias-disable; //No Pull + }; + }; + +}; + + +&qupv3_se1_i2c { + status = "ok"; + magnachip@0C { + compatible = "magnachip,mxm1120,up"; + reg = <0x0C>; + vdd-supply = <&pm8150l_l7>; + vio-supply = <&pm8150l_l8>; + magnachip,init-interval = <200>; + interrupt-parent = <&tlmm>; + interrupts = <120 0x2>; + dhall,irq-gpio = <&tlmm 120 0x2008>; + mxm,id = <1>; + }; + magnachip@0D { + compatible = "magnachip,mxm1120,down"; + reg = <0x0D>; + vdd-supply = <&pm8150l_l7>; + vio-supply = <&pm8150l_l8>; + magnachip,init-interval = <200>; + interrupt-parent = <&tlmm>; + interrupts = <121 0x2>; + dhall,irq-gpio = <&tlmm 121 0x2008>; + mxm,id = <2>; + }; +}; + + +/* @bsp, 2019/04/17 Battery & Charging porting STRAT */ +&qupv3_se8_i2c { + qcom,clk-freq-out = <100000>; + status = "ok"; + bq27541_battery:bq27541-battery@55 { + status = "ok"; + compatible = "ti,bq27541-battery"; + reg = <0x55>; + qcom,modify-soc-smooth; + }; + + oneplus_fastchg@26{ + status = "ok"; + compatible = "microchip,oneplus_fastchg"; + reg = <0x26>; + microchip,mcu-en-gpio = <&tlmm 10 0x00>; + microchip,usb-sw-1-gpio = <&tlmm 94 0x00>; + microchip,usb-sw-2-gpio = <&tlmm 59 0x00>; + microchip,ap-clk = <&tlmm 92 0x00>; + microchip,ap-data = <&tlmm 93 0x00>; + + pinctrl-names = "mux_fastchg_active", + "mux_fastchg_suspend", + "mcu_data_active", + "mcu_data_suspend"; + pinctrl-0 = <&fastchg_active + &usb_sw_active + &ap_clk_active>; + pinctrl-1 = <&usb_sw_suspend + &fastchg_suspend + &ap_clk_suspend>; + pinctrl-2 =<&ap_data_active>; + pinctrl-3 =<&ap_data_suspend>; + op,fw-erase-count = <384>; + op,fw-addr-low = <0x88>; + op,fw-addr-high = <0>; + }; +}; + +&pm8150b_gpios { + gpio1_adc { + gpio1_adc_default: gpio1_adc_default { + pins = "gpio1"; /* GPIO 1 */ + function = "normal"; /* normal */ + bias-pull-up; + bias-high-impedance; /* DISABLE GPIO1 for ADC*/ + }; + }; + + gpio12_adc { + gpio12_adc_default: gpio12_adc_default { + pins = "gpio12"; /* GPIO 12 */ + function = "normal"; /* normal */ + bias-pull-up; + bias-high-impedance; /* DISABLE GPIO12 for ADC*/ + }; + }; +}; + +&pm8150b_vadc { + gpio12_v { + reg = ; + label = "gpio12_v"; + qcom,pre-scaling = <1 1>; + }; + gpio1_v { + reg = ;/* 0x30*/ + label = "gpio1_v"; + qcom,ratiometric; + qcom,hw-settle-time = <800>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm8150b_charger { + qcom,dc-icl-ua = <1200000>; + qcom,fcc-max-ua = <500000>; + qcom,usb-icl-ua = <1800000>; + qcom,fv-max-uv = <4365000>; + /* ibatmax setting for different temp regions */ + ibatmax-little-cold-ma = <350>; + ibatmax-cool-ma = <2000>; + ibatmax-little-cool-ma = <2100>; + ibatmax-pre-normal-ma = <2100>; + ibatmax-normal-ma = <3000>; + ibatmax-warm-ma = <1100>; + ibatmax-little-cool-thr-ma = <1900>; + ibatmax-cool-thr-ma = <1100>; + /* vbatmax setting for different temp regions */ + vbatmax-little-cold-mv = <3975>; + vbatmax-cool-mv = <4390>; + vbatmax-little-cool-mv = <4390>; + vbatmax-pre-normal-mv = <4390>; + vbatmax-normal-mv = <4390>; + vbatmax-warm-mv = <4130>; + little-cool-vbat-thr-mv = <4180>; + cool-vbat-thr-mv = <4180>; + /* vbatdet setting for different temp regions */ + vbatdet-little-cold-mv = <3700>; + vbatdet-cool-mv = <4150>; + vbatdet-little-cool-mv = <4270>; + vbatdet-pre-normal-mv = <4270>; + vbatdet-normal-mv = <4270>; + vbatdet-warm-mv = <3980>; + /* temp region settings */ + cold-bat-decidegc = <20>; + little-cold-bat-decidegc = <0>; + cool-bat-decidegc = <50>; + little-cool-bat-decidegc = <120>; + pre-normal-bat-decidegc = <160>; + warm-bat-decidegc = <450>; + hot-bat-decidegc = <500>; + qcom,otg-cl-ua = <1500000>; + op,sw-iterm-ma = <310>; + op,sw-check-full-enable; + + /*otg low battery current limit*/ + op,otg-icl-ctrl-enable; + otg-low-battery-thr = <15>; + otg-low-bat-icl-thr = <1000000>; + otg-normal-bat-icl-thr = <1500000>; + //disable-pd; + qcom,lpd-disable; + /*add to disable HVDCP*/ + qcom,hvdcp-disable; + /*usb connector hw auto detection*/ + op,usb-check = <&tlmm 91 0x00>; + /* other settings */ + qcom,cutoff-voltage-with-charger = <3250>; + qcom,msm-bus,name = "dash_clk_vote"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <1 731 0 300000000>, + <1 731 0 0>; + /*ffc temp region*/ + ffc-pre-normal-decidegc = <160>; + ffc-normal-decidegc = <350>; + ffc-warm-decidegc = <400>; + ffc-normal-fcc-ma = <650>; + ffc-warm-fcc-ma = <750>; + ffc-normal-cutoff-ma = <550>; + ffc-warm-cutoff-ma = <650>; + ffc-full-vbat-mv = <4430>; + + /* for external ship mode suppot */ + pinctrl-names = "op_ship_mode_default","op_usb_temp_adc_default"; + pinctrl-0 = <&ship_mode_default>; + pinctrl-1= <&gpio1_adc_default>; + + op,stm-ctrl-gpio = <&tlmm 21 0x00>; + /* for usb connector temp protect */ + op,low-voltage-charger; + io-channels = <&pm8150b_vadc ADC_MID_CHG_DIV6>, + <&pm8150b_vadc ADC_USB_IN_V_16>, + <&pm8150b_vadc ADC_USB_IN_I>, + <&pm8150b_vadc ADC_CHG_TEMP>, + <&pm8150b_vadc ADC_AMUX_THM4_PU1>, + <&pm8150b_vadc ADC_VPH_PWR>, + <&pm8150b_vadc ADC_SBUx>; + io-channel-names = "mid_voltage", + "usb_in_voltage", + "usb_in_current", + "chg_temp", + "gpio1_voltage", + "vph_voltage", + "sbux_res"; + op,vbus-ctrl-gpio = <&pm8150l_gpios 9 GPIO_ACTIVE_LOW>; +}; + +&pm8150b_fg { + qcom,fg-force-load-profile; + oem,use_external_fg; + qcom,fg-rsense-sel = <0>; + qcom,fg-sys-term-current = <180>; + qcom,fg-chg-term-current = <165>; +}; + +&tlmm { + pm8150b_charger { + ship_mode_default: ship_mode_default { + mux { + pins = "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio21"; + drive-strength = <8>; + bias-pull-down; + }; + }; + }; + + oneplus_fastchg { + usb_sw_active: usb_sw_active { + mux { + pins = "gpio94", "gpio59"; + function = "gpio"; + }; + + config { + pins = "gpio94", "gpio59"; + drive-strength = <16>; + bias-pull-down; + }; + }; + + usb_sw_suspend: usb_sw_suspend { + mux { + pins = "gpio94", "gpio59"; + function = "gpio"; + }; + + config { + pins = "gpio94", "gpio59"; + drive-strength = <2>; + bias-disable; + }; + }; + + fastchg_active: fastchg_active { + mux { + pins = "gpio10"; + function = "gpio"; + }; + + config { + pins = "gpio10"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + fastchg_suspend: fastchg_suspend { + mux { + pins = "gpio10"; + function = "gpio"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>; + bias-disable; + }; + }; + + ap_clk_active: ap_clk_active { + mux { + pins = "gpio92"; + function = "gpio"; + }; + + config { + pins = "gpio92"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + ap_clk_suspend: ap_clk_suspend { + mux { + pins = "gpio92"; + function = "gpio"; + }; + + config { + pins = "gpio92"; + drive-strength = <2>; + bias-disable; + }; + }; + + ap_data_active: ap_data_active { + mux { + pins = "gpio93"; + function = "gpio"; + }; + + config { + pins = "gpio93"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + ap_data_suspend: ap_data_suspend { + mux { + pins = "gpio93"; + function = "gpio"; + }; + + config { + pins = "gpio93"; + drive-strength = <2>; + bias-disable; + }; + }; + }; +}; +/* @bsp, 2018/07/20 Battery & Charging porting END */ +/* @bsp,step motor START*/ +&pm8150b_gpios { + motor_mode0_gpio: motor_mode0_gpio { + pins = "gpio5"; /* GPIO 5 */ + function = "normal"; /* normal */ + output-high; + bias-disable; /* No Pull */ + }; + motor_mode0_hi_impedance: motor_mode0_hi_impedance { + pins = "gpio5"; /* GPIO 5 */ + function = "normal"; /* normal */ + bias-high-impedance; + }; + motor_boost_en: motor_boost_en { + pins = "gpio12"; /* GPIO 12 */ + function = "normal"; /* normal */ + output-low; + bias-disable; /* No Pull */ + }; + ab_id2 { + ab_id2_default: ab_id2_default { + pins = "gpio2"; + function = "normal"; + input-enable; + bias-disable; + power-source = <0>; + }; + }; +}; + +&pm8150l_gpios { + motor_pwm_config: motor_pwm_config { + pins = "gpio10"; + function = "func1"; + bias-disable; + power-source = <0>; + output-low; + qcom,drive-strength = <3>; + drive-push-pull; + }; + motor_mode1_gpio: motor_mode1_gpio { + pins = "gpio8"; + function = "normal"; + power-source = <0>; /* 3.6V */ + bias-disable; /* No Pull */ + output-low; /* digital output, no invert */ + qcom,drive-strength = <3>; /* LOW strength */ + }; + motor_dir_gpio: motor_dir_gpio { + pins = "gpio11"; + function = "normal"; + bias-disable; /* No Pull */ + power-source = <0>; /* VIN0 3.6V*/ + output-low; /* digital output, no invert */ + qcom,drive-strength = <3>; /* LOW strength */ + }; +}; + +&pm8150_gpios { + motor_sleep_gpio: motor_sleep_gpio { + pins = "gpio10"; + function = "normal"; + power-source = <0>; + bias-disable; + output-low; + }; + fp_id1_init: fp_id1_init { + pins = "gpio3"; + function = "normal"; + power-source = <0>; + bias-disable; + input-enable; + }; +}; + +&vendor { + step_motor { + compatible = "oneplus,step-motor"; + status = "okay"; + + pwms = <&pm8150l_pwm 1 20000000>; + op,boost-en-pin = <&pm8150b_gpios 12 GPIO_ACTIVE_LOW>; + op,mode0-pin = <&pm8150b_gpios 5 GPIO_ACTIVE_LOW>; + op,mode1-pin = <&pm8150l_gpios 8 GPIO_ACTIVE_LOW>; + op,nsleep-pin = <&pm8150_gpios 10 GPIO_ACTIVE_LOW>; + op,dir-pin = <&pm8150l_gpios 11 GPIO_ACTIVE_LOW>; + op,step-pin = <&pm8150l_gpios 10 GPIO_ACTIVE_LOW>; + pinctrl-names = "boost", + "m0_gpio", + "m0_high_impedance", + "m1_gpio", + "sleep_gpio", + "dir_gpio", + "pwm_config"; + pinctrl-0 = <&motor_boost_en>; + pinctrl-1 = <&motor_mode0_gpio>; + pinctrl-2 = <&motor_mode0_hi_impedance>; + pinctrl-3 = <&motor_mode1_gpio>; + pinctrl-4 = <&motor_sleep_gpio>; + pinctrl-5 = <&motor_dir_gpio>; + pinctrl-6 = <&motor_pwm_config>; + }; +}; + +&usb1 { + status = "disabled"; +}; + +/* @bsp,step motor END*/ + +&extcon_usb1 { + status = "disabled"; +}; + +&usb1 { + extcon = <&extcon_usb1>; + status = "disabled"; +}; + +&spmi_bus { + qcom,pm8009@10 { + compatible = "qcom,spmi-pmic"; + reg = <0xa SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + + pm8009_gpios: pinctrl@c000 { + compatible = "qcom,spmi-gpio"; + reg = <0xc000 0x400>; + interrupts = <0xa 0xc0 0 IRQ_TYPE_NONE>, + <0xa 0xc1 0 IRQ_TYPE_NONE>, + <0xa 0xc2 0 IRQ_TYPE_NONE>, + <0xa 0xc3 0 IRQ_TYPE_NONE>; + interrupt-names = "pm8009_gpio1", "pm8009_gpio2", + "pm8009_gpio3", "pm8009_gpio4"; + gpio-controller; + #gpio-cells = <2>; + }; + }; + /*power key + vol down long press hard reset*/ + qcom,pm8150@0 { + qcom,power-on@800 { + interrupts = <0x0 0x8 0x0 IRQ_TYPE_NONE>, + <0x0 0x8 0x1 IRQ_TYPE_NONE>, + <0x0 0x8 0x5 IRQ_TYPE_NONE>; + interrupt-names = "kpdpwr", "resin", "kpdpwr-resin-bark"; + qcom,s3-src = "kpdpwr-and-resin"; + qcom,pon_1 { + qcom,support-reset = <0>; + qcom,s1-timer = <6720>; + qcom,s2-timer = <2000>; + qcom,s2-type = ; + qcom,pull-up; + }; + + qcom,pon_2 { + qcom,support-reset = <0>; + qcom,s1-timer = <6720>; + qcom,s2-timer = <2000>; + qcom,s2-type = ; + qcom,pull-up; + }; + + qcom,pon_3 { + qcom,pon-type = ; + qcom,support-reset = <0>; + qcom,s1-timer = <6720>; + qcom,s2-timer = <2000>; + qcom,s2-type = ; + qcom,pull-up; + }; + }; + }; +}; +&pm8150_gpios { + key_vol_down { + key_vol_down_default: key_vol_down_default { + pins = "gpio7"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <1>; + }; + }; + ab_id1 { + ab_id1_default: ab_id1_default { + pins = "gpio1"; + function = "normal"; + input-enable; + bias-disable; + power-source = <0>; + }; + }; +}; + +&soc { + gpio_keys { + pinctrl-0 = <&key_vol_up_default &key_vol_down_default>; + vol_down { + label = "volume_down"; + gpios = <&pm8150_gpios 7 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + }; + + bootloader_log { + compatible = "bootloader_log"; + linux,contiguous-region = <&bootloader_log_mem>; + }; +}; + +&reserved_memory { + + bootloader_log_mem: bootloader_log_mem@0x9FFF7000 { + reg = <0 0x9FFF7000 0 0x00009000>; + label = "bootloader_log_mem"; + }; + + param_mem: param_mem@ac200000 { + reg = <0 0xAC200000 0 0x00100000>; + label = "param_mem"; + }; + + //after cdsp_sec_mem + ramoops: ramoops@0xA9800000 { + compatible = "ramoops"; + reg = <0 0xA9800000 0 0x00400000>; + record-size = <0x40000>; //256x1024 + console-size = <0x40000>; + ftrace-size = <0x40000>; + pmsg-size= <0x200000>; + devinfo-size= <0x01000>; + ecc-size= <0x0>; + }; + + mtp_mem: mtp_mem@ac300000 { + reg = <0 0xAC300000 0 0x00B00000>; + label = "mtp_mem"; + }; +}; + +&pm8009_gpios { + pm8009_gpios_pinctl: pm8009_gpios_pinctl { + + rf_cable_ant1: rf_cable_ant1{ + pins = "gpio3"; + function = "normal"; + power-source = <1>; + bias-pull-up; + qcom,pull-up-strength = <0>; /* 30uA pull up */ + input-enable; /* digital input */ + }; + rf_cable_ant3: rf_cable_ant3 { + pins = "gpio4"; + function = "normal"; + power-source = <1>; + bias-pull-up; + qcom,pull-up-strength = <0>; /* 30uA pull up */ + input-enable; /* digital input */ + }; + }; +}; + +&soc { + oem_aboard_check:oem_aboard_check { + compatible = "oem,aboard"; + interrupt-parent = <&tlmm>; + oem,aboard-gpio-0 = <&pm8150_gpios 1 0>; + oem,aboard-gpio-1 = <&pm8150b_gpios 2 0>; + pinctrl-names = "oem_aboard_active"; + pinctrl-0 = <&ab_id1_default &ab_id2_default>; + }; + oem_serial_pinctrl { + compatible = "oem,oem_serial_pinctrl"; + pinctrl-names = "uart_pinctrl_active","uart_pinctrl_deactive"; + pinctrl-0 = <&qupv3_se12_2uart_active>; + pinctrl-1 = <&qupv3_se12_2uart_oem_sleep>; + }; + + oem_rf_cable:oem_rf_cable { + compatible = "oem,rf_cable"; + interrupt-parent = <&tlmm>; + rf,cable-gpio-0 = <&tlmm 36 0>; + rf,cable-gpio-1 = <&pm8009_gpios 4 0>; + rf,cable-support-timer = <0>; + pinctrl-names = "oem_rf_cable_active"; + pinctrl-0 = <&rf_cable_ant0_active &rf_cable_ant1 &rf_cable_ant3 >; + }; +}; + +&tlmm { + rf_cable_ant0_active: rf_cable_ant0_active { + mux { + pins = "gpio36"; + function = "gpio"; + }; + config { + pins = "gpio36"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se12_2uart_oem_sleep: qupv3_se12_2uart_oem_sleep { + mux { + pins = "gpio85", "gpio86"; + function = "gpio"; + }; + config { + pins = "gpio85", "gpio86"; + drive-strength = <2>; + bias-pull-down; + }; + }; +}; + +&qupv3_se12_2uart { + compatible = "qcom,msm-geni-console-oem"; +}; + +/*disable smb3190 config */ +&smb1390 { + status = "disabled"; +}; +&smb1390_charger { + status = "disabled"; +}; +&smb1355 { + status = "disabled"; +}; +&smb1355_charger { + status = "disabled"; +}; + +/* neil.sun@Connectivity, 2019/05/16, disable SMMU S1 for WLAN and ipa */ +&ipa_smmu_wlan { + qcom,smmu-s1-bypass; +}; + +&icnss { + qcom,smmu-s1-bypass; +}; +/* #endif VENDOR_EDIT */ + +/* eleven.xie@Connectivity, 2019/05/20, disable wil6210 dts config */ +&wil6210 { + status = "disabled"; +}; + + diff --git a/arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi b/arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi index a771977a5bf87a3f7b368025fc84ed53ab96ab82..d37a1aaab0963eecc77cccf1070f9a0ad2cce207 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi @@ -163,9 +163,6 @@ qcom,vreg-0.9-voltage-level = <880000 880000 24000>; qcom,vreg-cx-voltage-level = ; - qcom,bw-scale = ; msi-parent = <&pcie0_msi>; @@ -486,9 +483,6 @@ qcom,vreg-0.9-voltage-level = <880000 880000 24000>; qcom,vreg-cx-voltage-level = ; - qcom,bw-scale = ; msi-parent = <&pcie1_msi>; diff --git a/arch/arm64/boot/dts/qcom/sm8150-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/sm8150-pinctrl.dtsi index 29df85b5fe8273e170cc1f97617b2b3bf7e83643..416bba8e3bd854ac6440a05df15bbf4acb7cb0ab 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-pinctrl.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-pinctrl.dtsi @@ -69,14 +69,14 @@ storage_cd: storage_cd { mux { - pins = "gpio96"; - function = "gpio"; + /*pins = "gpio96"; + function = "gpio";*/ }; config { - pins = "gpio96"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 MA */ + /*pins = "gpio96";*/ + /*bias-pull-up;*/ /* pull up */ + /*drive-strength = <2>;*/ /* 2 MA */ }; }; @@ -513,14 +513,14 @@ wil6210_refclk3_en_pin: wil6210_refclk3_en_pin { mux { - pins = "gpio87"; - function = "gpio"; + /*pins = "gpio87"; + function = "gpio";*/ }; config { - pins = "gpio87"; - bias-pull-down; /* PULL DOWN */ - drive-strength = <2>; /* 2 MA */ + /*pins = "gpio87";*/ + /*bias-pull-down;*/ /* PULL DOWN */ + /*drive-strength = <2>;*/ /* 2 MA */ }; }; @@ -1689,7 +1689,8 @@ config { pins = "gpio55", "gpio56"; drive-strength = <2>; - bias-pull-up; + bias-disable; + input-enable; }; }; }; @@ -4285,456 +4286,6 @@ }; }; - hs1_i2s_mclk { - hs1_i2s_mclk_sleep: hs1_i2s_mclk_sleep { - mux { - pins = "gpio155"; - function = "gpio"; - }; - - config { - pins = "gpio155"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs1_i2s_mclk_active: hs1_i2s_mclk_active { - mux { - pins = "gpio155"; - function = "hs1_mi2s"; - }; - - config { - pins = "gpio155"; - drive-strength = <8>; /* 8 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs1_i2s_sck { - hs1_i2s_sck_sleep: hs1_i2s_sck_sleep { - mux { - pins = "gpio156"; - function = "gpio"; - }; - - config { - pins = "gpio156"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs1_i2s_sck_active: hs1_i2s_sck_active { - mux { - pins = "gpio156"; - function = "hs1_mi2s"; - }; - - config { - pins = "gpio156"; - drive-strength = <8>; /* 8 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs1_i2s_ws { - hs1_i2s_ws_sleep: hs1_i2s_ws_sleep { - mux { - pins = "gpio157"; - function = "gpio"; - }; - - config { - pins = "gpio157"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs1_i2s_ws_active: hs1_i2s_ws_active { - mux { - pins = "gpio157"; - function = "hs1_mi2s"; - }; - - config { - pins = "gpio157"; - drive-strength = <8>; /* 8 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs1_i2s_data0 { - hs1_i2s_data0_sleep: hs1_i2s_data0_sleep { - mux { - pins = "gpio158"; - function = "sleep"; - }; - - config { - pins = "gpio158"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs1_i2s_data0_active: hs1_i2s_data0_active { - mux { - pins = "gpio158"; - function = "hs1_mi2s"; - }; - - config { - pins = "gpio158"; - drive-strength = <8>; /* 8 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs1_i2s_data1 { - hs1_i2s_data1_sleep: hs1_i2s_data1_sleep { - mux { - pins = "gpio159"; - function = "gpio"; - }; - - config { - pins = "gpio159"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs1_i2s_data1_active: hs1_i2s_data1_active { - mux { - pins = "gpio159"; - function = "hs1_mi2s"; - }; - - config { - pins = "gpio159"; - drive-strength = <8>; /* 8 mA */ - bias-disable; /* NO PULL */ - input-enable; - }; - }; - }; - - hs2_i2s_mclk { - hs2_i2s_mclk_sleep: hs2_i2s_mclk_sleep { - mux { - pins = "gpio160"; - function = "gpio"; - }; - - config { - pins = "gpio160"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs2_i2s_mclk_active: hs2_i2s_mclk_active { - mux { - pins = "gpio160"; - function = "hs2_mi2s"; - }; - - config { - pins = "gpio160"; - drive-strength = <8>; /* 8 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs2_i2s_sck { - hs2_i2s_sck_sleep: hs2_i2s_sck_sleep { - mux { - pins = "gpio161"; - function = "gpio"; - }; - - config { - pins = "gpio161"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs2_i2s_sck_active: hs2_i2s_sck_active { - mux { - pins = "gpio161"; - function = "hs2_mi2s"; - }; - - config { - pins = "gpio161"; - drive-strength = <8>; /* 8 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs2_i2s_ws { - hs2_i2s_ws_sleep: hs2_i2s_ws_sleep { - mux { - pins = "gpio162"; - function = "gpio"; - }; - - config { - pins = "gpio162"; - drive-strength = <2>; /* 8 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs2_i2s_ws_active: hs2_i2s_ws_active { - mux { - pins = "gpio162"; - function = "hs2_mi2s"; - }; - - config { - pins = "gpio162"; - drive-strength = <8>; /* 8 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs2_i2s_data0 { - hs2_i2s_data0_sleep: hs2_i2s_data0_sleep { - mux { - pins = "gpio163"; - function = "gpio"; - }; - - config { - pins = "gpio163"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs2_i2s_data0_active: hs2_i2s_data0_active { - mux { - pins = "gpio163"; - function = "hs2_mi2s"; - }; - - config { - pins = "gpio163"; - drive-strength = <8>; /* 8 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs2_i2s_data1 { - hs2_i2s_data1_sleep: hs2_i2s_data1_sleep { - mux { - pins = "gpio164"; - function = "gpio"; - }; - - config { - pins = "gpio164"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs2_i2s_data1_active: hs2_i2s_data1_active { - mux { - pins = "gpio164"; - function = "hs2_mi2s"; - }; - - config { - pins = "gpio164"; - drive-strength = <8>; /* 8 mA */ - bias-disable; /* NO PULL */ - input-enable; - }; - }; - }; - - hs3_i2s_mclk { - hs3_i2s_mclk_sleep: hs3_i2s_mclk_sleep { - mux { - pins = "gpio125"; - function = "gpio"; - }; - - config { - pins = "gpio125"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs3_i2s_mclk_active: hs3_i2s_mclk_active { - mux { - pins = "gpio125"; - function = "hs3_mi2s"; - }; - - config { - pins = "gpio125"; - drive-strength = <8>; /* 8 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs3_i2s_sck { - hs3_i2s_sck_sleep: hs3_i2s_sck_sleep { - mux { - pins = "gpio165"; - function = "gpio"; - }; - - config { - pins = "gpio165"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs3_i2s_sck_active: hs3_i2s_sck_active { - mux { - pins = "gpio165"; - function = "hs3_mi2s"; - }; - - config { - pins = "gpio165"; - drive-strength = <8>; /* 8 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs3_i2s_ws { - hs3_i2s_ws_sleep: hs3_i2s_ws_sleep { - mux { - pins = "gpio166"; - function = "gpio"; - }; - - config { - pins = "gpio166"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs3_i2s_ws_active: hs3_i2s_ws_active { - mux { - pins = "gpio166"; - function = "hs3_mi2s"; - }; - - config { - pins = "gpio166"; - drive-strength = <8>; /* 8 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs3_i2s_data0 { - hs3_i2s_data0_sleep: hs3_i2s_data0_sleep { - mux { - pins = "gpio167"; - function = "gpio"; - }; - - config { - pins = "gpio167"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs3_i2s_data0_active: hs3_i2s_data0_active { - mux { - pins = "gpio167"; - function = "hs3_mi2s"; - }; - - config { - pins = "gpio167"; - drive-strength = <8>; /* 8 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs3_i2s_data1 { - hs3_i2s_data1_sleep: hs3_i2s_data1_sleep { - mux { - pins = "gpio168"; - function = "gpio"; - }; - - config { - pins = "gpio168"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs3_i2s_data1_active: hs3_i2s_data1_active { - mux { - pins = "gpio168"; - function = "hs3_mi2s"; - }; - - config { - pins = "gpio168"; - drive-strength = <8>; /* 8 mA */ - bias-disable; /* NO PULL */ - input-enable; - }; - }; - }; - emac { emac_mdc: emac_mdc { mux { diff --git a/arch/arm64/boot/dts/qcom/sm8150-regulator.dtsi b/arch/arm64/boot/dts/qcom/sm8150-regulator.dtsi index 40a4ab37f02a850e4d4fb08cf1d7d1eff3147da5..e12333e4bc0979d1f71336fbf000f3eaea19cf17 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-regulator.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-regulator.dtsi @@ -909,13 +909,13 @@ }; rpmh-regulator-ldof2 { - compatible = "qcom,rpmh-xob-regulator"; + compatible = "qcom,rpmh-vrm-regulator"; mboxes = <&apps_rsc 0>; qcom,resource-name = "ldof2"; L2F: pm8009_l2: regulator-pm8009-l2 { regulator-name = "pm8009_l2"; qcom,set = ; - regulator-min-microvolt = <1200000>; + regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1200000>; }; }; @@ -944,6 +944,54 @@ }; }; + rpmh-regulator-ldof1 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldof1"; + L1F: pm8009_l1: regulator-pm8009-l1 { + regulator-name = "pm8009_l1"; + qcom,set = ; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + }; + }; + + rpmh-regulator-ldof3 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldof3"; + L3F: pm8009_l3: regulator-pm8009-l3 { + regulator-name = "pm8009_l3"; + qcom,set = ; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + }; + }; + + rpmh-regulator-ldof4 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldof4"; + L4F: pm8009_l4: regulator-pm8009-l4 { + regulator-name = "pm8009_l4"; + qcom,set = ; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + }; + }; + + rpmh-regulator-ldof7 { + compatible = "qcom,rpmh-xob-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldof7"; + L7F: pm8009_l7: regulator-pm8009-l7 { + regulator-name = "pm8009_l7"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + refgen: refgen-regulator@88e7000 { compatible = "qcom,refgen-regulator"; reg = <0x88e7000 0x60>; diff --git a/arch/arm64/boot/dts/qcom/sm8150-sde-display.dtsi b/arch/arm64/boot/dts/qcom/sm8150-sde-display.dtsi old mode 100644 new mode 100755 index 58bb42baefe7f062e4a42c4d1c4c741bdc4b79fb..31318f685946f1a2b16a1ac3853ddaac0b1db89d --- a/arch/arm64/boot/dts/qcom/sm8150-sde-display.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-sde-display.dtsi @@ -33,6 +33,11 @@ #include "dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi" #include "dsi-panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi" #include +#include "dsi-panel-samsung_oneplus_dsc.dtsi" +#include "dsi-panel-samsung_s6e3fc2x01.dtsi" +#include "dsi-panel-samsung_sofef03f_m_fhd_dsc_cmd.dtsi" +#include "dsi-panel-samsung_sofef00_m_video.dtsi" + &tlmm { display_panel_avdd_eldo_default: display_panel_avdd_eldo_default { @@ -174,7 +179,7 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-enable-ramp-delay = <233>; - gpio = <&tlmm 130 0>; +// gpio = <&tlmm 130 0>; enable-active-high; regulator-boot-on; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/sm8150-sdxprairie-mtp-overlay.dts b/arch/arm64/boot/dts/qcom/sm8150-sdxprairie-mtp-overlay.dts old mode 100644 new mode 100755 index 94a61455100ec5c8aa50bd3e56630195f8996dee..8e62d71f77633858e71f6d21e279f6743432eee2 --- a/arch/arm64/boot/dts/qcom/sm8150-sdxprairie-mtp-overlay.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-sdxprairie-mtp-overlay.dts @@ -24,6 +24,8 @@ #include "sm8150-sdxprairie.dtsi" #include "sm8150-mtp-audio-overlay.dtsi" +#include "sm8150-oem.dtsi" + / { model = "SDXPRAIRIE MTP"; compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; diff --git a/arch/arm64/boot/dts/qcom/sm8150-sdxprairie.dtsi b/arch/arm64/boot/dts/qcom/sm8150-sdxprairie.dtsi index 19e713aacb6f3304482df49e22b08f1091d820bf..2c01b219613a7ea0d3f66cc445700752d1d14218 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-sdxprairie.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-sdxprairie.dtsi @@ -42,8 +42,7 @@ }; mhi_chan@25 { - mhi,num-elements = <32>; - mhi,event-ring = <1>; + status = "disabled"; }; mhi_chan@80 { @@ -91,6 +90,7 @@ mhi_devices { mhi_qrtr { + mhi,chan = "IPCR"; qcom,net-id = <3>; }; }; @@ -206,6 +206,16 @@ status = "disabled"; }; + +&icnss { + esoc-names = "mdm"; + esoc-0 = <&mdm3>; +}; + +&icnss { + qcom,clk-monitor-enable; +}; + &soc { qmi-tmd-devices { compatible = "qcom,qmi-cooling-devices"; diff --git a/arch/arm64/boot/dts/qcom/sm8150-thermal-overlay.dtsi b/arch/arm64/boot/dts/qcom/sm8150-thermal-overlay.dtsi index 643bb84e36699c2a13b58c0c3de2682569959de9..87e75cf559e7e8a66071513f59a39210e615d65e 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-thermal-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-thermal-overlay.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -127,134 +127,169 @@ soc { cooling-maps { - soc_cpu4 { - trip = <&soc_trip>; + soctrip_cpu4 { + trip = <&soc_trip2>; cooling-device = - <&CPU4 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; + <&CPU4 6 6>; }; - soc_cpu5 { - trip = <&soc_trip>; + soctrip_cpu7 { + trip = <&soc_trip2>; cooling-device = - <&CPU5 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; }; - soc_cpu6 { + soctrip_cpu6 { trip = <&soc_trip>; cooling-device = <&CPU6 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - soc_cpu7 { - trip = <&soc_trip>; - cooling-device = - <&CPU7 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; + THERMAL_MAX_LIMIT>; }; }; }; - pm8150b-bcl-lvl0 { + pm8150b-vbat-lvl0 { cooling-maps { vbat_cpu4 { - trip = <&b_bcl_lvl0>; + trip = <&vbat_lvl0>; cooling-device = <&CPU4 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; vbat_cpu5 { - trip = <&b_bcl_lvl0>; + trip = <&vbat_lvl0>; cooling-device = <&CPU5 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; vbat_gpu0 { - trip = <&b_bcl_lvl0>; + trip = <&vbat_lvl0>; cooling-device = <&msm_gpu 2 2>; }; }; }; - pm8150b-bcl-lvl1 { + pm8150b-vbat-lvl1 { cooling-maps { vbat_cpu6 { - trip = <&b_bcl_lvl1>; + trip = <&vbat_lvl1>; cooling-device = <&CPU6 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; vbat_cpu7 { - trip = <&b_bcl_lvl1>; + trip = <&vbat_lvl1>; cooling-device = <&CPU7 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; vbat_gpu1 { - trip = <&b_bcl_lvl1>; + trip = <&vbat_lvl1>; cooling-device = <&msm_gpu 4 4>; }; }; }; - pm8150b-bcl-lvl2 { + pm8150b-vbat-lvl2 { cooling-maps { vbat_gpu2 { - trip = <&b_bcl_lvl2>; + trip = <&vbat_lvl2>; cooling-device = <&msm_gpu THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; }; }; - pm8150l-bcl-lvl0 { + pm8150b-ibat-lvl0 { + cooling-maps { + ibat_cpu4 { + trip = <&ibat_lvl0>; + cooling-device = + <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + ibat_cpu5 { + trip = <&ibat_lvl0>; + cooling-device = + <&CPU5 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + ibat_gpu0 { + trip = <&ibat_lvl0>; + cooling-device = <&msm_gpu 2 2>; + }; + }; + }; + + pm8150b-ibat-lvl1 { + cooling-maps { + ibat_cpu6 { + trip = <&ibat_lvl1>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + ibat_cpu7 { + trip = <&ibat_lvl1>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + ibat_gpu1 { + trip = <&ibat_lvl1>; + cooling-device = <&msm_gpu 4 4>; + }; + }; + }; + + pm8150l-vph-lvl0 { disable-thermal-zone; cooling-maps { vph_cpu4 { - trip = <&l_bcl_lvl0>; + trip = <&vph_lvl0>; cooling-device = <&CPU4 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; vph_cpu5 { - trip = <&l_bcl_lvl0>; + trip = <&vph_lvl0>; cooling-device = <&CPU5 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; vph_gpu0 { - trip = <&l_bcl_lvl0>; + trip = <&vph_lvl0>; cooling-device = <&msm_gpu 2 2>; }; }; }; - pm8150l-bcl-lvl1 { + pm8150l-vph-lvl1 { disable-thermal-zone; cooling-maps { vph_cpu6 { - trip = <&l_bcl_lvl1>; + trip = <&vph_lvl1>; cooling-device = <&CPU6 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; vph_cpu7 { - trip = <&l_bcl_lvl1>; + trip = <&vph_lvl1>; cooling-device = <&CPU7 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; vph_gpu1 { - trip = <&l_bcl_lvl1>; + trip = <&vph_lvl1>; cooling-device = <&msm_gpu 4 4>; }; }; }; - pm8150l-bcl-lvl2 { + pm8150l-vph-lvl2 { disable-thermal-zone; cooling-maps { vph_gpu2 { - trip = <&l_bcl_lvl2>; + trip = <&vph_lvl2>; cooling-device = <&msm_gpu THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8150-thermal.dtsi b/arch/arm64/boot/dts/qcom/sm8150-thermal.dtsi index 59c7e913659c765048fbbb526e7a8a40cd9651d0..79460e4d4401cd95c3c12ec9f7f8949c12dc118e 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-thermal.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-thermal.dtsi @@ -774,8 +774,8 @@ }; gpuss-max-step { - polling-delay-passive = <10>; - polling-delay = <100>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-governor = "step_wise"; wake-capable-sensor; trips { diff --git a/arch/arm64/boot/dts/qcom/sm8150-usb.dtsi b/arch/arm64/boot/dts/qcom/sm8150-usb.dtsi index 210ead532d21f0601c1b0d51c2483bb4c0e80916..cc1d4930aa87d4238466c729e872addf0ed31177 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-usb.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-usb.dtsi @@ -61,6 +61,7 @@ 0x144 /* GSI_RING_BASE_ADDR_H */ 0x1a4>; /* GSI_IF_STS */ qcom,dwc-usb3-msm-tx-fifo-size = <27696>; + qcom,pm-qos-latency = <44>; qcom,msm-bus,name = "usb0"; qcom,msm-bus,num-cases = <4>; @@ -98,10 +99,11 @@ snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; snps,ssp-u3-u0-quirk; - snps,usb3-u1u2-disable; + //snps,usb3-u1u2-disable; usb-core-id = <0>; tx-fifo-resize; - maximum-speed = "super-speed-plus"; + maximum-speed = "super-speed"; + //maximum-speed = "super-speed-plus"; dr_mode = "otg"; }; @@ -386,6 +388,7 @@ 0x1a4>; /* GSI_IF_STS */ qcom,dwc-usb3-msm-tx-fifo-size = <27696>; qcom,charging-disabled; + qcom,pm-qos-latency = <44>; qcom,msm-bus,name = "usb1"; qcom,msm-bus,num-cases = <3>; diff --git a/arch/arm64/boot/dts/qcom/sm8150-v2-camera.dtsi b/arch/arm64/boot/dts/qcom/sm8150-v2-camera.dtsi index c0793f3d7c87956af073ec6cda66b3d8d2095193..9bcdf51cfe091431908cc27700a143018fd0466a 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-v2-camera.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-v2-camera.dtsi @@ -238,7 +238,7 @@ /* Shared region is 150MB long */ iova-region-name = "shared"; iova-region-start = <0x7400000>; - iova-region-len = <0x9600000>; + iova-region-len = <0xc800000>; iova-region-id = <0x1>; status = "ok"; }; @@ -246,7 +246,7 @@ iova-mem-region-secondary-heap { /* Secondary heap region is 1MB long */ iova-region-name = "secheap"; - iova-region-start = <0x10A00000>; + iova-region-start = <0x13C00000>; iova-region-len = <0x100000>; iova-region-id = <0x4>; status = "ok"; @@ -255,8 +255,8 @@ iova-mem-region-io { /* IO region is approximately 3.3 GB */ iova-region-name = "io"; - iova-region-start = <0x10C00000>; - iova-region-len = <0xCF300000>; + iova-region-start = <0x13E00000>; + iova-region-len = <0xCC100000>; iova-region-id = <0x3>; status = "ok"; }; @@ -264,7 +264,7 @@ iova-mem-qdss-region { /* QDSS region is appropriate 1MB */ iova-region-name = "qdss"; - iova-region-start = <0x10B00000>; + iova-region-start = <0x13D00000>; iova-region-len = <0x100000>; iova-region-id = <0x5>; qdss-phy-addr = <0x16790000>; diff --git a/arch/arm64/boot/dts/qcom/sm8150-v2.dtsi b/arch/arm64/boot/dts/qcom/sm8150-v2.dtsi index 737195c6a3ea80b3fc9e556006d8c0a41f214a07..a94098ec58ca7253064537c9c9cb57f544d84700 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-v2.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-v2.dtsi @@ -1128,6 +1128,12 @@ USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0 USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x00 0 USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x00 0 + /*op do optimize A/B side 0x1214/0x1614:0x06 0x1308/0x1708:0x0c + *0x120C/0x160C:0x06 + */ + USB3_DP_QSERDES_TXA_TX_DRV_LVL 0x06 0 + USB3_DP_QSERDES_TXA_PRE_EMPH 0x0c 0 + USB3_DP_QSERDES_TXA_TX_EMP_POST1_LVL 0x06 0 USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x16 0 USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x05 0 USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x20 0 @@ -1171,6 +1177,12 @@ USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12 0 USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x00 0 USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x00 0 + /*op do optimize A/B side 0x1214/0x1614:0x06 0x1308/0x1708:0x0c + *0x120C/0x160C:0x06 + */ + USB3_DP_QSERDES_TXB_TX_DRV_LVL 0x06 0 + USB3_DP_QSERDES_TXB_PRE_EMPH 0x0c 0 + USB3_DP_QSERDES_TXB_TX_EMP_POST1_LVL 0x06 0 USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x16 0 USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x05 0 USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x01 0 diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 2799385f733a76d82f1bb82f9b083cbf98ad6316..f5e52a2e1f4814813375d2e6195b8163080eeab1 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -580,7 +580,7 @@ compatible = "android,fstab"; vendor { compatible = "android,vendor"; - dev = "/dev/block/platform/soc/8804000.sdhci/by-name/vendor"; + dev = "/dev/block/platform/soc/1d84000.sdhci/by-name/vendor"; type = "ext4"; mnt_flags = "ro,barrier=1,discard"; fsmgr_flags = "wait,slotselect,avb"; @@ -3003,7 +3003,8 @@ qcom_seecom: qseecom@87900000 { compatible = "qcom,qseecom"; - reg = <0x87900000 0x2200000>; + /* enlarge TA memory size from 34M to 62M on 2018/11/22 */ + reg = <0x87900000 0x3E00000>; reg-names = "secapp-region"; memory-region = <&qseecom_mem>; qcom,hlos-num-ce-hw-instances = <1>; @@ -3020,7 +3021,8 @@ qcom_smcinvoke: smcinvoke@87900000 { compatible = "qcom,smcinvoke"; - reg = <0x87900000 0x2200000>; + /* enlarge TA memory size from 34M to 62M on 2018/11/22 */ + reg = <0x87900000 0x3E00000>; reg-names = "secapp-region"; }; diff --git a/arch/arm64/boot/dts/qcom/trinket-thermal-overlay.dtsi b/arch/arm64/boot/dts/qcom/trinket-thermal-overlay.dtsi index 1c3a5fe6a9509a95ed4e0ba574731e619732f561..cc055b4a542ddecf2fd5a57beceeff8af65f1747 100644 --- a/arch/arm64/boot/dts/qcom/trinket-thermal-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-thermal-overlay.dtsi @@ -125,52 +125,52 @@ }; }; - pmi632-bcl-lvl0 { + pmi632-vbat-lvl0 { cooling-maps { - cpu0_cdev { - trip = <&bcl_lvl0>; + vbat_cpu0 { + trip = <&pmi632_vbat_lvl0>; cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-6) (THERMAL_MAX_LIMIT-6)>; }; - cpu1_cdev { - trip = <&bcl_lvl0>; + vbat_cpu1 { + trip = <&pmi632_vbat_lvl0>; cooling-device = <&CPU1 (THERMAL_MAX_LIMIT-6) (THERMAL_MAX_LIMIT-6)>; }; - cpu2_cdev { - trip = <&bcl_lvl0>; + vbat_cpu2 { + trip = <&pmi632_vbat_lvl0>; cooling-device = <&CPU2 (THERMAL_MAX_LIMIT-6) (THERMAL_MAX_LIMIT-6)>; }; - cpu3_cdev { - trip = <&bcl_lvl0>; + vbat_cpu3 { + trip = <&pmi632_vbat_lvl0>; cooling-device = <&CPU3 (THERMAL_MAX_LIMIT-6) (THERMAL_MAX_LIMIT-6)>; }; - cpu4_cdev { - trip = <&bcl_lvl0>; + vbat_cpu4 { + trip = <&pmi632_vbat_lvl0>; cooling-device = <&CPU4 (THERMAL_MAX_LIMIT-6) (THERMAL_MAX_LIMIT-6)>; }; - cpu5_cdev { - trip = <&bcl_lvl0>; + vbat_cpu5 { + trip = <&pmi632_vbat_lvl0>; cooling-device = <&CPU5 (THERMAL_MAX_LIMIT-6) (THERMAL_MAX_LIMIT-6)>; }; - cpu6_cdev { - trip = <&bcl_lvl0>; + vbat_cpu6 { + trip = <&pmi632_vbat_lvl0>; cooling-device = <&CPU6 (THERMAL_MAX_LIMIT-6) (THERMAL_MAX_LIMIT-6)>; }; - cpu7_cdev { - trip = <&bcl_lvl0>; + vbat_cpu7 { + trip = <&pmi632_vbat_lvl0>; cooling-device = <&CPU7 (THERMAL_MAX_LIMIT-6) (THERMAL_MAX_LIMIT-6)>; @@ -178,52 +178,52 @@ }; }; - pmi632-bcl-lvl1 { + pmi632-vbat-lvl1 { cooling-maps { - cpu0_cdev { - trip = <&bcl_lvl1>; + vbat_cpu0 { + trip = <&pmi632_vbat_lvl1>; cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-5) (THERMAL_MAX_LIMIT-5)>; }; - cpu1_cdev { - trip = <&bcl_lvl1>; + vbat_cpu1 { + trip = <&pmi632_vbat_lvl1>; cooling-device = <&CPU1 (THERMAL_MAX_LIMIT-5) (THERMAL_MAX_LIMIT-5)>; }; - cpu2_cdev { - trip = <&bcl_lvl1>; + vbat_cpu2 { + trip = <&pmi632_vbat_lvl1>; cooling-device = <&CPU2 (THERMAL_MAX_LIMIT-5) (THERMAL_MAX_LIMIT-5)>; }; - cpu3_cdev { - trip = <&bcl_lvl1>; + vbat_cpu3 { + trip = <&pmi632_vbat_lvl1>; cooling-device = <&CPU3 (THERMAL_MAX_LIMIT-5) (THERMAL_MAX_LIMIT-5)>; }; - cpu4_cdev { - trip = <&bcl_lvl1>; + vbat_cpu4 { + trip = <&pmi632_vbat_lvl1>; cooling-device = <&CPU4 (THERMAL_MAX_LIMIT-5) (THERMAL_MAX_LIMIT-5)>; }; - cpu5_cdev { - trip = <&bcl_lvl1>; + vbat_cpu5 { + trip = <&pmi632_vbat_lvl1>; cooling-device = <&CPU5 (THERMAL_MAX_LIMIT-5) (THERMAL_MAX_LIMIT-5)>; }; - cpu6_cdev { - trip = <&bcl_lvl1>; + vbat_cpu6 { + trip = <&pmi632_vbat_lvl1>; cooling-device = <&CPU6 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; - cpu7_cdev { - trip = <&bcl_lvl1>; + vbat_cpu7 { + trip = <&pmi632_vbat_lvl1>; cooling-device = <&CPU7 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; @@ -231,52 +231,158 @@ }; }; - pmi632-bcl-lvl2 { + pmi632-vbat-lvl2 { cooling-maps { - cpu0_cdev { - trip = <&bcl_lvl2>; + vbat_cpu0 { + trip = <&pmi632_vbat_lvl2>; cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-5) (THERMAL_MAX_LIMIT-5)>; }; - cpu1_cdev { - trip = <&bcl_lvl2>; + vbat_cpu1 { + trip = <&pmi632_vbat_lvl2>; cooling-device = <&CPU1 (THERMAL_MAX_LIMIT-5) (THERMAL_MAX_LIMIT-5)>; }; - cpu2_cdev { - trip = <&bcl_lvl2>; + vbat_cpu2 { + trip = <&pmi632_vbat_lvl2>; cooling-device = <&CPU2 (THERMAL_MAX_LIMIT-5) (THERMAL_MAX_LIMIT-5)>; }; - cpu3_cdev { - trip = <&bcl_lvl2>; + vbat_cpu3 { + trip = <&pmi632_vbat_lvl2>; cooling-device = <&CPU3 (THERMAL_MAX_LIMIT-5) (THERMAL_MAX_LIMIT-5)>; }; - cpu4_cdev { - trip = <&bcl_lvl2>; + vbat_cpu4 { + trip = <&pmi632_vbat_lvl2>; cooling-device = <&CPU4 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; - cpu5_cdev { - trip = <&bcl_lvl2>; + vbat_cpu5 { + trip = <&pmi632_vbat_lvl2>; cooling-device = <&CPU5 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; - cpu6_cdev { - trip = <&bcl_lvl2>; + vbat_cpu6 { + trip = <&pmi632_vbat_lvl2>; cooling-device = <&CPU6 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; - cpu7_cdev { - trip = <&bcl_lvl2>; + vbat_cpu7 { + trip = <&pmi632_vbat_lvl2>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pmi632-ibat-lvl0 { + cooling-maps { + ibat_cpu0 { + trip = <&pmi632_ibat_lvl0>; + cooling-device = + <&CPU0 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; + }; + ibat_cpu1 { + trip = <&pmi632_ibat_lvl0>; + cooling-device = + <&CPU1 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; + }; + ibat_cpu2 { + trip = <&pmi632_ibat_lvl0>; + cooling-device = + <&CPU2 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; + }; + ibat_cpu3 { + trip = <&pmi632_ibat_lvl0>; + cooling-device = + <&CPU3 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; + }; + ibat_cpu4 { + trip = <&pmi632_ibat_lvl0>; + cooling-device = + <&CPU4 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; + }; + ibat_cpu5 { + trip = <&pmi632_ibat_lvl0>; + cooling-device = + <&CPU5 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; + }; + ibat_cpu6 { + trip = <&pmi632_ibat_lvl0>; + cooling-device = + <&CPU6 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; + }; + ibat_cpu7 { + trip = <&pmi632_ibat_lvl0>; + cooling-device = + <&CPU7 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; + }; + }; + }; + + pmi632-ibat-lvl1 { + cooling-maps { + ibat_cpu0 { + trip = <&pmi632_ibat_lvl1>; + cooling-device = + <&CPU0 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + ibat_cpu1 { + trip = <&pmi632_ibat_lvl1>; + cooling-device = + <&CPU1 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + ibat_cpu2 { + trip = <&pmi632_ibat_lvl1>; + cooling-device = + <&CPU2 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + ibat_cpu3 { + trip = <&pmi632_ibat_lvl1>; + cooling-device = + <&CPU3 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + ibat_cpu4 { + trip = <&pmi632_ibat_lvl1>; + cooling-device = + <&CPU4 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + ibat_cpu5 { + trip = <&pmi632_ibat_lvl1>; + cooling-device = + <&CPU5 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + ibat_cpu6 { + trip = <&pmi632_ibat_lvl1>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + ibat_cpu7 { + trip = <&pmi632_ibat_lvl1>; cooling-device = <&CPU7 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; diff --git a/arch/arm64/boot/dts/qcom/trinket-usb.dtsi b/arch/arm64/boot/dts/qcom/trinket-usb.dtsi index bb5087492c11d57d4a6edd2a96bd0967941d6647..5a7c14dd4bb8fde198dafe6f2d5a0c0abf15d3e3 100644 --- a/arch/arm64/boot/dts/qcom/trinket-usb.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-usb.dtsi @@ -54,7 +54,6 @@ 0x144 /* GSI_RING_BASE_ADDR_H */ 0x1a4>; /* GSI_IF_STS */ qcom,dwc-usb3-msm-tx-fifo-size = <21288>; - qcom,gsi-disable-io-coherency; qcom,msm-bus,name = "usb0"; qcom,msm-bus,num-cases = <4>; diff --git a/arch/arm64/configs/vendor/atoll-perf_defconfig b/arch/arm64/configs/vendor/atoll-perf_defconfig index 3a37a69f1c58410262a19fcf007aaba3c08ffe66..0a1d220d512257f1a241027392d8de59aa3e6bef 100644 --- a/arch/arm64/configs/vendor/atoll-perf_defconfig +++ b/arch/arm64/configs/vendor/atoll-perf_defconfig @@ -67,7 +67,6 @@ CONFIG_ZSMALLOC=y CONFIG_BALANCE_ANON_FILE_RECLAIM=y CONFIG_SECCOMP=y # CONFIG_UNMAP_KERNEL_AT_EL0 is not set -CONFIG_ARM64_SSBD=y CONFIG_ARMV8_DEPRECATED=y CONFIG_SWP_EMULATION=y CONFIG_CP15_BARRIER_EMULATION=y @@ -79,6 +78,7 @@ CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y CONFIG_KRYO_PMU_WORKAROUND=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_COMPAT=y +CONFIG_PM_AUTOSLEEP=y CONFIG_PM_WAKELOCKS=y CONFIG_PM_WAKELOCKS_LIMIT=0 # CONFIG_PM_WAKELOCKS_GC is not set @@ -105,7 +105,6 @@ CONFIG_IP_MULTIPLE_TABLES=y CONFIG_IP_ROUTE_VERBOSE=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y -CONFIG_NET_IPGRE_DEMUX=y CONFIG_SYN_COOKIES=y CONFIG_NET_IPVTI=y CONFIG_INET_AH=y @@ -224,7 +223,6 @@ CONFIG_NET_CLS_FW=y CONFIG_NET_CLS_U32=y CONFIG_CLS_U32_MARK=y CONFIG_NET_CLS_FLOW=y -CONFIG_NET_CLS_BPF=y CONFIG_NET_EMATCH=y CONFIG_NET_EMATCH_CMP=y CONFIG_NET_EMATCH_NBYTE=y @@ -252,7 +250,6 @@ CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y CONFIG_DMA_CMA=y CONFIG_ZRAM=y CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_LOOP_MIN_COUNT=16 CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=8192 CONFIG_HDCP_QSEECOM=y @@ -294,13 +291,11 @@ CONFIG_PPP_FILTER=y CONFIG_PPP_MPPE=y CONFIG_PPP_MULTILINK=y CONFIG_PPPOE=y -CONFIG_PPTP=y CONFIG_PPPOL2TP=y CONFIG_PPPOLAC=y CONFIG_PPPOPNS=y CONFIG_PPP_ASYNC=y CONFIG_PPP_SYNC_TTY=y -CONFIG_USB_RTL8152=y CONFIG_USB_USBNET=y CONFIG_WIL6210=m CONFIG_WCNSS_MEM_PRE_ALLOC=y @@ -322,15 +317,6 @@ CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_RMI_DEV=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_EXTRA_SYSFS=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_TEST_REPORTING=y -CONFIG_TOUCHSCREEN_SYNAPTICS_TCM=y -CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_CORE=y -CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_TOUCH=y -CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_DEVICE=y -CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_TESTING=y -CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_REFLASH=y -CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_RECOVERY=y -CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_ZEROFLASH=y -CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_DIAGNOSTICS=y CONFIG_INPUT_MISC=y CONFIG_INPUT_QPNP_POWER_ON=y CONFIG_INPUT_UINPUT=y @@ -338,7 +324,6 @@ CONFIG_INPUT_UINPUT=y # CONFIG_LEGACY_PTYS is not set # CONFIG_DEVMEM is not set CONFIG_SERIAL_MSM_GENI=y -CONFIG_SERIAL_MSM_WITH_HALF_SAMPLING=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_MSM_LEGACY=y # CONFIG_DEVPORT is not set @@ -361,6 +346,7 @@ CONFIG_SLIMBUS_MSM_NGD=y CONFIG_PTP_1588_CLOCK=y CONFIG_PINCTRL_SX150X=y CONFIG_PINCTRL_QCOM_SPMI_PMIC=y +CONFIG_PINCTRL_SDMMAGPIE=y CONFIG_PINCTRL_ATOLL=y CONFIG_PINCTRL_SLPI=y CONFIG_GPIO_SYSFS=y @@ -384,16 +370,15 @@ CONFIG_QTI_THERMAL_LIMITS_DCVS=y CONFIG_QTI_VIRTUAL_SENSOR=y CONFIG_QTI_AOP_REG_COOLING_DEVICE=y CONFIG_QTI_QMI_COOLING_DEVICE=y -CONFIG_QTI_QMI_SENSOR=y CONFIG_REGULATOR_COOLING_DEVICE=y CONFIG_QTI_BCL_PMIC5=y CONFIG_QTI_BCL_SOC_DRIVER=y CONFIG_QTI_ADC_TM=y +CONFIG_QTI_CX_IPEAK_COOLING_DEVICE=y CONFIG_MFD_I2C_PMIC=y CONFIG_MFD_SPMI_PMIC=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_PROXY_CONSUMER=y -CONFIG_REGULATOR_PM8008=y CONFIG_REGULATOR_QPNP_AMOLED=y CONFIG_REGULATOR_QPNP_LCDB=y CONFIG_REGULATOR_REFGEN=y @@ -553,12 +538,6 @@ CONFIG_MSM_VIDEOCC_SDMMAGPIE=y CONFIG_MSM_NPUCC_SDMMAGPIE=y CONFIG_MSM_GPUCC_SDMMAGPIE=y CONFIG_MSM_DEBUGCC_SDMMAGPIE=y -CONFIG_SM_GCC_ATOLL=y -CONFIG_SM_CAMCC_ATOLL=y -CONFIG_SM_VIDEOCC_ATOLL=y -CONFIG_SM_DISPCC_ATOLL=y -CONFIG_SM_NPUCC_ATOLL=y -CONFIG_SM_DEBUGCC_ATOLL=y CONFIG_HWSPINLOCK=y CONFIG_HWSPINLOCK_QCOM=y CONFIG_QCOM_APCS_IPC=y @@ -575,6 +554,8 @@ CONFIG_RPMSG_QCOM_GLINK_SPI=y CONFIG_QCOM_CPUSS_DUMP=y CONFIG_QCOM_RUN_QUEUE_STATS=y CONFIG_QCOM_LLCC=y +CONFIG_QCOM_SM6150_LLCC=y +CONFIG_QCOM_SDMMAGPIE_LLCC=y CONFIG_QCOM_ATOLL_LLCC=y CONFIG_QCOM_LLCC_PERFMON=m CONFIG_QCOM_QMI_HELPERS=y @@ -665,7 +646,6 @@ CONFIG_QUOTA=y CONFIG_QUOTA_NETLINK_INTERFACE=y CONFIG_QFMT_V2=y CONFIG_FUSE_FS=y -CONFIG_OVERLAY_FS=y CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y CONFIG_TMPFS_POSIX_ACL=y diff --git a/arch/arm64/configs/vendor/atoll_defconfig b/arch/arm64/configs/vendor/atoll_defconfig index a1b038e0b444f79fd9287f4fcdc046a0e84ca5cf..f27b39732be8a3a86455e06bc4addf6fa4ee8cf9 100644 --- a/arch/arm64/configs/vendor/atoll_defconfig +++ b/arch/arm64/configs/vendor/atoll_defconfig @@ -72,7 +72,6 @@ CONFIG_BALANCE_ANON_FILE_RECLAIM=y CONFIG_SECCOMP=y # CONFIG_UNMAP_KERNEL_AT_EL0 is not set CONFIG_PRINT_VMEMLAYOUT=y -CONFIG_ARM64_SSBD=y CONFIG_ARMV8_DEPRECATED=y CONFIG_SWP_EMULATION=y CONFIG_CP15_BARRIER_EMULATION=y @@ -83,6 +82,7 @@ CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y CONFIG_KRYO_PMU_WORKAROUND=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_COMPAT=y +CONFIG_PM_AUTOSLEEP=y CONFIG_PM_WAKELOCKS=y CONFIG_PM_WAKELOCKS_LIMIT=0 # CONFIG_PM_WAKELOCKS_GC is not set @@ -110,7 +110,6 @@ CONFIG_IP_MULTIPLE_TABLES=y CONFIG_IP_ROUTE_VERBOSE=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y -CONFIG_NET_IPGRE_DEMUX=y CONFIG_SYN_COOKIES=y CONFIG_NET_IPVTI=y CONFIG_INET_AH=y @@ -230,7 +229,6 @@ CONFIG_NET_CLS_FW=y CONFIG_NET_CLS_U32=y CONFIG_CLS_U32_MARK=y CONFIG_NET_CLS_FLOW=y -CONFIG_NET_CLS_BPF=y CONFIG_NET_EMATCH=y CONFIG_NET_EMATCH_CMP=y CONFIG_NET_EMATCH_NBYTE=y @@ -260,7 +258,6 @@ CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y CONFIG_DMA_CMA=y CONFIG_ZRAM=y CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_LOOP_MIN_COUNT=16 CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=8192 CONFIG_HDCP_QSEECOM=y @@ -302,13 +299,11 @@ CONFIG_PPP_FILTER=y CONFIG_PPP_MPPE=y CONFIG_PPP_MULTILINK=y CONFIG_PPPOE=y -CONFIG_PPTP=y CONFIG_PPPOL2TP=y CONFIG_PPPOLAC=y CONFIG_PPPOPNS=y CONFIG_PPP_ASYNC=y CONFIG_PPP_SYNC_TTY=y -CONFIG_USB_RTL8152=y CONFIG_USB_USBNET=y CONFIG_WIL6210=m CONFIG_WCNSS_MEM_PRE_ALLOC=y @@ -348,7 +343,6 @@ CONFIG_INPUT_UINPUT=y # CONFIG_DEVMEM is not set CONFIG_SERIAL_MSM_GENI=y CONFIG_SERIAL_MSM_GENI_CONSOLE=y -CONFIG_SERIAL_MSM_WITH_HALF_SAMPLING=y CONFIG_SERIAL_DEV_BUS=y CONFIG_TTY_PRINTK=y CONFIG_HW_RANDOM=y @@ -373,6 +367,7 @@ CONFIG_SLIMBUS_MSM_NGD=y CONFIG_PTP_1588_CLOCK=y CONFIG_PINCTRL_SX150X=y CONFIG_PINCTRL_QCOM_SPMI_PMIC=y +CONFIG_PINCTRL_SDMMAGPIE=y CONFIG_PINCTRL_ATOLL=y CONFIG_PINCTRL_SLPI=y CONFIG_GPIO_SYSFS=y @@ -396,16 +391,15 @@ CONFIG_QTI_THERMAL_LIMITS_DCVS=y CONFIG_QTI_VIRTUAL_SENSOR=y CONFIG_QTI_AOP_REG_COOLING_DEVICE=y CONFIG_QTI_QMI_COOLING_DEVICE=y -CONFIG_QTI_QMI_SENSOR=y CONFIG_REGULATOR_COOLING_DEVICE=y CONFIG_QTI_BCL_PMIC5=y CONFIG_QTI_BCL_SOC_DRIVER=y CONFIG_QTI_ADC_TM=y +CONFIG_QTI_CX_IPEAK_COOLING_DEVICE=y CONFIG_MFD_I2C_PMIC=y CONFIG_MFD_SPMI_PMIC=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_PROXY_CONSUMER=y -CONFIG_REGULATOR_PM8008=y CONFIG_REGULATOR_QPNP_AMOLED=y CONFIG_REGULATOR_QPNP_LCDB=y CONFIG_REGULATOR_REFGEN=y @@ -574,12 +568,6 @@ CONFIG_MSM_VIDEOCC_SDMMAGPIE=y CONFIG_MSM_NPUCC_SDMMAGPIE=y CONFIG_MSM_GPUCC_SDMMAGPIE=y CONFIG_MSM_DEBUGCC_SDMMAGPIE=y -CONFIG_SM_GCC_ATOLL=y -CONFIG_SM_CAMCC_ATOLL=y -CONFIG_SM_VIDEOCC_ATOLL=y -CONFIG_SM_DISPCC_ATOLL=y -CONFIG_SM_NPUCC_ATOLL=y -CONFIG_SM_DEBUGCC_ATOLL=y CONFIG_HWSPINLOCK=y CONFIG_HWSPINLOCK_QCOM=y CONFIG_QCOM_APCS_IPC=y @@ -596,6 +584,8 @@ CONFIG_RPMSG_QCOM_GLINK_SPI=y CONFIG_QCOM_CPUSS_DUMP=y CONFIG_QCOM_RUN_QUEUE_STATS=y CONFIG_QCOM_LLCC=y +CONFIG_QCOM_SM6150_LLCC=y +CONFIG_QCOM_SDMMAGPIE_LLCC=y CONFIG_QCOM_ATOLL_LLCC=y CONFIG_QCOM_LLCC_PERFMON=m CONFIG_QCOM_QMI_HELPERS=y @@ -693,7 +683,6 @@ CONFIG_QUOTA=y CONFIG_QUOTA_NETLINK_INTERFACE=y CONFIG_QFMT_V2=y CONFIG_FUSE_FS=y -CONFIG_OVERLAY_FS=y CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y CONFIG_TMPFS_POSIX_ACL=y diff --git a/arch/arm64/configs/vendor/qcs405-perf_defconfig b/arch/arm64/configs/vendor/qcs405-perf_defconfig index d400e57f2f5e4ba3f96603044664788b7510bcfd..08d8d66b6353a7e0a21f708bf41c70bba5a51121 100644 --- a/arch/arm64/configs/vendor/qcs405-perf_defconfig +++ b/arch/arm64/configs/vendor/qcs405-perf_defconfig @@ -200,6 +200,8 @@ CONFIG_NET_EMATCH_TEXT=y CONFIG_NET_CLS_ACT=y CONFIG_QRTR=y CONFIG_QRTR_SMD=y +CONFIG_QRTR_USB=y +CONFIG_RMNET_USB=y CONFIG_BT=y # CONFIG_BT_BREDR is not set # CONFIG_BT_LE is not set @@ -214,6 +216,10 @@ CONFIG_RFKILL=y CONFIG_NTAG_NQ=y CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y CONFIG_DMA_CMA=y +CONFIG_MHI_BUS=y +CONFIG_MHI_QCOM=y +CONFIG_MHI_NETDEV=y +CONFIG_MHI_UCI=y CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_BLOCK=y @@ -267,9 +273,6 @@ CONFIG_ATH10K_DEBUG=y CONFIG_ATH10K_DEBUGFS=y CONFIG_WCNSS_MEM_PRE_ALLOC=y CONFIG_CLD_LL_CORE=y -CONFIG_CNSS=y -CONFIG_CNSS_SDIO=y -CONFIG_CLD_HL_SDIO_CORE=y CONFIG_INPUT_EVDEV=y CONFIG_INPUT_EVBUG=m CONFIG_INPUT_KEYRESET=y @@ -384,6 +387,7 @@ CONFIG_USB_SERIAL=y CONFIG_USB_EHSET_TEST_FIXTURE=y CONFIG_USB_LINK_LAYER_TEST=y CONFIG_USB_TYPEC_MUX_NXP5150A=y +CONFIG_USB_QCOM_DIAG_BRIDGE=y CONFIG_NOP_USB_XCEIV=y CONFIG_MSM_SNPS_FEMTO_PHY=y CONFIG_USB_MSM_SSPHY=y diff --git a/arch/arm64/configs/vendor/qcs405_defconfig b/arch/arm64/configs/vendor/qcs405_defconfig index 7a0a543823c40f322335b35a3a58543b8a9f2146..61e6f160b519e47550119ba37d4c1fed4630e9ca 100644 --- a/arch/arm64/configs/vendor/qcs405_defconfig +++ b/arch/arm64/configs/vendor/qcs405_defconfig @@ -206,6 +206,8 @@ CONFIG_NET_EMATCH_TEXT=y CONFIG_NET_CLS_ACT=y CONFIG_QRTR=y CONFIG_QRTR_SMD=y +CONFIG_QRTR_USB=y +CONFIG_RMNET_USB=y CONFIG_BT=y # CONFIG_BT_BREDR is not set # CONFIG_BT_LE is not set @@ -220,6 +222,11 @@ CONFIG_RFKILL=y CONFIG_NTAG_NQ=y CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y CONFIG_DMA_CMA=y +CONFIG_MHI_BUS=y +CONFIG_MHI_DEBUG=y +CONFIG_MHI_QCOM=y +CONFIG_MHI_NETDEV=y +CONFIG_MHI_UCI=y CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_BLOCK=y @@ -273,9 +280,6 @@ CONFIG_ATH10K_DEBUG=y CONFIG_ATH10K_DEBUGFS=y CONFIG_WCNSS_MEM_PRE_ALLOC=y CONFIG_CLD_LL_CORE=y -CONFIG_CNSS=y -CONFIG_CNSS_SDIO=y -CONFIG_CLD_HL_SDIO_CORE=y CONFIG_INPUT_EVDEV=y CONFIG_INPUT_EVBUG=m CONFIG_INPUT_KEYRESET=y @@ -394,6 +398,7 @@ CONFIG_USB_SERIAL=y CONFIG_USB_EHSET_TEST_FIXTURE=y CONFIG_USB_LINK_LAYER_TEST=y CONFIG_USB_TYPEC_MUX_NXP5150A=y +CONFIG_USB_QCOM_DIAG_BRIDGE=y CONFIG_NOP_USB_XCEIV=y CONFIG_MSM_SNPS_FEMTO_PHY=y CONFIG_USB_MSM_SSPHY=y diff --git a/arch/arm64/configs/vendor/qti-quin-gvm-perf_defconfig b/arch/arm64/configs/vendor/qti-quin-gvm-perf_defconfig index 43f066057da59ae4beb645a83099e58cd25eedd6..1c21491ae274e1dd220d21bdde3dbdb4b014cbcc 100644 --- a/arch/arm64/configs/vendor/qti-quin-gvm-perf_defconfig +++ b/arch/arm64/configs/vendor/qti-quin-gvm-perf_defconfig @@ -308,9 +308,7 @@ CONFIG_SPI=y CONFIG_SPI_QCOM_GENI=y CONFIG_SPI_SPIDEV=y CONFIG_SPMI=y -CONFIG_PTP_1588_CLOCK=y CONFIG_PINCTRL_SX150X=y -CONFIG_PINCTRL_QCOM_SPMI_PMIC=y CONFIG_PINCTRL_SM8150=y CONFIG_PINCTRL_SDMSHRIKE=y CONFIG_PINCTRL_SM6150=y @@ -324,13 +322,11 @@ CONFIG_THERMAL=y CONFIG_THERMAL_WRITABLE_TRIPS=y CONFIG_THERMAL_GOV_USER_SPACE=y CONFIG_THERMAL_GOV_LOW_LIMITS=y -CONFIG_MFD_SPMI_PMIC=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_PROXY_CONSUMER=y CONFIG_REGULATOR_REFGEN=y CONFIG_REGULATOR_STUB=y -CONFIG_VIRTIO_REGULATOR=y CONFIG_MEDIA_SUPPORT=y CONFIG_MEDIA_CAMERA_SUPPORT=y CONFIG_MEDIA_CONTROLLER=y diff --git a/arch/arm64/configs/vendor/qti-quin-gvm_defconfig b/arch/arm64/configs/vendor/qti-quin-gvm_defconfig index 42e89099a1034b63ee2f04fef7cccbf3fa19220c..0ab5f39e47ad3a045c6af2b6feb432cc842c20b9 100644 --- a/arch/arm64/configs/vendor/qti-quin-gvm_defconfig +++ b/arch/arm64/configs/vendor/qti-quin-gvm_defconfig @@ -320,9 +320,7 @@ CONFIG_SPI=y CONFIG_SPI_QCOM_GENI=y CONFIG_SPI_SPIDEV=y CONFIG_SPMI=y -CONFIG_PTP_1588_CLOCK=y CONFIG_PINCTRL_SX150X=y -CONFIG_PINCTRL_QCOM_SPMI_PMIC=y CONFIG_PINCTRL_SM8150=y CONFIG_PINCTRL_SDMSHRIKE=y CONFIG_PINCTRL_SM6150=y @@ -336,13 +334,11 @@ CONFIG_THERMAL=y CONFIG_THERMAL_WRITABLE_TRIPS=y CONFIG_THERMAL_GOV_USER_SPACE=y CONFIG_THERMAL_GOV_LOW_LIMITS=y -CONFIG_MFD_SPMI_PMIC=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_PROXY_CONSUMER=y CONFIG_REGULATOR_REFGEN=y CONFIG_REGULATOR_STUB=y -CONFIG_VIRTIO_REGULATOR=y CONFIG_MEDIA_SUPPORT=y CONFIG_MEDIA_CAMERA_SUPPORT=y CONFIG_MEDIA_CONTROLLER=y diff --git a/arch/arm64/configs/vendor/sa8155-perf_defconfig b/arch/arm64/configs/vendor/sa8155-perf_defconfig index ca9ff962ff294a5776c860793f074af6e89a21d5..dde0c1b816920537de1a5e05b6d388429b206af2 100644 --- a/arch/arm64/configs/vendor/sa8155-perf_defconfig +++ b/arch/arm64/configs/vendor/sa8155-perf_defconfig @@ -309,9 +309,6 @@ CONFIG_CNSS2_DEBUG=y CONFIG_CNSS2_QMI=y CONFIG_CNSS_ASYNC=y CONFIG_CNSS_GENL=y -CONFIG_NVM=y -CONFIG_NVM_RRPC=y -CONFIG_NVM_PBLK=y CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_GPIO=y # CONFIG_INPUT_MOUSE is not set diff --git a/arch/arm64/configs/vendor/sa8155_defconfig b/arch/arm64/configs/vendor/sa8155_defconfig index 940dbf4ca5929002a49cd70c9e7997fb7b7b65c1..98af752b29b7c95a3b6ff7c2a26f97dc4b6c0089 100644 --- a/arch/arm64/configs/vendor/sa8155_defconfig +++ b/arch/arm64/configs/vendor/sa8155_defconfig @@ -322,9 +322,6 @@ CONFIG_CNSS2_DEBUG=y CONFIG_CNSS2_QMI=y CONFIG_CNSS_ASYNC=y CONFIG_CNSS_GENL=y -CONFIG_NVM=y -CONFIG_NVM_RRPC=y -CONFIG_NVM_PBLK=y CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_GPIO=y # CONFIG_INPUT_MOUSE is not set diff --git a/arch/arm64/configs/vendor/sdmsteppe-auto-perf_defconfig b/arch/arm64/configs/vendor/sdmsteppe-auto-perf_defconfig index a449ce2f488074b85ca81e94ee43adc9f811387f..a395cb5dcaf8ec05734bf4bc3fe65e7af30b9050 100644 --- a/arch/arm64/configs/vendor/sdmsteppe-auto-perf_defconfig +++ b/arch/arm64/configs/vendor/sdmsteppe-auto-perf_defconfig @@ -704,3 +704,8 @@ CONFIG_CRYPTO_AES_ARM64_CE_CCM=y CONFIG_CRYPTO_AES_ARM64_CE_BLK=y CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y CONFIG_STACK_HASH_ORDER_SHIFT=12 +CONFIG_PSTORE=y +CONFIG_PSTORE_CONSOLE=y +CONFIG_PSTORE_RAM=y +CONFIG_PSTORE_DEVICE_INFO=y +CONFIG_PSTORE_PMSG=y diff --git a/arch/arm64/configs/vendor/sdmsteppe-auto_defconfig b/arch/arm64/configs/vendor/sdmsteppe-auto_defconfig index 1ddb89cc282fe1e70d8792d6d1e115c7f1d8a09a..95eb55e243d9320010fb49937bd874a3cd5aa27f 100644 --- a/arch/arm64/configs/vendor/sdmsteppe-auto_defconfig +++ b/arch/arm64/configs/vendor/sdmsteppe-auto_defconfig @@ -377,7 +377,6 @@ CONFIG_PINCTRL_SDMMAGPIE=y CONFIG_PINCTRL_SM6150=y CONFIG_PINCTRL_SLPI=y CONFIG_GPIO_SYSFS=y -CONFIG_GNSS_SIRF=y CONFIG_POWER_RESET_QCOM=y CONFIG_QCOM_DLOAD_MODE=y CONFIG_POWER_RESET_XGENE=y @@ -789,3 +788,8 @@ CONFIG_CRYPTO_AES_ARM64_CE_CCM=y CONFIG_CRYPTO_AES_ARM64_CE_BLK=y CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y CONFIG_XZ_DEC=y +CONFIG_PSTORE=y +CONFIG_PSTORE_CONSOLE=y +CONFIG_PSTORE_RAM=y +CONFIG_PSTORE_DEVICE_INFO=y +CONFIG_PSTORE_PMSG=y diff --git a/arch/arm64/configs/vendor/sdmsteppe-perf_defconfig b/arch/arm64/configs/vendor/sdmsteppe-perf_defconfig index 0dd156d0612a904d8c8899f098ba352cecee50d5..c560420f7c1ec0cdc849a696fad7fb7d71ee5b8f 100644 --- a/arch/arm64/configs/vendor/sdmsteppe-perf_defconfig +++ b/arch/arm64/configs/vendor/sdmsteppe-perf_defconfig @@ -252,7 +252,6 @@ CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y CONFIG_DMA_CMA=y CONFIG_ZRAM=y CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_LOOP_MIN_COUNT=16 CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=8192 CONFIG_HDCP_QSEECOM=y diff --git a/arch/arm64/configs/vendor/sdmsteppe_defconfig b/arch/arm64/configs/vendor/sdmsteppe_defconfig index 7887c8f5b8880cd6f88f98c666df1842f6ab2eeb..b83c506497a7b3468a0b2f2a4a8c8a61a0b75c08 100644 --- a/arch/arm64/configs/vendor/sdmsteppe_defconfig +++ b/arch/arm64/configs/vendor/sdmsteppe_defconfig @@ -261,7 +261,6 @@ CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y CONFIG_DMA_CMA=y CONFIG_ZRAM=y CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_LOOP_MIN_COUNT=16 CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=8192 CONFIG_HDCP_QSEECOM=y diff --git a/arch/arm64/configs/vendor/sm8150-perf_defconfig b/arch/arm64/configs/vendor/sm8150-perf_defconfig index 1105ae35f0dcdca7150dbb097a16647afe0a557f..09e0d213368f3116ad26cc7a2dbcb7220fcbc3ad 100644 --- a/arch/arm64/configs/vendor/sm8150-perf_defconfig +++ b/arch/arm64/configs/vendor/sm8150-perf_defconfig @@ -1,4 +1,4 @@ -CONFIG_HOTPLUG_SIZE_BITS=29 +# CONFIG_HOTPLUG_SIZE_BITS is not set CONFIG_LOCALVERSION="-perf" # CONFIG_LOCALVERSION_AUTO is not set # CONFIG_FHANDLE is not set @@ -64,10 +64,10 @@ CONFIG_SCHED_MC=y CONFIG_NR_CPUS=8 CONFIG_PREEMPT=y CONFIG_HZ_100=y -CONFIG_MEMORY_HOTPLUG=y -CONFIG_MEMORY_HOTPLUG_DEFAULT_ONLINE=y -CONFIG_MEMORY_HOTPLUG_MOVABLE_NODE=y -CONFIG_MEMORY_HOTREMOVE=y +# CONFIG_MEMORY_HOTPLUG is not set +# CONFIG_MEMORY_HOTPLUG_DEFAULT_ONLINE is not set +# CONFIG_MEMORY_HOTPLUG_MOVABLE_NODE is not set +# CONFIG_MEMORY_HOTREMOVE is not set CONFIG_CMA=y CONFIG_ZSMALLOC=y CONFIG_BALANCE_ANON_FILE_RECLAIM=y @@ -80,6 +80,7 @@ CONFIG_SETEND_EMULATION=y # CONFIG_ARM64_VHE is not set CONFIG_RANDOMIZE_BASE=y # CONFIG_EFI is not set +CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y CONFIG_BUILD_ARM64_UNCOMPRESSED_KERNEL=y CONFIG_KRYO_PMU_WORKAROUND=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set @@ -90,6 +91,7 @@ CONFIG_PM_WAKELOCKS_LIMIT=0 CONFIG_CPU_IDLE=y CONFIG_ARM_CPUIDLE=y CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y CONFIG_CPU_FREQ_TIMES=y CONFIG_CPU_FREQ_GOV_POWERSAVE=y CONFIG_CPU_FREQ_GOV_USERSPACE=y @@ -254,7 +256,12 @@ CONFIG_CFG80211_CERTIFICATION_ONUS=y CONFIG_CFG80211_REG_CELLULAR_HINTS=y CONFIG_CFG80211_INTERNAL_REGDB=y CONFIG_RFKILL=y -CONFIG_NFC_NQ=y +# CONFIG_NFC_NQ=y +# CONFIG_NFC_PN5XX=y +# CONFIG_NFC_PN80T=y +CONFIG_NXP_ESE_PN8XT=y +CONFIG_NXP_NFC_PN8XT=y +CONFIG_NXP_NFC_ESE_DEVICE=y CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y CONFIG_DMA_CMA=y @@ -319,11 +326,30 @@ CONFIG_CLD_LL_CORE=y CONFIG_CNSS_GENL=y CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_GPIO=y +CONFIG_TRI_STATE_KEY=y # CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_FINGERPRINT=y +CONFIG_FINGERPRINT_DETECT=y +CONFIG_FINGERPRINT_GOODIX=y CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ST=y +CONFIG_TOUCHPANEL_SAMSUNG=y +CONFIG_TOUCHPANEL_SAMSUNG_S6SY761=y +CONFIG_TOUCHPANEL_ONEPLUS=y +CONFIG_TOUCHPANEL_SYNAPTICS=y +CONFIG_TOUCHPANEL_SYNAPTICS_S3706=y +CONFIG_SENSOR_HALL_MXM1120=y +CONFIG_SENSOR_HALL_IST8801=y +CONFIG_HALL_TRI_STATE_KEY=y + +#CONFIG_TOUCHSCREEN_SYNAPTICS_S3320_I2C_RMI=y +#CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_CORE=y +#CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_RMI_DEV=y +#CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE=y +#CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_EXTRA_SYSFS=y +#CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_TEST_REPORTING=y + CONFIG_INPUT_MISC=y -CONFIG_INPUT_HBTP_INPUT=y +# CONFIG_INPUT_HBTP_INPUT is not set CONFIG_INPUT_QPNP_POWER_ON=y CONFIG_INPUT_QTI_HAPTICS=y CONFIG_INPUT_UINPUT=y @@ -332,6 +358,7 @@ CONFIG_INPUT_UINPUT=y # CONFIG_LEGACY_PTYS is not set # CONFIG_DEVMEM is not set CONFIG_SERIAL_MSM_GENI=y +CONFIG_SERIAL_MSM_GENI_CONSOLE=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_MSM_LEGACY=y # CONFIG_DEVPORT is not set @@ -363,6 +390,11 @@ CONFIG_QPNP_FG_GEN4=y CONFIG_SMB1355_SLAVE_CHARGER=y CONFIG_QPNP_SMB5=y CONFIG_QPNP_QNOVO5=y +CONFIG_FG_BQ27541=y +CONFIG_ONEPLUS_FASTCHG=y +CONFIG_JOYSTICK_XPAD=y +CONFIG_HID_SONY=y +CONFIG_SONY_FF=y CONFIG_SMB1390_CHARGE_PUMP_PSY=y CONFIG_THERMAL=y CONFIG_THERMAL_WRITABLE_TRIPS=y @@ -547,8 +579,8 @@ CONFIG_RPMSG_CHAR=y CONFIG_RPMSG_QCOM_GLINK_SMEM=y CONFIG_RPMSG_QCOM_GLINK_SPSS=y CONFIG_RPMSG_QCOM_GLINK_SPI=y -CONFIG_QCOM_MEM_OFFLINE=y -CONFIG_OVERRIDE_MEMORY_LIMIT=y +# CONFIG_QCOM_MEM_OFFLINE is not set +# CONFIG_OVERRIDE_MEMORY_LIMIT is not set CONFIG_QCOM_CPUSS_DUMP=y CONFIG_QCOM_RUN_QUEUE_STATS=y CONFIG_QCOM_LLCC=y @@ -653,6 +685,8 @@ CONFIG_FUSE_FS=y CONFIG_OVERLAY_FS=y CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y +CONFIG_EXFAT_FS=y +CONFIG_NTFS_FS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_ECRYPT_FS=y CONFIG_ECRYPT_FS_MESSAGING=y @@ -662,11 +696,15 @@ CONFIG_NLS_ISO8859_1=y CONFIG_PRINTK_TIME=y CONFIG_DEBUG_INFO=y CONFIG_PAGE_OWNER=y +CONFIG_PAGE_OWNER_ENABLE_DEFAULT=y CONFIG_MAGIC_SYSRQ=y CONFIG_PANIC_TIMEOUT=-1 CONFIG_SCHEDSTATS=y # CONFIG_DEBUG_PREEMPT is not set CONFIG_IPC_LOGGING=y +# CONFIG_QCOM_RTB is not set +# CONFIG_QCOM_RTB_SEPARATE_CPUS is not set +CONFIG_BLK_DEV_IO_TRACE=y CONFIG_DEBUG_ALIGN_RODATA=y CONFIG_CORESIGHT=y CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y @@ -706,3 +744,38 @@ CONFIG_CRYPTO_AES_ARM64_CE_CCM=y CONFIG_CRYPTO_AES_ARM64_CE_BLK=y CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y CONFIG_STACK_HASH_ORDER_SHIFT=12 +CONFIG_PSTORE=y +CONFIG_PSTORE_CONSOLE=y +CONFIG_PSTORE_RAM=y +CONFIG_PSTORE_DEVICE_INFO=y +CONFIG_PSTORE_PMSG=y +CONFIG_PROJECT_INFO=y +CONFIG_BOOTLOADER_LOG=y +CONFIG_OEM_BOOT_MODE=y +CONFIG_AW8697_HAPTIC=y +CONFIG_DIGITAL_HALL_M1120=y +CONFIG_STEP_MOTOR=y +CONFIG_NET_CLS_CGROUP=y +CONFIG_OPCHAIN=y +CONFIG_RF_CABLE_DETECT=y +CONFIG_ADJ_CHAIN=y +CONFIG_DEFRAG=y +CONFIG_FSC=y +CONFIG_SMART_BOOST=y +CONFIG_MEMPLUS=y +CONFIG_OVERLAY_FS=y +CONFIG_HOUSTON=y +CONFIG_CONTROL_CENTER=y +CONFIG_AIGOV=y +CONFIG_ONEPLUS_MEM_MONITOR=y +CONFIG_ONEPLUS_FG_OPT=y +CONFIG_ONEPLUS_HEALTHINFO=y +CONFIG_SLAB_STAT_DEBUG=y +CONFIG_SLABINFO=y +# dylanchang, 2019/4/30, enable noop io scheduler +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +# dylanchang,2019/4/1, add for kernel log reserve +CONFIG_WB_KERNEL_LOG=y +CONFIG_SLA=y +CONFIG_SLA_ALGO=y diff --git a/arch/arm64/configs/vendor/sm8150_defconfig b/arch/arm64/configs/vendor/sm8150_defconfig index 0aa80bf5bdff1602245ec91cb3aba2d0082f9b66..13f25cc20fd4a7ff2a26c5a04c3a772a68da01d1 100644 --- a/arch/arm64/configs/vendor/sm8150_defconfig +++ b/arch/arm64/configs/vendor/sm8150_defconfig @@ -1,4 +1,4 @@ -CONFIG_HOTPLUG_SIZE_BITS=29 +# CONFIG_HOTPLUG_SIZE_BITS is not set # CONFIG_LOCALVERSION_AUTO is not set # CONFIG_FHANDLE is not set CONFIG_AUDIT=y @@ -68,10 +68,10 @@ CONFIG_SCHED_MC=y CONFIG_NR_CPUS=8 CONFIG_PREEMPT=y CONFIG_HZ_100=y -CONFIG_MEMORY_HOTPLUG=y -CONFIG_MEMORY_HOTPLUG_DEFAULT_ONLINE=y -CONFIG_MEMORY_HOTPLUG_MOVABLE_NODE=y -CONFIG_MEMORY_HOTREMOVE=y +# CONFIG_MEMORY_HOTPLUG is not set +# CONFIG_MEMORY_HOTPLUG_DEFAULT_ONLINE is not set +# CONFIG_MEMORY_HOTPLUG_MOVABLE_NODE is not set +# CONFIG_MEMORY_HOTREMOVE is not set CONFIG_CLEANCACHE=y CONFIG_CMA=y CONFIG_CMA_DEBUGFS=y @@ -86,6 +86,7 @@ CONFIG_CP15_BARRIER_EMULATION=y CONFIG_SETEND_EMULATION=y # CONFIG_ARM64_VHE is not set CONFIG_RANDOMIZE_BASE=y +CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y CONFIG_BUILD_ARM64_UNCOMPRESSED_KERNEL=y CONFIG_KRYO_PMU_WORKAROUND=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set @@ -97,6 +98,7 @@ CONFIG_PM_DEBUG=y CONFIG_CPU_IDLE=y CONFIG_ARM_CPUIDLE=y CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y CONFIG_CPU_FREQ_TIMES=y CONFIG_CPU_FREQ_GOV_POWERSAVE=y CONFIG_CPU_FREQ_GOV_USERSPACE=y @@ -264,7 +266,12 @@ CONFIG_CFG80211_REG_CELLULAR_HINTS=y CONFIG_CFG80211_INTERNAL_REGDB=y # CONFIG_CFG80211_CRDA_SUPPORT is not set CONFIG_RFKILL=y -CONFIG_NFC_NQ=y +# CONFIG_NFC_NQ=y +# CONFIG_NFC_PN5XX=y +# CONFIG_NFC_PN80T=y +CONFIG_NXP_ESE_PN8XT=y +CONFIG_NXP_NFC_PN8XT=y +CONFIG_NXP_NFC_ESE_DEVICE=y CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y CONFIG_DMA_CMA=y @@ -330,12 +337,31 @@ CONFIG_CLD_LL_CORE=y CONFIG_CNSS_GENL=y CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_GPIO=y +CONFIG_TRI_STATE_KEY=y # CONFIG_INPUT_MOUSE is not set CONFIG_INPUT_JOYSTICK=y +CONFIG_INPUT_FINGERPRINT=y +CONFIG_FINGERPRINT_DETECT=y +CONFIG_FINGERPRINT_GOODIX=y CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ST=y +CONFIG_TOUCHPANEL_SAMSUNG=y +CONFIG_TOUCHPANEL_SAMSUNG_S6SY761=y +CONFIG_TOUCHPANEL_ONEPLUS=y +CONFIG_TOUCHPANEL_SYNAPTICS=y +CONFIG_TOUCHPANEL_SYNAPTICS_S3706=y +CONFIG_SENSOR_HALL_MXM1120=y +CONFIG_SENSOR_HALL_IST8801=y +CONFIG_HALL_TRI_STATE_KEY=y + +#CONFIG_TOUCHSCREEN_SYNAPTICS_S3320_I2C_RMI=y +#CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_CORE=y +#CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_RMI_DEV=y +#CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE=y +#CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_EXTRA_SYSFS=y +#CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_TEST_REPORTING=y + CONFIG_INPUT_MISC=y -CONFIG_INPUT_HBTP_INPUT=y +# CONFIG_INPUT_HBTP_INPUT is not set CONFIG_INPUT_QPNP_POWER_ON=y CONFIG_INPUT_QTI_HAPTICS=y CONFIG_INPUT_UINPUT=y @@ -378,6 +404,11 @@ CONFIG_QPNP_FG_GEN4=y CONFIG_SMB1355_SLAVE_CHARGER=y CONFIG_QPNP_SMB5=y CONFIG_QPNP_QNOVO5=y +CONFIG_FG_BQ27541=y +CONFIG_ONEPLUS_FASTCHG=y +CONFIG_JOYSTICK_XPAD=y +CONFIG_HID_SONY=y +CONFIG_SONY_FF=y CONFIG_SMB1390_CHARGE_PUMP_PSY=y CONFIG_THERMAL=y CONFIG_THERMAL_WRITABLE_TRIPS=y @@ -571,8 +602,8 @@ CONFIG_RPMSG_CHAR=y CONFIG_RPMSG_QCOM_GLINK_SMEM=y CONFIG_RPMSG_QCOM_GLINK_SPSS=y CONFIG_RPMSG_QCOM_GLINK_SPI=y -CONFIG_QCOM_MEM_OFFLINE=y -CONFIG_OVERRIDE_MEMORY_LIMIT=y +# CONFIG_QCOM_MEM_OFFLINE is not set +# CONFIG_OVERRIDE_MEMORY_LIMIT is not set CONFIG_QCOM_CPUSS_DUMP=y CONFIG_QCOM_RUN_QUEUE_STATS=y CONFIG_QCOM_LLCC=y @@ -683,6 +714,8 @@ CONFIG_FUSE_FS=y CONFIG_OVERLAY_FS=y CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y +CONFIG_EXFAT_FS=y +CONFIG_NTFS_FS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_EFIVAR_FS=y CONFIG_ECRYPT_FS=y @@ -712,7 +745,7 @@ CONFIG_DEBUG_OBJECTS_WORK=y CONFIG_DEBUG_OBJECTS_PERCPU_COUNTER=y CONFIG_SLUB_DEBUG_ON=y CONFIG_DEBUG_KMEMLEAK=y -CONFIG_DEBUG_KMEMLEAK_EARLY_LOG_SIZE=4000 +CONFIG_DEBUG_KMEMLEAK_EARLY_LOG_SIZE=8192 CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y CONFIG_DEBUG_STACK_USAGE=y CONFIG_DEBUG_MEMORY_INIT=y @@ -792,3 +825,40 @@ CONFIG_CRYPTO_AES_ARM64_CE_CCM=y CONFIG_CRYPTO_AES_ARM64_CE_BLK=y CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y CONFIG_XZ_DEC=y +# yangfb,2018/1/26, add for aging test get log and limmit current +CONFIG_OP_DEBUG_CHG=y +CONFIG_PSTORE=y +CONFIG_PSTORE_CONSOLE=y +CONFIG_PSTORE_RAM=y +CONFIG_PSTORE_DEVICE_INFO=y +CONFIG_PSTORE_PMSG=y +CONFIG_PROJECT_INFO=y +CONFIG_BOOTLOADER_LOG=y +CONFIG_OEM_BOOT_MODE=y +CONFIG_AW8697_HAPTIC=y +CONFIG_DIGITAL_HALL_M1120=y +CONFIG_STEP_MOTOR=y +CONFIG_NET_CLS_CGROUP=y +CONFIG_OPCHAIN=y +CONFIG_RF_CABLE_DETECT=y +CONFIG_ADJ_CHAIN=y +CONFIG_DEFRAG=y +CONFIG_FSC=y +CONFIG_SMART_BOOST=y +CONFIG_MEMPLUS=y +CONFIG_OVERLAY_FS=y +CONFIG_HOUSTON=y +CONFIG_CONTROL_CENTER=y +CONFIG_AIGOV=y +CONFIG_ONEPLUS_MEM_MONITOR=y +CONFIG_ONEPLUS_FG_OPT=y +CONFIG_ONEPLUS_HEALTHINFO=y +CONFIG_SLAB_STAT_DEBUG=y +CONFIG_SLABINFO=y +# dylanchang, 2019/4/30, enable noop io scheduler +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +# dylanchang,2019/4/1, add for kernel log reserve +CONFIG_WB_KERNEL_LOG=y +CONFIG_SLA=y +CONFIG_SLA_ALGO=y diff --git a/arch/arm64/configs/vendor/trinket-perf_defconfig b/arch/arm64/configs/vendor/trinket-perf_defconfig index 797f8f1fba9a20ab6f4050ead1b86645b271c8bd..ada21ac70ca0fc1bf5c99c1d1028a60dcff43d93 100644 --- a/arch/arm64/configs/vendor/trinket-perf_defconfig +++ b/arch/arm64/configs/vendor/trinket-perf_defconfig @@ -79,6 +79,7 @@ CONFIG_ARM64_SW_TTBR0_PAN=y # CONFIG_ARM64_PAN is not set # CONFIG_ARM64_VHE is not set CONFIG_RANDOMIZE_BASE=y +CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_COMPAT=y CONFIG_PM_WAKELOCKS=y @@ -257,7 +258,6 @@ CONFIG_DMA_CMA=y CONFIG_ZRAM=y CONFIG_ZRAM_DEDUP=y CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_LOOP_MIN_COUNT=16 CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=8192 CONFIG_HDCP_QSEECOM=y diff --git a/arch/arm64/configs/vendor/trinket_defconfig b/arch/arm64/configs/vendor/trinket_defconfig index 523a2dd3b4bef109b710895a6773a95c4d150a78..ed1eac7f348dafe73b07973c4e20195130e32f9c 100644 --- a/arch/arm64/configs/vendor/trinket_defconfig +++ b/arch/arm64/configs/vendor/trinket_defconfig @@ -85,6 +85,7 @@ CONFIG_ARM64_SW_TTBR0_PAN=y # CONFIG_ARM64_PAN is not set # CONFIG_ARM64_VHE is not set CONFIG_RANDOMIZE_BASE=y +CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_COMPAT=y CONFIG_PM_WAKELOCKS=y @@ -266,7 +267,6 @@ CONFIG_DMA_CMA=y CONFIG_ZRAM=y CONFIG_ZRAM_DEDUP=y CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_LOOP_MIN_COUNT=16 CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=8192 CONFIG_HDCP_QSEECOM=y @@ -570,7 +570,6 @@ CONFIG_MSM_QMP=y CONFIG_IOMMU_IO_PGTABLE_FAST=y CONFIG_ARM_SMMU=y CONFIG_IOMMU_TLBSYNC_DEBUG=y -CONFIG_ARM_SMMU_TESTBUS_DUMP=y CONFIG_QCOM_LAZY_MAPPING=y CONFIG_IOMMU_DEBUG=y CONFIG_IOMMU_DEBUG_TRACKING=y diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h index 802968818aa3a7a1a8399761d3886bd54d5fda4c..ab1149efda437496dc2f62ca8fe9fd73e3f00407 100644 --- a/arch/arm64/include/asm/cpucaps.h +++ b/arch/arm64/include/asm/cpucaps.h @@ -46,9 +46,7 @@ #define ARM64_HW_DBM 26 #define ARM64_SSBD 27 #define ARM64_MISMATCHED_CACHE_TYPE 28 -#define ARM64_SSBS 29 -#define ARM64_WORKAROUND_1188873 30 -#define ARM64_NCAPS 31 +#define ARM64_NCAPS 29 #endif /* __ASM_CPUCAPS_H */ diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h index e174fe5e208a60b5b4931e96b929a1391c8d7f6e..e2675f9d3da6408aef09f557b521d4dcf7c71bdb 100644 --- a/arch/arm64/include/asm/io.h +++ b/arch/arm64/include/asm/io.h @@ -107,11 +107,10 @@ static inline u64 __raw_readq_no_log(const volatile void __iomem *addr) #define __raw_write_logged(v, a, _t) ({ \ int _ret; \ - volatile void __iomem *_a = (a); \ - void *_addr = (void __force *)(_a); \ + void *_addr = (void *)(a); \ _ret = uncached_logk(LOGK_WRITEL, _addr); \ ETB_WAYPOINT; \ - __raw_write##_t##_no_log((v), _a); \ + __raw_write##_t##_no_log((v), _addr); \ if (_ret) \ LOG_BARRIER; \ }) @@ -123,12 +122,11 @@ static inline u64 __raw_readq_no_log(const volatile void __iomem *addr) #define __raw_read_logged(a, _l, _t) ({ \ _t __a; \ - const volatile void __iomem *_a = (a); \ - void *_addr = (void __force *)(_a); \ + void *_addr = (void *)(a); \ int _ret; \ _ret = uncached_logk(LOGK_READL, _addr); \ ETB_WAYPOINT; \ - __a = __raw_read##_l##_no_log(_a); \ + __a = __raw_read##_l##_no_log(_addr); \ if (_ret) \ LOG_BARRIER; \ __a; \ diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h index 87653c86b2e6d141440cc211a9066a8f9651cf84..e02c4bd7c68ff8e977e88916c71f6bfce5bdb89e 100644 --- a/arch/arm64/include/asm/processor.h +++ b/arch/arm64/include/asm/processor.h @@ -147,10 +147,6 @@ static inline void start_thread(struct pt_regs *regs, unsigned long pc, { start_thread_common(regs, pc); regs->pstate = PSR_MODE_EL0t; - - if (arm64_get_ssbd_state() != ARM64_SSBD_FORCE_ENABLE) - regs->pstate |= PSR_SSBS_BIT; - regs->sp = sp; } @@ -167,9 +163,6 @@ static inline void compat_start_thread(struct pt_regs *regs, unsigned long pc, regs->pstate |= COMPAT_PSR_E_BIT; #endif - if (arm64_get_ssbd_state() != ARM64_SSBD_FORCE_ENABLE) - regs->pstate |= COMPAT_PSR_SSBS_BIT; - regs->compat_sp = sp; } #endif diff --git a/arch/arm64/include/asm/ptrace.h b/arch/arm64/include/asm/ptrace.h index 17c7e949e42ce64af7d8ccf7207473a25388a8de..9faaba0064a292d7d6328168798705a6d67930b2 100644 --- a/arch/arm64/include/asm/ptrace.h +++ b/arch/arm64/include/asm/ptrace.h @@ -50,7 +50,6 @@ #define COMPAT_PSR_I_BIT 0x00000080 #define COMPAT_PSR_A_BIT 0x00000100 #define COMPAT_PSR_E_BIT 0x00000200 -#define COMPAT_PSR_SSBS_BIT 0x00800000 #define COMPAT_PSR_J_BIT 0x01000000 #define COMPAT_PSR_Q_BIT 0x08000000 #define COMPAT_PSR_V_BIT 0x10000000 diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 82e4c7eea8cf46fa5d64904803c4a31d94745598..642333e9ba634d5125bfb1e6b26492c5c095ace0 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -83,26 +83,13 @@ #endif /* CONFIG_BROKEN_GAS_INST */ -/* - * Instructions for modifying PSTATE fields. - * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints, - * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions - * for accessing PSTATE fields have the following encoding: - * Op0 = 0, CRn = 4 - * Op1, Op2 encodes the PSTATE field modified and defines the constraints. - * CRm = Imm4 for the instruction. - * Rt = 0x1f - */ -#define pstate_field(op1, op2) ((op1) << Op1_shift | (op2) << Op2_shift) -#define PSTATE_Imm_shift CRm_shift - -#define PSTATE_PAN pstate_field(0, 4) -#define PSTATE_UAO pstate_field(0, 3) -#define PSTATE_SSBS pstate_field(3, 1) +#define REG_PSTATE_PAN_IMM sys_reg(0, 0, 4, 0, 4) +#define REG_PSTATE_UAO_IMM sys_reg(0, 0, 4, 0, 3) -#define SET_PSTATE_PAN(x) __emit_inst(0xd500401f | PSTATE_PAN | ((!!x) << PSTATE_Imm_shift)) -#define SET_PSTATE_UAO(x) __emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift)) -#define SET_PSTATE_SSBS(x) __emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift)) +#define SET_PSTATE_PAN(x) __emit_inst(0xd5000000 | REG_PSTATE_PAN_IMM | \ + (!!x)<<8 | 0x1f) +#define SET_PSTATE_UAO(x) __emit_inst(0xd5000000 | REG_PSTATE_UAO_IMM | \ + (!!x)<<8 | 0x1f) #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2) #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2) @@ -314,7 +301,6 @@ #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7) /* Common SCTLR_ELx flags. */ -#define SCTLR_ELx_DSSBS (1UL << 44) #define SCTLR_ELx_EE (1 << 25) #define SCTLR_ELx_I (1 << 12) #define SCTLR_ELx_SA (1 << 3) @@ -375,13 +361,6 @@ #define ID_AA64PFR0_EL0_64BIT_ONLY 0x1 #define ID_AA64PFR0_EL0_32BIT_64BIT 0x2 -/* id_aa64pfr1 */ -#define ID_AA64PFR1_SSBS_SHIFT 4 - -#define ID_AA64PFR1_SSBS_PSTATE_NI 0 -#define ID_AA64PFR1_SSBS_PSTATE_ONLY 1 -#define ID_AA64PFR1_SSBS_PSTATE_INSNS 2 - /* id_aa64mmfr0 */ #define ID_AA64MMFR0_TGRAN4_SHIFT 28 #define ID_AA64MMFR0_TGRAN64_SHIFT 24 diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h index eed4600efdad3a9c2dcd5e648ebce7b5c9b32230..f243c57d1670a7e2d1e1144bffb6ab24d26a5561 100644 --- a/arch/arm64/include/uapi/asm/hwcap.h +++ b/arch/arm64/include/uapi/asm/hwcap.h @@ -42,6 +42,5 @@ #define HWCAP_SM4 (1 << 19) #define HWCAP_ASIMDDP (1 << 20) #define HWCAP_SHA512 (1 << 21) -#define HWCAP_SSBS (1 << 22) #endif /* _UAPI__ASM_HWCAP_H */ diff --git a/arch/arm64/include/uapi/asm/ptrace.h b/arch/arm64/include/uapi/asm/ptrace.h index eea58f8ec35516535a14a27c63b67be1616cd180..67d4c33974e886d0a4798e341b2a0c5293a4a4b6 100644 --- a/arch/arm64/include/uapi/asm/ptrace.h +++ b/arch/arm64/include/uapi/asm/ptrace.h @@ -45,7 +45,6 @@ #define PSR_I_BIT 0x00000080 #define PSR_A_BIT 0x00000100 #define PSR_D_BIT 0x00000200 -#define PSR_SSBS_BIT 0x00001000 #define PSR_PAN_BIT 0x00400000 #define PSR_UAO_BIT 0x00800000 #define PSR_Q_BIT 0x08000000 diff --git a/arch/arm64/include/uapi/asm/setup.h b/arch/arm64/include/uapi/asm/setup.h index 5d703888f35110d2a7a15ec1836bffcffae3c8bb..9f583cb9e76ecf4ce937fc93f41d0d4dcff8927a 100644 --- a/arch/arm64/include/uapi/asm/setup.h +++ b/arch/arm64/include/uapi/asm/setup.h @@ -22,6 +22,6 @@ #include -#define COMMAND_LINE_SIZE 2048 +#define COMMAND_LINE_SIZE 3072 #endif diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 99ac724f2153d18b2e1c25c03a421eed9b6d376c..2c27bf15cd2ebea7d6fb94ef042e79195af274dc 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -271,14 +271,6 @@ early_param("ssbd", ssbd_cfg); void arm64_set_ssbd_mitigation(bool state) { - if (this_cpu_has_cap(ARM64_SSBS)) { - if (state) - asm volatile(SET_PSTATE_SSBS(0)); - else - asm volatile(SET_PSTATE_SSBS(1)); - return; - } - switch (psci_ops.conduit) { case PSCI_CONDUIT_HVC: arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_2, state, NULL); @@ -303,11 +295,6 @@ static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry, WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); - if (this_cpu_has_cap(ARM64_SSBS)) { - required = false; - goto out_printmsg; - } - if (psci_ops.smccc_version == SMCCC_VERSION_1_0) { ssbd_state = ARM64_SSBD_UNKNOWN; return false; @@ -356,6 +343,7 @@ static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry, switch (ssbd_state) { case ARM64_SSBD_FORCE_DISABLE: + pr_info_once("%s disabled from command-line\n", entry->desc); arm64_set_ssbd_mitigation(false); required = false; break; @@ -368,6 +356,7 @@ static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry, break; case ARM64_SSBD_FORCE_ENABLE: + pr_info_once("%s forced from command-line\n", entry->desc); arm64_set_ssbd_mitigation(true); required = true; break; @@ -377,17 +366,6 @@ static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry, break; } -out_printmsg: - switch (ssbd_state) { - case ARM64_SSBD_FORCE_DISABLE: - pr_info_once("%s disabled from command-line\n", entry->desc); - break; - - case ARM64_SSBD_FORCE_ENABLE: - pr_info_once("%s forced from command-line\n", entry->desc); - break; - } - return required; } #endif /* CONFIG_ARM64_SSBD */ @@ -554,12 +532,6 @@ const struct arm64_cpu_capabilities arm64_errata[] = { MIDR_CPU_VAR_REV(0, 0), MIDR_CPU_VAR_REV(3, 0)), }, - { - .capability = ARM64_WORKAROUND_REPEAT_TLBI, - MIDR_RANGE(MIDR_KRYO4G, - MIDR_CPU_VAR_REV(12, 14), - MIDR_CPU_VAR_REV(13, 14)), - }, #endif #ifdef CONFIG_ARM64_ERRATUM_858921 { @@ -644,25 +616,6 @@ const struct arm64_cpu_capabilities arm64_errata[] = { .capability = ARM64_SSBD, .matches = has_ssbd_mitigation, }, -#endif -#ifdef CONFIG_ARM64_ERRATUM_1188873 - { - .desc = "ARM erratum 1188873", - .capability = ARM64_WORKAROUND_1188873, - /* Cortex-A76 r0p0 to r2p0 */ - MIDR_RANGE(MIDR_CORTEX_A76, - MIDR_CPU_VAR_REV(0, 0), - MIDR_CPU_VAR_REV(2, 0)), - - }, - { - .desc = "ARM erratum 1188873", - .capability = ARM64_WORKAROUND_1188873, - /* Kryo-4G r15p14 */ - MIDR_RANGE(MIDR_KRYO4G, - MIDR_CPU_VAR_REV(15, 14), - MIDR_CPU_VAR_REV(15, 15)), - }, #endif { } diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index fa4924bad29031ea9202ac5d496855e8f24675e0..152fda8b9cbc52ddd733462f76568386e873fcb0 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -142,11 +142,6 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { ARM64_FTR_END, }; -static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI), - ARM64_FTR_END, -}; - static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI), S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI), @@ -346,8 +341,7 @@ static const struct __ftr_reg_entry { /* Op1 = 0, CRn = 0, CRm = 4 */ ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0), - ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1), - ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_raz), + ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_raz), /* Op1 = 0, CRn = 0, CRm = 5 */ ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), @@ -615,6 +609,7 @@ void update_cpu_features(int cpu, /* * EL3 is not our concern. + * ID_AA64PFR1 is currently RES0. */ taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); @@ -983,50 +978,6 @@ static int cpu_copy_el2regs(void *__unused) return 0; } -#ifdef CONFIG_ARM64_SSBD -static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr) -{ - if (user_mode(regs)) - return 1; - - if (instr & BIT(PSTATE_Imm_shift)) - regs->pstate |= PSR_SSBS_BIT; - else - regs->pstate &= ~PSR_SSBS_BIT; - - regs->pc += 4; - return 0; -} - -static struct undef_hook ssbs_emulation_hook = { - .instr_mask = ~(1U << PSTATE_Imm_shift), - .instr_val = 0xd500401f | PSTATE_SSBS, - .fn = ssbs_emulation_handler, -}; - -static int cpu_enable_ssbs(void *__unsused) -{ - static bool undef_hook_registered = false; - static DEFINE_SPINLOCK(hook_lock); - - spin_lock(&hook_lock); - if (!undef_hook_registered) { - register_undef_hook(&ssbs_emulation_hook); - undef_hook_registered = true; - } - spin_unlock(&hook_lock); - - if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) { - write_sysreg((read_sysreg(sctlr_el1) | SCTLR_ELx_DSSBS), - sctlr_el1); - arm64_set_ssbd_mitigation(false); - } else { - arm64_set_ssbd_mitigation(true); - } - return 0; -} -#endif /* CONFIG_ARM64_SSBD */ - static const struct arm64_cpu_capabilities arm64_features[] = { { .desc = "GIC system register CPU interface", @@ -1159,18 +1110,6 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .matches = has_hw_dbm, .enable = cpu_enable_hw_dbm, }, -#endif -#ifdef CONFIG_ARM64_SSBD - { - .desc = "Speculative Store Bypassing Safe (SSBS)", - .capability = ARM64_SSBS, - .matches = has_cpuid_feature, - .sys_reg = SYS_ID_AA64PFR1_EL1, - .field_pos = ID_AA64PFR1_SSBS_SHIFT, - .sign = FTR_UNSIGNED, - .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY, - .enable = cpu_enable_ssbs, - }, #endif {}, }; @@ -1209,7 +1148,6 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_JSCVT), HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA), HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_LRCPC), - HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, HWCAP_SSBS), {}, }; diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 1e3fbfb2b977f41aa6724e5142d665a314c4d8d5..5bca95fcdfe9cb5f2e2be3257393e052bbff5c1f 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -81,7 +81,6 @@ static const char *const hwcap_str[] = { "sm4", "asimddp", "sha512", - "ssbs", NULL }; diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index de16794fd64cef946c680a3c5792c7c32124c38e..7e50aec45858ddf17edfe3d1c4d45b67d1f82f1e 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -602,7 +602,7 @@ el1_undef: enable_dbg mov x0, sp bl do_undefinstr - kernel_exit 1 + ASM_BUG() el1_dbg: /* * Debug exception handling diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index e0a80e230c5ee887e760e6fe3c23f934c4743ab5..66eb8e23bc67b92bb9a2299bbcc85d3c91e9d5a4 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -1001,7 +1001,7 @@ static void armv8pmu_idle_update(struct arm_pmu *cpu_pmu) struct perf_event *event; int idx; - if (!cpu_pmu) + if (!cpu_pmu || !(cpu_pmu->hw_events)) return; if (__this_cpu_read(is_hotplugging)) diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index 6f3258a9d0ebe319a718ac2e5e89c9fb1f4539f5..e31f59db93976478a96ca11c5707171f99afe799 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -365,10 +365,6 @@ int copy_thread(unsigned long clone_flags, unsigned long stack_start, if (IS_ENABLED(CONFIG_ARM64_UAO) && cpus_have_const_cap(ARM64_HAS_UAO)) childregs->pstate |= PSR_UAO_BIT; - - if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) - childregs->pstate |= PSR_SSBS_BIT; - p->thread.cpu_context.x19 = stack_start; p->thread.cpu_context.x20 = stk_sz; } diff --git a/arch/arm64/kernel/ssbd.c b/arch/arm64/kernel/ssbd.c index 477ede8809c8e2d86019d02a945a43378264db46..0560738c1d5ccad415d1f50d2ffec56ba7e9ff08 100644 --- a/arch/arm64/kernel/ssbd.c +++ b/arch/arm64/kernel/ssbd.c @@ -3,31 +3,13 @@ * Copyright (C) 2018 ARM Ltd, All Rights Reserved. */ -#include #include #include #include -#include #include #include -static void ssbd_ssbs_enable(struct task_struct *task) -{ - u64 val = is_compat_thread(task_thread_info(task)) ? - COMPAT_PSR_SSBS_BIT : PSR_SSBS_BIT; - - task_pt_regs(task)->pstate |= val; -} - -static void ssbd_ssbs_disable(struct task_struct *task) -{ - u64 val = is_compat_thread(task_thread_info(task)) ? - COMPAT_PSR_SSBS_BIT : PSR_SSBS_BIT; - - task_pt_regs(task)->pstate &= ~val; -} - /* * prctl interface for SSBD */ @@ -63,14 +45,12 @@ static int ssbd_prctl_set(struct task_struct *task, unsigned long ctrl) return -EPERM; task_clear_spec_ssb_disable(task); clear_tsk_thread_flag(task, TIF_SSBD); - ssbd_ssbs_enable(task); break; case PR_SPEC_DISABLE: if (state == ARM64_SSBD_FORCE_DISABLE) return -EPERM; task_set_spec_ssb_disable(task); set_tsk_thread_flag(task, TIF_SSBD); - ssbd_ssbs_disable(task); break; case PR_SPEC_FORCE_DISABLE: if (state == ARM64_SSBD_FORCE_DISABLE) @@ -78,7 +58,6 @@ static int ssbd_prctl_set(struct task_struct *task, unsigned long ctrl) task_set_spec_ssb_disable(task); task_set_spec_ssb_force_disable(task); set_tsk_thread_flag(task, TIF_SSBD); - ssbd_ssbs_disable(task); break; default: return -ERANGE; diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c index d1a891023b10239657b8c06cdcffa1d3b6e47576..fedd5eb1463e552fca3eb6461adef0588b2798f0 100644 --- a/arch/arm64/kernel/traps.c +++ b/arch/arm64/kernel/traps.c @@ -51,6 +51,9 @@ #include #include +/* Save pt_regs ptr to get panic info for display in xbl mode */ +void *panic_info = NULL; + static const char *handler[]= { "Synchronous Abort", "IRQ", @@ -194,6 +197,10 @@ static int __die(const char *str, int err, struct pt_regs *regs) static int die_counter; int ret; + /* Save regs to display in xbl mode */ + if (!panic_info) + panic_info = (void *)regs; + pr_emerg("Internal error: %s: %x [#%d]" S_PREEMPT S_SMP "\n", str, err, ++die_counter); @@ -303,12 +310,10 @@ static int call_undef_hook(struct pt_regs *regs) int (*fn)(struct pt_regs *regs, u32 instr) = NULL; void __user *pc = (void __user *)instruction_pointer(regs); - if (!user_mode(regs)) { - __le32 instr_le; - if (probe_kernel_address((__force __le32 *)pc, instr_le)) - goto exit; - instr = le32_to_cpu(instr_le); - } else if (compat_thumb_mode(regs)) { + if (!user_mode(regs)) + return 1; + + if (compat_thumb_mode(regs)) { /* 16-bit Thumb instruction */ __le16 instr_le; if (get_user(instr_le, (__le16 __user *)pc)) @@ -406,7 +411,6 @@ asmlinkage void __exception do_undefinstr(struct pt_regs *regs) trace_undef_instr(regs, pc); force_signal_inject(SIGILL, ILL_ILLOPC, regs, 0); - BUG_ON(!user_mode(regs)); } int cpu_enable_cache_maint_trap(void *__unused) diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c index b23cb41017563d1f962ce863a4405843832cb71d..c87f97a8740d87a833cc94ae99037b7f17bce3a6 100644 --- a/arch/arm64/mm/fault.c +++ b/arch/arm64/mm/fault.c @@ -488,6 +488,9 @@ static int __kprobes do_page_fault(unsigned long addr, unsigned int esr, * the mmap_sem because it would already be released * in __lock_page_or_retry in mm/filemap.c. */ +#ifdef CONFIG_MEMPLUS + count_vm_event(RETRYPAGE); +#endif if (fatal_signal_pending(current)) { if (!user_mode(regs)) goto no_context; diff --git a/block/blk-core.c b/block/blk-core.c index 0c7e240430c15fda69edcd0123836ca0c2182764..1d7fb3f2d91592d2244819e3fb08f47c3a550070 100644 --- a/block/blk-core.c +++ b/block/blk-core.c @@ -45,6 +45,10 @@ #include +#ifdef CONFIG_MEMPLUS +#include +#endif + #ifdef CONFIG_DEBUG_FS struct dentry *blk_debugfs_root; #endif @@ -117,6 +121,8 @@ void blk_rq_init(struct request_queue *q, struct request *rq) memset(rq, 0, sizeof(*rq)); INIT_LIST_HEAD(&rq->queuelist); + /*dylanchang, 2019/4/30, add foreground task io opt*/ + INIT_LIST_HEAD(&rq->fg_list); INIT_LIST_HEAD(&rq->timeout_list); rq->cpu = -1; rq->q = q; @@ -828,6 +834,9 @@ static void blk_rq_timed_out_timer(unsigned long data) kblockd_schedule_work(&q->timeout_work); } +/*dylanchang, 2019/4/30, add foreground task io opt*/ +#define FG_CNT_DEF 20 +#define BOTH_CNT_DEF 10 struct request_queue *blk_alloc_queue_node(gfp_t gfp_mask, int node_id) { struct request_queue *q; @@ -857,6 +866,11 @@ struct request_queue *blk_alloc_queue_node(gfp_t gfp_mask, int node_id) (VM_MAX_READAHEAD * 1024) / PAGE_SIZE; q->backing_dev_info->capabilities = BDI_CAP_CGROUP_WRITEBACK; q->backing_dev_info->name = "block"; +/*dylanchang, 2019/4/30, add foreground task io opt*/ + q->fg_count_max = FG_CNT_DEF; + q->both_count_max = BOTH_CNT_DEF; + q->fg_count = FG_CNT_DEF; + q->both_count = BOTH_CNT_DEF; q->node = node_id; setup_timer(&q->backing_dev_info->laptop_mode_wb_timer, @@ -864,6 +878,8 @@ struct request_queue *blk_alloc_queue_node(gfp_t gfp_mask, int node_id) setup_timer(&q->timeout, blk_rq_timed_out_timer, (unsigned long) q); INIT_WORK(&q->timeout_work, NULL); INIT_LIST_HEAD(&q->queue_head); +/*dylanchang, 2019/4/30, add foreground task io opt*/ + INIT_LIST_HEAD(&q->fg_head); INIT_LIST_HEAD(&q->timeout_list); INIT_LIST_HEAD(&q->icq_list); #ifdef CONFIG_BLK_CGROUP @@ -1797,7 +1813,9 @@ unsigned int blk_plug_queued_count(struct request_queue *q) void blk_init_request_from_bio(struct request *req, struct bio *bio) { struct io_context *ioc = rq_ioc(bio); - +/*dylanchang, 2019/4/30, add foreground task io opt*/ + if (bio->bi_opf & REQ_FG) + req->cmd_flags |= REQ_FG; if (bio->bi_opf & REQ_RAHEAD) req->cmd_flags |= REQ_FAILFAST_MASK; @@ -2271,6 +2289,83 @@ blk_qc_t generic_make_request(struct bio *bio) } EXPORT_SYMBOL(generic_make_request); +/*dylanchang, 2019/4/30, add foreground task io opt*/ +#define SYSTEM_APP_UID 1000 +static bool is_system_uid(struct task_struct *t) +{ + int cur_uid; + + cur_uid = task_uid(t).val; + if (cur_uid == SYSTEM_APP_UID) + return true; + + return false; +} + +static bool is_zygote_process(struct task_struct *t) +{ + const struct cred *tcred = __task_cred(t); + + struct task_struct *first_child = NULL; + + if (t->children.next && t->children.next != + (struct list_head *)&t->children.next) + first_child = + container_of(t->children.next, + struct task_struct, sibling); + if (!strcmp(t->comm, "main") && (tcred->uid.val == 0) && + (t->parent != 0 && !strcmp(t->parent->comm, "init"))) + return true; + else + return false; + return false; +} + +static bool is_system_process(struct task_struct *t) +{ + if (is_system_uid(t)) { + if (t->group_leader && ( + !strncmp(t->group_leader->comm, "system_server", 13) || + !strncmp(t->group_leader->comm, "surfaceflinger", 14) || + !strncmp(t->group_leader->comm, "servicemanager", 14) || + !strncmp(t->group_leader->comm, "ndroid.systemui", 15))) + return true; + } + return false; +} + +bool is_critial_process(struct task_struct *t) +{ + if (is_zygote_process(t) || is_system_process(t)) + return true; + + return false; +} + +bool is_filter_process(struct task_struct *t) +{ + if (!strncmp(t->comm, "logcat", TASK_COMM_LEN)) + return true; + + return false; +} +static bool high_prio_for_task(struct task_struct *t) +{ + int cur_uid; + + if (!sysctl_fg_io_opt) + return false; + + cur_uid = task_uid(t).val; + if ((is_fg(cur_uid) && !is_system_uid(t) && + !is_filter_process(t)) || + is_critial_process(t)) + return true; + + return false; +} + + /** * submit_bio - submit a bio to the block device layer for I/O * @bio: The &struct bio which describes the I/O @@ -2310,7 +2405,16 @@ blk_qc_t submit_bio(struct bio *bio) bio_devname(bio, b), count); } } - +/*dylanchang, 2019/4/30, add foreground task io opt*/ +#ifdef CONFIG_MEMPLUS + if (current_is_swapind()) + bio->bi_opf |= REQ_FG; + else if (high_prio_for_task(current)) + bio->bi_opf |= REQ_FG; +#else + if (high_prio_for_task(current)) + bio->bi_opf |= REQ_FG; +#endif return generic_make_request(bio); } EXPORT_SYMBOL(submit_bio); @@ -2663,6 +2767,10 @@ static void blk_dequeue_request(struct request *rq) list_del_init(&rq->queuelist); +/*dylanchang, 2019/4/30, add foreground task io opt*/ + if (sysctl_fg_io_opt && (rq->cmd_flags & REQ_FG)) + list_del_init(&rq->fg_list); + /* * the time frame between a request being removed from the lists * and to it is freed is accounted as io that is in progress at diff --git a/block/blk-flush.c b/block/blk-flush.c index 6603352879e73e2c36b6450613ad593d59245c6d..86ef012d5f58948b2045228bb66acd27c15aec65 100644 --- a/block/blk-flush.c +++ b/block/blk-flush.c @@ -138,10 +138,15 @@ static bool blk_flush_queue_rq(struct request *rq, bool add_front) blk_mq_add_to_requeue_list(rq, add_front, true); return false; } else { - if (add_front) + +/*dylanchang, 2019/4/30, add foreground task io opt*/ + if (add_front) { list_add(&rq->queuelist, &rq->q->queue_head); - else + queue_throtl_add_request(rq->q, rq, true); + } else { list_add_tail(&rq->queuelist, &rq->q->queue_head); + queue_throtl_add_request(rq->q, rq, false); + } return true; } } @@ -465,7 +470,11 @@ void blk_insert_flush(struct request *rq) if (q->mq_ops) blk_mq_sched_insert_request(rq, false, true, false, false); else +/*dylanchang, 2019/4/30, add foreground task io opt*/ + { list_add_tail(&rq->queuelist, &q->queue_head); + queue_throtl_add_request(q, rq, false); + } return; } diff --git a/block/blk-sysfs.c b/block/blk-sysfs.c index e54be402899daa18dc45ef35130d7e191d459bb0..92302b196695200f9e5025116d09ef56edd330b6 100644 --- a/block/blk-sysfs.c +++ b/block/blk-sysfs.c @@ -111,6 +111,49 @@ queue_ra_store(struct request_queue *q, const char *page, size_t count) return ret; } +/*dylanchang, 2019/4/30, add foreground task io opt*/ +static ssize_t queue_fgio_show(struct request_queue *q, char *page) +{ + int cnt = q->fg_count_max; + + return queue_var_show(cnt, (page)); +} + +static ssize_t +queue_fgio_store(struct request_queue *q, const char *page, size_t count) +{ + unsigned long cnt; + ssize_t ret = queue_var_store(&cnt, page, count); + + if (ret < 0) + return ret; + + q->fg_count_max = cnt; + + return ret; +} +static ssize_t queue_bothio_show(struct request_queue *q, char *page) +{ + int cnt = q->both_count_max; + + return queue_var_show(cnt, (page)); +} + +static ssize_t +queue_bothio_store(struct request_queue *q, const char *page, size_t count) +{ + unsigned long cnt; + ssize_t ret = queue_var_store(&cnt, page, count); + + if (ret < 0) + return ret; + + q->both_count_max = cnt; + + return ret; +} + + static ssize_t queue_max_sectors_show(struct request_queue *q, char *page) { int max_sectors_kb = queue_max_sectors(q) >> 1; @@ -517,6 +560,20 @@ static struct queue_sysfs_entry queue_ra_entry = { .store = queue_ra_store, }; +/*dylanchang, 2019/4/30, add foreground task io opt*/ +static struct queue_sysfs_entry queue_fgio_entry = { + .attr = {.name = "fg_io_cnt_max", .mode = 0644 }, + .show = queue_fgio_show, + .store = queue_fgio_store, +}; + +static struct queue_sysfs_entry queue_bothio_entry = { + .attr = {.name = "both_io_cnt_max", .mode = 0644 }, + .show = queue_bothio_show, + .store = queue_bothio_store, +}; + + static struct queue_sysfs_entry queue_max_sectors_entry = { .attr = {.name = "max_sectors_kb", .mode = S_IRUGO | S_IWUSR }, .show = queue_max_sectors_show, @@ -690,6 +747,9 @@ static struct queue_sysfs_entry throtl_sample_time_entry = { static struct attribute *default_attrs[] = { &queue_requests_entry.attr, &queue_ra_entry.attr, +/*dylanchang, 2019/4/30, add foreground task io opt*/ + &queue_fgio_entry.attr, + &queue_bothio_entry.attr, &queue_max_hw_sectors_entry.attr, &queue_max_sectors_entry.attr, &queue_max_segments_entry.attr, diff --git a/block/blk.h b/block/blk.h index b2c287c2c6a3bbf5a064fd49de7e6baa06ffc482..4a1ec390a358f8d8609843eece2fb85da3de1f32 100644 --- a/block/blk.h +++ b/block/blk.h @@ -149,6 +149,12 @@ static inline void blk_clear_rq_complete(struct request *rq) void blk_insert_flush(struct request *rq); +/*dylanchang, 2019/4/30, add foreground task io opt*/ +extern int fg_count; +extern int both_count; +extern bool fg_debug; +extern unsigned int sysctl_fg_io_opt; + static inline struct request *__elv_next_request(struct request_queue *q) { struct request *rq; @@ -158,7 +164,32 @@ static inline struct request *__elv_next_request(struct request_queue *q) while (1) { if (!list_empty(&q->queue_head)) { - rq = list_entry_rq(q->queue_head.next); +/*dylanchang, 2019/4/30, add foreground task io opt*/ + if (unlikely(!sysctl_fg_io_opt)) + rq = list_entry_rq(q->queue_head.next); + else { +#ifdef CONFIG_PM + if (!list_empty(&q->fg_head) && + q->fg_count > 0 && + (q->rpm_status == RPM_ACTIVE)) { +#else + if (!list_empty(&q->fg_head) && + q->fg_count > 0) { +#endif + rq = list_entry( + q->fg_head.next, + struct request, + fg_list); + q->fg_count--; + } else if (q->both_count > 0) { + rq = list_entry_rq(q->queue_head.next); + q->both_count--; + } else { + q->fg_count = q->fg_count_max; + q->both_count = q->both_count_max; + rq = list_entry_rq(q->queue_head.next); + } + } return rq; } diff --git a/block/elevator.c b/block/elevator.c index 2346c5b53b9337fc2ac860671bfa9a1bd8493e1a..bda37816da9bb8b9039ea709b3e63a1b7a1a0952 100644 --- a/block/elevator.c +++ b/block/elevator.c @@ -204,6 +204,8 @@ int elevator_init(struct request_queue *q, char *name) return 0; INIT_LIST_HEAD(&q->queue_head); +/*dylanchang, 2019/4/30, add foreground task io opt*/ + INIT_LIST_HEAD(&q->fg_head); q->last_merge = NULL; q->end_sector = 0; q->boundary_rq = NULL; @@ -415,6 +417,8 @@ void elv_dispatch_sort(struct request_queue *q, struct request *rq) } list_add(&rq->queuelist, entry); +/*dylanchang, 2019/4/30, add foreground task io opt*/ + queue_throtl_add_request(q, rq, false); } EXPORT_SYMBOL(elv_dispatch_sort); @@ -435,6 +439,8 @@ void elv_dispatch_add_tail(struct request_queue *q, struct request *rq) q->end_sector = rq_end_sector(rq); q->boundary_rq = rq; list_add_tail(&rq->queuelist, &q->queue_head); +/*dylanchang, 2019/4/30, add foreground task io opt*/ + queue_throtl_add_request(q, rq, false); } EXPORT_SYMBOL(elv_dispatch_add_tail); @@ -663,12 +669,16 @@ void __elv_add_request(struct request_queue *q, struct request *rq, int where) case ELEVATOR_INSERT_FRONT: rq->rq_flags |= RQF_SOFTBARRIER; list_add(&rq->queuelist, &q->queue_head); +/*dylanchang, 2019/4/30, add foreground task io opt*/ + queue_throtl_add_request(q, rq, true); break; case ELEVATOR_INSERT_BACK: rq->rq_flags |= RQF_SOFTBARRIER; elv_drain_elevator(q); list_add_tail(&rq->queuelist, &q->queue_head); +/*dylanchang, 2019/4/30, add foreground task io opt*/ + queue_throtl_add_request(q, rq, false); /* * We kick the queue here for the following reasons. * - The elevator might have returned NULL previously diff --git a/coretech/.gitignore b/coretech/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..ab5c102e72c4a047b8bc9bd9e2f6d89c1a4b70de --- /dev/null +++ b/coretech/.gitignore @@ -0,0 +1,21 @@ +uxcore/* +!uxcore/Makefile +!uxcore/opchain_helper.c +!uxcore/opchain_helper.h +!uxcore/opchain_define.h +memplus/* +!memplus/memplus_helper.c +!memplus/memplus_helper.h +!memplus/Makefile +smartboost/* +!smartboost/smartboost_helper.c +!smartboost/smartboost_helper.h +!smartboost/Makefile +defrag/* +!defrag/defrag_helper.c +!defrag/defrag_helper.h +!defrag/Makefile +fsc/* +houston/* +control_center/* +aigov/* diff --git a/coretech/Kconfig b/coretech/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..b363e86ed90c2224cfaee264bdc9a0581afd67e0 --- /dev/null +++ b/coretech/Kconfig @@ -0,0 +1,34 @@ +config OPCHAIN + default n + bool "Oneplus CoreTech helper, used for opchain module" +config MEMPLUS + default n + bool "memory+ feature" + help + Memory+ feature +config SMART_BOOST + bool "support smart boost feature" + default n + help + this feature allow memory used by recent-app stay in kernel. +config DEFRAG + default n + bool "anti-defragment feature" + help + anti-defragment feature. +config FSC + default n + bool "system layer file status cache" + help + To cache absence file and avoid stat call storm +config HOUSTON + default n + bool "to collect system-wide and pmu data" + help + Realtime temperature monitor +config CONTROL_CENTER + default n + bool "control center" +config AIGOV + default n + bool "A governor which using ai predicted info as input" diff --git a/coretech/Makefile b/coretech/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..1ef1c68bf567920178867ff644b6d7bb457aad08 --- /dev/null +++ b/coretech/Makefile @@ -0,0 +1,28 @@ +obj-$(CONFIG_OPCHAIN) += uxcore/ +CORE_PATH = $(KBUILD_SRC)/coretech/uxcore/core +ifeq ($(CORE_PATH),$(wildcard $(CORE_PATH))) +obj-$(CONFIG_OPCHAIN) += uxcore/core/ +endif + +obj-$(CONFIG_MEMPLUS) += memplus/ +CORE_PATH = $(KBUILD_SRC)/coretech/memplus/core +ifeq ($(CORE_PATH),$(wildcard $(CORE_PATH))) +obj-$(CONFIG_MEMPLUS) += memplus/core/ +endif + +obj-$(CONFIG_SMART_BOOST) += smartboost/ +CORE_PATH = $(KBUILD_SRC)/coretech/smartboost/core +ifeq ($(CORE_PATH),$(wildcard $(CORE_PATH))) +obj-$(CONFIG_SMART_BOOST) += smartboost/core/ +endif + +obj-$(CONFIG_DEFRAG) += defrag/ +CORE_PATH = $(KBUILD_SRC)/coretech/defrag/core +ifeq ($(CORE_PATH),$(wildcard $(CORE_PATH))) +obj-$(CONFIG_DEFRAG) += defrag/core/ +endif + +obj-$(CONFIG_FSC) += fsc/ +obj-$(CONFIG_HOUSTON) += houston/ +obj-$(CONFIG_CONTROL_CENTER) += control_center/ +obj-$(CONFIG_AIGOV) += aigov/ diff --git a/coretech/defrag/Makefile b/coretech/defrag/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..a1e70c67e401e009f65cbd09a408f9c0800d5737 --- /dev/null +++ b/coretech/defrag/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_DEFRAG) += defrag_helper.o diff --git a/coretech/defrag/defrag_helper.c b/coretech/defrag/defrag_helper.c new file mode 100644 index 0000000000000000000000000000000000000000..6538bfdbea34b1b642c6249ee57f672da7e361e8 --- /dev/null +++ b/coretech/defrag/defrag_helper.c @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +struct defrag_cb_set defrag_cbs; +atomic64_t fp_order_usage[MAX_ORDER] = {ATOMIC64_INIT(0)}; +atomic64_t fp_order_fail[MAX_ORDER] = {ATOMIC64_INIT(0)}; + +/* calling functions */ +struct page *defrag_alloc(struct zone *zone, unsigned long flags, + int migratetype, int order) +{ + if (defrag_cbs.defrag_alloc_cb) + return defrag_cbs.defrag_alloc_cb(zone, + flags, migratetype, order); + return NULL; +} + +long defrag_calc(struct zone *zone, int order, int alloc_flag) +{ + if (likely(defrag_cbs.defrag_calc_cb)) + return defrag_cbs.defrag_calc_cb(zone, order, alloc_flag); + else + return defrag_zone_free_size(zone); +} + +bool defrag_check_alloc_flag(unsigned int alloc_flags, int order) +{ + if (defrag_cbs.defrag_check_alloc_flag_cb) + return defrag_cbs.defrag_check_alloc_flag_cb(alloc_flags, + order); + return false; +} + +void defrag_register_cb_set(struct defrag_cb_set *cbs) +{ + defrag_cbs = *cbs; +} + +void defrag_unregister_cb_set(void) +{ + defrag_cbs.defrag_alloc_cb = NULL; + defrag_cbs.defrag_check_alloc_flag_cb = NULL; + defrag_cbs.defrag_calc_cb = NULL; +} diff --git a/coretech/memplus/Makefile b/coretech/memplus/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..2bff8d58cde398493f8e2a2499f629f79bb3c8dd --- /dev/null +++ b/coretech/memplus/Makefile @@ -0,0 +1 @@ +obj-y += memplus_helper.o diff --git a/coretech/memplus/memplus_helper.c b/coretech/memplus/memplus_helper.c new file mode 100644 index 0000000000000000000000000000000000000000..886126e9951a1617f7b9949927a7f8e2775583fc --- /dev/null +++ b/coretech/memplus/memplus_helper.c @@ -0,0 +1,61 @@ +#include +#include + +static struct memplus_cb_set cb_set; +#define PF_NO_TAIL(page, enforce) ({ \ + VM_BUG_ON_PGFLAGS(enforce && PageTail(page), page); \ + compound_head(page); }) + +bool memplus_enabled(void) +{ + if (cb_set.memplus_enabled_cb) + return cb_set.memplus_enabled_cb(); + return false; +} +bool __memplus_enabled(void) +{ + if (cb_set.__memplus_enabled_cb) + return cb_set.__memplus_enabled_cb(); + return false; +} +bool current_is_swapind(void) +{ + if (cb_set.current_is_swapind_cb) + return cb_set.current_is_swapind_cb(); + return false; +} + +void memplus_move_swapcache_to_anon_lru(struct page *page) +{ + if (cb_set.memplus_move_swapcache_to_anon_lru_cb) + cb_set.memplus_move_swapcache_to_anon_lru_cb(page); + else + clear_bit(PG_swapcache, &(PF_NO_TAIL(page, 1))->flags); +} +void memplus_move_anon_to_swapcache_lru(struct page *page) +{ + if (cb_set.memplus_move_anon_to_swapcache_lru_cb) + cb_set.memplus_move_anon_to_swapcache_lru_cb(page); + else + set_bit(PG_swapcache, &(PF_NO_TAIL(page, 1))->flags); +} +void memplus_state_check(bool legacy, int oom_adj, + struct task_struct *task, int type, int update) +{ + if (cb_set.memplus_state_check_cb) + cb_set.memplus_state_check_cb(legacy, + oom_adj, task, type, update); +} +bool memplus_check_isolate_page(struct page *page) +{ + if (cb_set.memplus_check_isolate_page_cb) + return cb_set.memplus_check_isolate_page_cb(page); + return false; +} + +void register_cb_set(struct memplus_cb_set *set) +{ + cb_set = *set; +} + +#undef PF_NO_TAIL diff --git a/coretech/smartboost/Makefile b/coretech/smartboost/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..6091ef65fe332e906d216d61be8585f3f630ad53 --- /dev/null +++ b/coretech/smartboost/Makefile @@ -0,0 +1 @@ +obj-y += smartboost_helper.o diff --git a/coretech/smartboost/smartboost_helper.c b/coretech/smartboost/smartboost_helper.c new file mode 100644 index 0000000000000000000000000000000000000000..6d5019c223c1302e75447be69755b97483f62a04 --- /dev/null +++ b/coretech/smartboost/smartboost_helper.c @@ -0,0 +1,38 @@ +#include +#include + +struct smb_cb_set smb_cbs; + +bool smb_uid_lru_add(struct page *page) +{ + if (smb_cbs.smb_uid_lru_add_cb) + return smb_cbs.smb_uid_lru_add_cb(page); + else + return false; +} + +unsigned long smb_isolate_list_or_putbcak(struct list_head *page_list, + struct lruvec *lruvec, struct pglist_data *pgdat, int priority, + bool enough_list_reclaimed) +{ + if (smb_cbs.smb_isolate_list_or_putbcak_cb) + return smb_cbs.smb_isolate_list_or_putbcak_cb(page_list, + lruvec, pgdat, priority, enough_list_reclaimed); + else + return 0; +} + +bool smb_update_uid_lru_size(struct page *page, + struct lruvec *lruvec, enum lru_list lru) +{ + if (smb_cbs.smb_update_uid_lru_size_cb) + return smb_cbs.smb_update_uid_lru_size_cb(page, lruvec, lru); + else + return false; +} + +void smb_register_cb_set(struct smb_cb_set *set) +{ + smb_cbs = *set; +} + diff --git a/coretech/uxcore/Makefile b/coretech/uxcore/Makefile new file mode 100755 index 0000000000000000000000000000000000000000..6a11f257f9308914e6e775165eca803f9b2e9624 --- /dev/null +++ b/coretech/uxcore/Makefile @@ -0,0 +1 @@ +obj-y += opchain_helper.o diff --git a/coretech/uxcore/opchain_define.h b/coretech/uxcore/opchain_define.h new file mode 100755 index 0000000000000000000000000000000000000000..27e359c838b661f29428be43d3f3b07b0f5a27d3 --- /dev/null +++ b/coretech/uxcore/opchain_define.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _LINUX_OPCHAIN_DEFINE_H +#define _LINUX_OPCHAIN_DEFINE_H + +#define UX_DEBUG 0 +#define UTASK 0 +#define UT_CLK_BASE 0x01 +#define UT_ETASK 0x02 +#define UT_LATEST_ONE 0x04 +#define UT_PERF_TOP 0x08 +#define UT_FORE (UT_CLK_BASE | UT_ETASK) + +#define OP_CLAIM_S -1 +#define OP_PATH_SLAVE -4 +#define OP_PATH_CLAIM -3 +#define OP_PATH_NORMAL -2 +#define OP_PATH_OCCUPIED -1 +#define MIN_POWER_CPU 0 + +#define ONESEC_NANO 1000000000 + +#if 1 +/* for MSM8998, SDM845*/ +#define FIRST_BIG_CORE 4 +#define NUMS_CPU 8 +#define CPU_VIRTUAL_PLUG_IN(i) (opc_cpu_active(i) && !opc_cpu_isolated(i)) +#else +/* for MSM8996*/ +#define FIRST_BIG_CORE 2 +#define NUMS_CPU 4 +#define CPU_VIRTUAL_PLUG_IN(i) (opc_cpu_active(i)) +#endif + +struct opchain_cb { + unsigned int (*is_opc_task_t)(void *rq, void *t, int type); + int (*opc_binder_pass_t)(void *rq, void* cur, unsigned int dsize, unsigned int *data, int send); + void (*opc_task_switch_t)(unsigned int enqueue, int cpu, void *p, void *rq, unsigned long long clock); + int (*opc_get_claim_on_cpu_t)(int cpu, void *rq); + unsigned int (*opc_get_claims_t)(void **rqs); + int (*opc_select_path_t)(void **rqs, void *w_rq, void *t_rq, void *cur, void *t, int prev_cpu); + unsigned long (*opc_cpu_util_t)(unsigned long util, int cpu, void *t, void *rq, int op_path); + void (*opc_add_to_chain_t)(void *rq, void *t); + int (*opc_check_uxtop_cpu_t)(int uxtop, int cpu); +}; +#endif diff --git a/coretech/uxcore/opchain_helper.c b/coretech/uxcore/opchain_helper.c new file mode 100755 index 0000000000000000000000000000000000000000..6bc6673be351c3e7093d0515017373b3ec8ad1f6 --- /dev/null +++ b/coretech/uxcore/opchain_helper.c @@ -0,0 +1,168 @@ +/* + * Copyright (c) 2015-2017, The OnePlus corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "../kernel/sched/sched.h" +#include "opchain_define.h" + +// tedlin@ASTI 2019/06/12 add for CONFIG_HOUSTON +#include + +#define t_rq(t) task_rq(t) +#define c_rq(cpu) cpu_rq(cpu) + +struct opchain_cb uxcore_api = {NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL}; +EXPORT_SYMBOL(uxcore_api); + +unsigned int *opc_boost_tl; +EXPORT_SYMBOL(opc_boost_tl); + +unsigned int *opc_boost; +EXPORT_SYMBOL(opc_boost); + +void opc_set_boost(unsigned int val) +{ + if (opc_boost) + *opc_boost = val; +} +EXPORT_SYMBOL(opc_set_boost); + +bool is_opc_task(struct task_struct *t, int type) +{ + if (uxcore_api.is_opc_task_t) + return uxcore_api.is_opc_task_t((void *)t_rq(t), (void *)t, type); + return 0; +} +EXPORT_SYMBOL(is_opc_task); + +void opc_binder_pass(size_t data_size, uint32_t *data, int send) +{ + if (uxcore_api.opc_binder_pass_t) { + if (uxcore_api.opc_binder_pass_t((void *)t_rq(current), (void *)current, data_size, data, send)) +// tedlin@ASTI 2019/06/12 add for CONFIG_HOUSTON + ht_perf_notify(); + } +} +EXPORT_SYMBOL(opc_binder_pass); + +void opc_task_switch(unsigned int enqueue, int cpu, struct task_struct *p, u64 clock) { + if (uxcore_api.opc_task_switch_t) + uxcore_api.opc_task_switch_t(enqueue, cpu, (void *)p, (void *)t_rq(p), clock); +} +EXPORT_SYMBOL(opc_task_switch); + +int opc_get_claim_on_cpu(int cpu) +{ + if (uxcore_api.opc_get_claim_on_cpu_t) + return uxcore_api.opc_get_claim_on_cpu_t(cpu, (void *)c_rq(cpu)); + return 0; +} +EXPORT_SYMBOL(opc_get_claim_on_cpu); + +unsigned int opc_get_claims(void) +{ + void *rqs[NUMS_CPU]; + int idx; + + if (uxcore_api.opc_get_claims_t) { + for (idx = 0; idx < NUMS_CPU; idx++) { + rqs[idx] = (void *)c_rq(idx); + } + return uxcore_api.opc_get_claims_t(rqs); + } + return 0; +} +EXPORT_SYMBOL(opc_get_claims); + +int opc_select_path(struct task_struct *cur, struct task_struct *t, int prev_cpu) +{ + void *rqs[NUMS_CPU]; + int idx; + + if (uxcore_api.opc_select_path_t) { + for (idx = 0; idx < NUMS_CPU; idx++) { + rqs[idx] = (void *)c_rq(idx); + } + return uxcore_api.opc_select_path_t(rqs, (void *)t_rq(cur), (void *)t_rq(t), (void *)cur, (void *)t, prev_cpu); + } + return OP_PATH_NORMAL; +} +EXPORT_SYMBOL(opc_select_path); + +unsigned long opc_cpu_util(unsigned long util, int cpu, struct task_struct *t, int op_path) +{ + if (uxcore_api.opc_cpu_util_t) + return uxcore_api.opc_cpu_util_t(util, cpu, (void *)t, (void *)c_rq(cpu), op_path); + return util; +} +EXPORT_SYMBOL(opc_cpu_util); + +void opc_add_to_chain(struct task_struct *t) +{ + if (uxcore_api.opc_add_to_chain_t) + uxcore_api.opc_add_to_chain_t((void *)t_rq(t), (void *)t); +} +EXPORT_SYMBOL(opc_add_to_chain); + +bool opc_check_uxtop_cpu(int uxtop, int cpu) +{ + if (uxcore_api.opc_check_uxtop_cpu_t) + return uxcore_api.opc_check_uxtop_cpu_t(uxtop, cpu); + return true; +} +EXPORT_SYMBOL(opc_check_uxtop_cpu); + +unsigned long __init opc_get_orig_capacity(int cpu) +{ + return cpu_rq(cpu)->cpu_capacity_orig; +} +EXPORT_SYMBOL(opc_get_orig_capacity); + +bool opc_utask_slave(struct task_struct *t) +{ + return t->utask_slave; +} +EXPORT_SYMBOL(opc_utask_slave); + +void __exit opc_exit_module(void) +{ + uxcore_api.opc_binder_pass_t = NULL; + uxcore_api.is_opc_task_t = NULL; + uxcore_api.opc_task_switch_t = NULL; + uxcore_api.opc_get_claim_on_cpu_t = NULL; + uxcore_api.opc_get_claims_t = NULL; + uxcore_api.opc_select_path_t = NULL; + uxcore_api.opc_cpu_util_t = NULL; + uxcore_api.opc_add_to_chain_t = NULL; + uxcore_api.opc_check_uxtop_cpu_t = NULL; + opc_boost_tl = NULL; + opc_boost = NULL; +} +EXPORT_SYMBOL(opc_exit_module); diff --git a/coretech/uxcore/opchain_helper.h b/coretech/uxcore/opchain_helper.h new file mode 100755 index 0000000000000000000000000000000000000000..5f6eeffa6dd1466b071d3051021c9d0d00de621d --- /dev/null +++ b/coretech/uxcore/opchain_helper.h @@ -0,0 +1,41 @@ +#ifndef _LINUX_OPCHAIN_HELPER_H +#define _LINUX_OPCHAIN_HELPER_H +#include "opchain_define.h" + +#ifdef CONFIG_OPCHAIN +extern struct opchain_cb uxcore_api; +extern void opc_binder_pass(size_t data_size, uint32_t *data, int send); +extern bool is_opc_task(struct task_struct *t, int type); +extern void opc_task_switch(bool enqueue, int cpu, struct task_struct *p, u64 clock); +extern int opc_get_claim_on_cpu(int cpu); +extern unsigned int opc_get_claims(void); +extern int opc_select_path(struct task_struct *cur, struct task_struct *t, int prev_cpu); +extern unsigned long opc_cpu_util(unsigned long util, int cpu, struct task_struct *t, int op_path); +extern bool opc_fps_check(int lvl); +extern void *opc_task_rq(void *t); +extern struct rq *opc_cpu_rq(int cpu); +extern unsigned int opc_task_load(struct task_struct *p); +extern int opc_cpu_active(int cpu); +extern int opc_cpu_isolated(int cpu); +bool opc_check_uxtop_cpu(int uxtop, int cpu); +bool opc_utask_slave(struct task_struct *t); +extern unsigned long __init opc_get_orig_capacity(int cpu); +extern void __exit opc_exit_module(void); +extern void opc_set_boost(unsigned int val); +#define UTASK_SLAVE(t) opc_utask_slave(t) + +#else +#define UTASK_SLAVE(t) 0 +static inline void opc_binder_pass(size_t data_size, uint32_t *data, int send) {} +static inline bool is_opc_task(struct task_struct *t, int type) { return 0; } +static inline void opc_task_switch(bool enqueue, int cpu, struct task_struct *p, u64 clock) {} +static inline int opc_get_claim_on_cpu(int cpu) { return 0; } +static inline unsigned int opc_get_claims(void) { return 0; } +static inline int opc_select_path(struct task_struct *cur, struct task_struct *t, int prev_cpu) { return OP_PATH_NORMAL; } +static inline unsigned long opc_cpu_util(unsigned long util, int cpu, struct task_struct *t, int op_path) { return util; } +static inline bool opc_fps_check(int lvl) { return false;} +static inline void opc_add_to_chain(struct task_struct *t) {} +static inline bool opc_check_uxtop_cpu(int uxtop, int cpu) { return true; } +static inline void opc_set_boost(unsigned int val) {}; +#endif +#endif diff --git a/drivers/Kconfig b/drivers/Kconfig index ed96eb7d8ba25d9213a4478b8531e4d3b8ff2aaa..5d43bd1fbf0b6ba1c59deefc42a4858ccbfa5c34 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -221,4 +221,14 @@ source "drivers/sensors/Kconfig" source "drivers/esoc/Kconfig" +source "drivers/oneplus/Kconfig" + +source "drivers/param_read_write/Kconfig" + +source "drivers/step_motor/Kconfig" + +source "drivers/tri_state_key/Kconfig" + +source "drivers/oem_debug/Kconfig" +source "drivers/vibrator/Kconfig" endmenu diff --git a/drivers/Makefile b/drivers/Makefile index cef0160448bc4f0e228cecbe09cc1ab8c4d7342e..f8939274059d75c4ca8405407d1865dad4523b2c 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -188,5 +188,12 @@ obj-$(CONFIG_TEE) += tee/ obj-$(CONFIG_MULTIPLEXER) += mux/ obj-$(CONFIG_SENSORS_SSC) += sensors/ obj-$(CONFIG_ESOC) += esoc/ +obj-y += oneplus/ +obj-y += param_read_write/ +obj-y += step_motor/ +obj-$(CONFIG_TRI_STATE_KEY) += tri_state_key/ +obj-$(CONFIG_AW8697_HAPTIC) += vibrator/ +obj-y += oem_debug/ +obj-y += infrared_proximity/infrared_power_control.o # GNSS driver obj-$(CONFIG_GNSS_SIRF) += gnsssirf/ diff --git a/drivers/android/binder.c b/drivers/android/binder.c index 64824dc8fc225f4781a955fed0aae30874994b4c..b9b7f6b5279a265c25f86741fff90bfd9045b3b1 100644 --- a/drivers/android/binder.c +++ b/drivers/android/binder.c @@ -3324,8 +3324,13 @@ static void binder_transaction(struct binder_proc *proc, sg_buf_offset = ALIGN(off_end_offset, sizeof(void *)); sg_buf_end_offset = sg_buf_offset + extra_buffers_size; off_min = 0; + + binder_alloc_pass_binder_buffer(&target_proc->alloc, + t->buffer, tr->data_size); + for (buffer_offset = off_start_offset; buffer_offset < off_end_offset; buffer_offset += sizeof(binder_size_t)) { + struct binder_object_header *hdr; size_t object_size; struct binder_object object; diff --git a/drivers/android/binder_alloc.c b/drivers/android/binder_alloc.c index 7b8a4bea865060c11ea93dc4542dd143ea1e2941..3721980caa46a2a6a74c080c215c2ad7b32a60d6 100644 --- a/drivers/android/binder_alloc.c +++ b/drivers/android/binder_alloc.c @@ -32,6 +32,7 @@ #include #include "binder_alloc.h" #include "binder_trace.h" +#include <../coretech/uxcore/opchain_helper.h> struct list_lru binder_alloc_lru; @@ -1117,6 +1118,21 @@ binder_alloc_copy_user_to_buffer(struct binder_alloc *alloc, return 0; } +void binder_alloc_pass_binder_buffer(struct binder_alloc *alloc, + struct binder_buffer *buffer, + binder_size_t buffer_size) +{ + struct page *page; + pgoff_t pgoff; + void *kptr; + + page = binder_alloc_get_page(alloc, buffer, + 0, &pgoff); + kptr = kmap_atomic(page) + pgoff; + opc_binder_pass(buffer_size, kptr, 1); + kunmap_atomic(kptr); +} + static void binder_alloc_do_buffer_copy(struct binder_alloc *alloc, bool to_buffer, struct binder_buffer *buffer, diff --git a/drivers/android/binder_alloc.h b/drivers/android/binder_alloc.h index b60d161b7a7ae98c412ca9c075af530da4d67ee9..c44797de7f446493e1f662456af33e6d027868a5 100644 --- a/drivers/android/binder_alloc.h +++ b/drivers/android/binder_alloc.h @@ -161,6 +161,10 @@ binder_alloc_get_free_async_space(struct binder_alloc *alloc) return free_async_space; } +void binder_alloc_pass_binder_buffer(struct binder_alloc *alloc, + struct binder_buffer *buffer, + binder_size_t buffer_size); + unsigned long binder_alloc_copy_user_to_buffer(struct binder_alloc *alloc, struct binder_buffer *buffer, diff --git a/drivers/base/power/wakeup.c b/drivers/base/power/wakeup.c index 79cf4c0fb2b7f5f19883747afb0f1a67a4d04d3c..8114e8883cc78576a2acab243fd62098e46a6247 100644 --- a/drivers/base/power/wakeup.c +++ b/drivers/base/power/wakeup.c @@ -22,6 +22,8 @@ #include #include "power.h" +#include +#include /* * If set, the suspend/hibernate code will abort transitions to a sleep state @@ -71,6 +73,10 @@ static struct wakeup_source deleted_ws = { .lock = __SPIN_LOCK_UNLOCKED(deleted_ws.lock), }; +#define WORK_TIMEOUT (60*1000) +static void ws_printk(struct work_struct *work); +static DECLARE_DELAYED_WORK(ws_printk_work, ws_printk); + /** * wakeup_source_prepare - Prepare a new wakeup source for initialization. * @ws: Wakeup source to prepare. @@ -856,7 +862,7 @@ void pm_print_active_wakeup_sources(void) srcuidx = srcu_read_lock(&wakeup_srcu); list_for_each_entry_rcu(ws, &wakeup_sources, entry) { if (ws->active) { - pr_debug("active wakeup source: %s\n", ws->name); + pr_info("active wakeup source: %s\n", ws->name); active = 1; } else if (!active && (!last_activity_ws || @@ -867,12 +873,30 @@ void pm_print_active_wakeup_sources(void) } if (!active && last_activity_ws) - pr_debug("last active wakeup source: %s\n", + pr_info("last active wakeup source: %s\n", last_activity_ws->name); srcu_read_unlock(&wakeup_srcu, srcuidx); } EXPORT_SYMBOL_GPL(pm_print_active_wakeup_sources); +static void ws_printk(struct work_struct *work) +{ + pm_print_active_wakeup_sources(); + queue_delayed_work(system_freezable_wq, + &ws_printk_work, msecs_to_jiffies(WORK_TIMEOUT)); +} + +void pm_print_active_wakeup_sources_queue(bool on) +{ + if (on) { + queue_delayed_work(system_freezable_wq, &ws_printk_work, + msecs_to_jiffies(WORK_TIMEOUT)); + } else { + cancel_delayed_work(&ws_printk_work); + } +} +EXPORT_SYMBOL_GPL(pm_print_active_wakeup_sources_queue); + /** * pm_wakeup_pending - Check if power transition in progress should be aborted. * @@ -936,6 +960,7 @@ void pm_system_irq_wakeup(unsigned int irq_number) else if (desc->action && desc->action->name) name = desc->action->name; + log_wakeup_reason(irq_number); pr_warn("%s: %d triggered %s\n", __func__, irq_number, name); diff --git a/drivers/base/regmap/regmap.c b/drivers/base/regmap/regmap.c index 8fd08023c0f5fae351800ab27d30a8a244eabaaa..cc60ddfd971fa90766cba4bc6e88391d4312a620 100644 --- a/drivers/base/regmap/regmap.c +++ b/drivers/base/regmap/regmap.c @@ -1651,6 +1651,9 @@ int _regmap_write(struct regmap *map, unsigned int reg, dev_info(map->dev, "%x <= %x\n", reg, val); #endif + if ( reg == 0x88E || reg == 0x88d) + dev_info(map->dev, "w:%x <= %x[%s],\n", reg, val,dev_name(map->dev)); + trace_regmap_reg_write(map, reg, val); return map->reg_write(context, reg, val); @@ -2379,6 +2382,8 @@ static int _regmap_read(struct regmap *map, unsigned int reg, if (map->dev && strcmp(dev_name(map->dev), LOG_DEVICE) == 0) dev_info(map->dev, "%x => %x\n", reg, *val); #endif + if ( reg == 0x88E || reg == 0x88d) + dev_info(map->dev, "r:%x <= %x[%s],\n", reg, val,dev_name(map->dev)); trace_regmap_reg_read(map, reg, *val); diff --git a/drivers/bus/mhi/controllers/mhi_arch_qcom.c b/drivers/bus/mhi/controllers/mhi_arch_qcom.c index 56708218081ef2a58dba7e8eeeae9280d7b0a857..9be0e421fe0e4833af92df26ccf55bf7b64ed8d0 100644 --- a/drivers/bus/mhi/controllers/mhi_arch_qcom.c +++ b/drivers/bus/mhi/controllers/mhi_arch_qcom.c @@ -202,6 +202,7 @@ static void mhi_arch_esoc_ops_power_off(void *priv, unsigned int flags) struct arch_info *arch_info = mhi_dev->arch_info; struct pci_dev *pci_dev = mhi_dev->pci_dev; + MHI_LOG("Enter: mdm_crashed:%d\n", mdm_state); /* diff --git a/drivers/bus/mhi/core/mhi_init.c b/drivers/bus/mhi/core/mhi_init.c index da10001d560c7215d250e1baee22f4c811da709f..8765f1428a6917612214d6a2e58c51e8881f97f5 100644 --- a/drivers/bus/mhi/core/mhi_init.c +++ b/drivers/bus/mhi/core/mhi_init.c @@ -1366,7 +1366,6 @@ void mhi_unregister_mhi_controller(struct mhi_controller *mhi_cntrl) list_del(&mhi_cntrl->node); mutex_unlock(&mhi_bus.lock); } -EXPORT_SYMBOL(mhi_unregister_mhi_controller); /* set ptr to control private data */ static inline void mhi_controller_set_devdata(struct mhi_controller *mhi_cntrl, @@ -1467,7 +1466,6 @@ void mhi_unprepare_after_power_down(struct mhi_controller *mhi_cntrl) mhi_deinit_dev_ctxt(mhi_cntrl); mhi_cntrl->pre_init = false; } -EXPORT_SYMBOL(mhi_unprepare_after_power_down); /* match dev to drv */ static int mhi_match(struct device *dev, struct device_driver *drv) @@ -1570,7 +1568,6 @@ static int mhi_driver_probe(struct device *dev) exit_probe: mhi_device_put(mhi_dev, MHI_VOTE_DEVICE); - return ret; } diff --git a/drivers/bus/mhi/core/mhi_internal.h b/drivers/bus/mhi/core/mhi_internal.h index 8853ba4a97c4be8eab329bd2f66b98699ed6edf6..e3aaca948dd293472d4e1c6278595facaaa1da06 100644 --- a/drivers/bus/mhi/core/mhi_internal.h +++ b/drivers/bus/mhi/core/mhi_internal.h @@ -773,6 +773,7 @@ static inline void mhi_timesync_log(struct mhi_controller *mhi_cntrl) readq_no_log(mhi_tsync->time_reg)); } + /* memory allocation methods */ static inline void *mhi_alloc_coherent(struct mhi_controller *mhi_cntrl, size_t size, diff --git a/drivers/bus/mhi/core/mhi_pm.c b/drivers/bus/mhi/core/mhi_pm.c index dd3e9bdc8744c2e8b84112c058e66042652a321a..6ecf5862cbcd3eb02428dd45fc132fd880698b61 100644 --- a/drivers/bus/mhi/core/mhi_pm.c +++ b/drivers/bus/mhi/core/mhi_pm.c @@ -499,6 +499,8 @@ static int mhi_pm_mission_mode_transition(struct mhi_controller *mhi_cntrl) /* add supported devices */ mhi_create_devices(mhi_cntrl); + /* setup sysfs nodes for userspace votes */ + mhi_create_vote_sysfs(mhi_cntrl); /* setup sysfs nodes for userspace votes */ mhi_create_vote_sysfs(mhi_cntrl); @@ -913,9 +915,6 @@ void mhi_control_error(struct mhi_controller *mhi_cntrl) goto exit_control_error; } - /* notify waiters to bail out early since MHI has entered ERROR state */ - wake_up_all(&mhi_cntrl->state_event); - /* start notifying all clients who request early notification */ device_for_each_child(mhi_cntrl->dev, NULL, mhi_early_notify_device); @@ -1329,7 +1328,6 @@ int mhi_pm_fast_resume(struct mhi_controller *mhi_cntrl, bool notify_client) return 0; } -EXPORT_SYMBOL(mhi_pm_resume); int __mhi_device_get_sync(struct mhi_controller *mhi_cntrl) { diff --git a/drivers/bus/mhi/devices/mhi_netdev.c b/drivers/bus/mhi/devices/mhi_netdev.c index 145157b35ba988727d6aaaf5a479c44b8c9df589..d32a5f482f36be4cd765e4743ceb15bff9c2c1cb 100644 --- a/drivers/bus/mhi/devices/mhi_netdev.c +++ b/drivers/bus/mhi/devices/mhi_netdev.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #define MHI_NETDEV_DRIVER_NAME "mhi_netdev" @@ -90,7 +89,6 @@ struct mhi_netdev { int alias; struct mhi_device *mhi_dev; struct mhi_netdev *rsc_dev; /* rsc linked node */ - struct mhi_netdev *rsc_parent; bool is_rsc_dev; int wake; @@ -100,26 +98,16 @@ struct mhi_netdev { struct napi_struct *napi; struct net_device *ndev; - struct list_head *recycle_pool; - int pool_size; + struct mhi_netbuf **netbuf_pool; + int pool_size; /* must be power of 2 */ + int current_index; bool chain_skb; struct mhi_net_chain *chain; - struct task_struct *alloc_task; - wait_queue_head_t alloc_event; - int bg_pool_limit; /* minimum pool size */ - int bg_pool_size; /* current size of the pool */ - struct list_head *bg_pool; - spinlock_t bg_lock; /* lock to access list */ - - struct dentry *dentry; enum MHI_DEBUG_LEVEL msg_lvl; enum MHI_DEBUG_LEVEL ipc_log_lvl; void *ipc_log; - - /* debug stats */ - u32 abuffers, kbuffers, rbuffers; }; struct mhi_netdev_priv { @@ -132,7 +120,6 @@ struct mhi_netdev_priv { */ struct mhi_netbuf { struct mhi_buf mhi_buf; /* this must be first element */ - bool recycle; void (*unmap)(struct device *dev, dma_addr_t addr, size_t size, enum dma_data_direction dir); }; @@ -177,15 +164,11 @@ static struct mhi_netbuf *mhi_netdev_alloc(struct device *dev, /* we going to use the end of page to store cached data */ netbuf = vaddr + (PAGE_SIZE << order) - sizeof(*netbuf); - netbuf->recycle = false; + mhi_buf = (struct mhi_buf *)netbuf; mhi_buf->page = page; mhi_buf->buf = vaddr; mhi_buf->len = (void *)netbuf - vaddr; - - if (!dev) - return netbuf; - mhi_buf->dma_addr = dma_map_page(dev, page, 0, mhi_buf->len, DMA_FROM_DEVICE); if (dma_mapping_error(dev, mhi_buf->dma_addr)) { @@ -204,10 +187,9 @@ static void mhi_netdev_unmap_page(struct device *dev, dma_unmap_page(dev, dma_addr, len, dir); } -static int mhi_netdev_tmp_alloc(struct mhi_netdev *mhi_netdev, - struct mhi_device *mhi_dev, - int nr_tre) +static int mhi_netdev_tmp_alloc(struct mhi_netdev *mhi_netdev, int nr_tre) { + struct mhi_device *mhi_dev = mhi_netdev->mhi_dev; struct device *dev = mhi_dev->dev.parent; const u32 order = mhi_netdev->order; int i, ret; @@ -231,73 +213,21 @@ static int mhi_netdev_tmp_alloc(struct mhi_netdev *mhi_netdev, __free_pages(mhi_buf->page, order); return ret; } - mhi_netdev->abuffers++; } return 0; } -static int mhi_netdev_queue_bg_pool(struct mhi_netdev *mhi_netdev, - struct mhi_device *mhi_dev, - int nr_tre) -{ - struct device *dev = mhi_dev->dev.parent; - int i, ret; - LIST_HEAD(head); - - spin_lock_bh(&mhi_netdev->bg_lock); - list_splice_init(mhi_netdev->bg_pool, &head); - spin_unlock_bh(&mhi_netdev->bg_lock); - - for (i = 0; i < nr_tre; i++) { - struct mhi_buf *mhi_buf = - list_first_entry_or_null(&head, struct mhi_buf, node); - struct mhi_netbuf *netbuf = (struct mhi_netbuf *)mhi_buf; - - if (!mhi_buf) - break; - - mhi_buf->dma_addr = dma_map_page(dev, mhi_buf->page, 0, - mhi_buf->len, DMA_FROM_DEVICE); - if (dma_mapping_error(dev, mhi_buf->dma_addr)) - break; - - netbuf->unmap = mhi_netdev_unmap_page; - ret = mhi_queue_transfer(mhi_dev, DMA_FROM_DEVICE, mhi_buf, - mhi_buf->len, MHI_EOT); - if (unlikely(ret)) { - MSG_ERR("Failed to queue transfer, ret:%d\n", ret); - mhi_netdev_unmap_page(dev, mhi_buf->dma_addr, - mhi_buf->len, DMA_FROM_DEVICE); - break; - } - list_del(&mhi_buf->node); - mhi_netdev->kbuffers++; - } - - /* add remaining buffers back to main pool */ - spin_lock_bh(&mhi_netdev->bg_lock); - list_splice(&head, mhi_netdev->bg_pool); - mhi_netdev->bg_pool_size -= i; - spin_unlock_bh(&mhi_netdev->bg_lock); - - - /* wake up the bg thread to allocate more buffers */ - wake_up_interruptible(&mhi_netdev->alloc_event); - - return i; -} - -static void mhi_netdev_queue(struct mhi_netdev *mhi_netdev, - struct mhi_device *mhi_dev) +static void mhi_netdev_queue(struct mhi_netdev *mhi_netdev) { + struct mhi_device *mhi_dev = mhi_netdev->mhi_dev; struct device *dev = mhi_dev->dev.parent; struct mhi_netbuf *netbuf; struct mhi_buf *mhi_buf; - struct list_head *pool = mhi_netdev->recycle_pool; + struct mhi_netbuf **netbuf_pool = mhi_netdev->netbuf_pool; int nr_tre = mhi_get_no_free_descriptors(mhi_dev, DMA_FROM_DEVICE); - int i, ret; - const int max_peek = 4; + int i, peak, cur_index, ret; + const int pool_size = mhi_netdev->pool_size - 1, max_peak = 4; MSG_VERB("Enter free_desc:%d\n", nr_tre); @@ -306,21 +236,23 @@ static void mhi_netdev_queue(struct mhi_netdev *mhi_netdev, /* try going thru reclaim pool first */ for (i = 0; i < nr_tre; i++) { - /* peek for the next buffer, we going to peak several times, + /* peak for the next buffer, we going to peak several times, * and we going to give up if buffers are not yet free */ - int peek = 0; - + cur_index = mhi_netdev->current_index; netbuf = NULL; - list_for_each_entry(mhi_buf, pool, node) { + for (peak = 0; peak < max_peak; peak++) { + struct mhi_netbuf *tmp = netbuf_pool[cur_index]; + + mhi_buf = &tmp->mhi_buf; + + cur_index = (cur_index + 1) & pool_size; + /* page == 1 idle, buffer is free to reclaim */ if (page_ref_count(mhi_buf->page) == 1) { - netbuf = (struct mhi_netbuf *)mhi_buf; + netbuf = tmp; break; } - - if (peek++ >= max_peek) - break; } /* could not find a free buffer */ @@ -331,7 +263,6 @@ static void mhi_netdev_queue(struct mhi_netdev *mhi_netdev, * with buffer, the buffer won't be freed */ page_ref_inc(mhi_buf->page); - list_del(&mhi_buf->node); dma_sync_single_for_device(dev, mhi_buf->dma_addr, mhi_buf->len, DMA_FROM_DEVICE); ret = mhi_queue_transfer(mhi_dev, DMA_FROM_DEVICE, mhi_buf, @@ -341,36 +272,30 @@ static void mhi_netdev_queue(struct mhi_netdev *mhi_netdev, netbuf->unmap(dev, mhi_buf->dma_addr, mhi_buf->len, DMA_FROM_DEVICE); page_ref_dec(mhi_buf->page); - list_add(&mhi_buf->node, pool); return; } - mhi_netdev->rbuffers++; + mhi_netdev->current_index = cur_index; } - /* recycling did not work, buffers are still busy use bg pool */ - if (i < nr_tre) - i += mhi_netdev_queue_bg_pool(mhi_netdev, mhi_dev, nr_tre - i); - /* recyling did not work, buffers are still busy allocate temp pkts */ if (i < nr_tre) - mhi_netdev_tmp_alloc(mhi_netdev, mhi_dev, nr_tre - i); + mhi_netdev_tmp_alloc(mhi_netdev, nr_tre - i); } /* allocating pool of memory */ static int mhi_netdev_alloc_pool(struct mhi_netdev *mhi_netdev) { int i; - struct mhi_netbuf *netbuf; - struct mhi_buf *mhi_buf, *tmp; + struct mhi_netbuf *netbuf, **netbuf_pool; + struct mhi_buf *mhi_buf; const u32 order = mhi_netdev->order; struct device *dev = mhi_netdev->mhi_dev->dev.parent; - struct list_head *pool = kmalloc(sizeof(*pool), GFP_KERNEL); - if (!pool) + netbuf_pool = kmalloc_array(mhi_netdev->pool_size, sizeof(*netbuf_pool), + GFP_KERNEL); + if (!netbuf_pool) return -ENOMEM; - INIT_LIST_HEAD(pool); - for (i = 0; i < mhi_netdev->pool_size; i++) { /* allocate paged data */ netbuf = mhi_netdev_alloc(dev, GFP_KERNEL, order); @@ -378,100 +303,44 @@ static int mhi_netdev_alloc_pool(struct mhi_netdev *mhi_netdev) goto error_alloc_page; netbuf->unmap = dma_sync_single_for_cpu; - netbuf->recycle = true; - mhi_buf = (struct mhi_buf *)netbuf; - list_add(&mhi_buf->node, pool); + netbuf_pool[i] = netbuf; } - mhi_netdev->recycle_pool = pool; + mhi_netdev->netbuf_pool = netbuf_pool; return 0; error_alloc_page: - list_for_each_entry_safe(mhi_buf, tmp, pool, node) { - list_del(&mhi_buf->node); + for (--i; i >= 0; i--) { + netbuf = netbuf_pool[i]; + mhi_buf = &netbuf->mhi_buf; dma_unmap_page(dev, mhi_buf->dma_addr, mhi_buf->len, DMA_FROM_DEVICE); __free_pages(mhi_buf->page, order); } - kfree(pool); + kfree(netbuf_pool); return -ENOMEM; } static void mhi_netdev_free_pool(struct mhi_netdev *mhi_netdev) { + int i; + struct mhi_netbuf *netbuf, **netbuf_pool = mhi_netdev->netbuf_pool; struct device *dev = mhi_netdev->mhi_dev->dev.parent; - struct mhi_buf *mhi_buf, *tmp; + struct mhi_buf *mhi_buf; - list_for_each_entry_safe(mhi_buf, tmp, mhi_netdev->recycle_pool, node) { - list_del(&mhi_buf->node); + for (i = 0; i < mhi_netdev->pool_size; i++) { + netbuf = netbuf_pool[i]; + mhi_buf = &netbuf->mhi_buf; dma_unmap_page(dev, mhi_buf->dma_addr, mhi_buf->len, DMA_FROM_DEVICE); __free_pages(mhi_buf->page, mhi_netdev->order); } - kfree(mhi_netdev->recycle_pool); - - /* free the bg pool */ - list_for_each_entry_safe(mhi_buf, tmp, mhi_netdev->bg_pool, node) { - list_del(&mhi_buf->node); - __free_pages(mhi_buf->page, mhi_netdev->order); - mhi_netdev->bg_pool_size--; - } -} - -static int mhi_netdev_alloc_thread(void *data) -{ - struct mhi_netdev *mhi_netdev = data; - struct mhi_netbuf *netbuf; - struct mhi_buf *mhi_buf, *tmp_buf; - const u32 order = mhi_netdev->order; - LIST_HEAD(head); - - while (!kthread_should_stop()) { - while (mhi_netdev->bg_pool_size <= mhi_netdev->bg_pool_limit) { - int buffers = 0, i; - - /* do a bulk allocation */ - for (i = 0; i < NAPI_POLL_WEIGHT; i++) { - if (kthread_should_stop()) - goto exit_alloc; - - netbuf = mhi_netdev_alloc(NULL, GFP_KERNEL, - order); - if (!netbuf) - continue; - - mhi_buf = (struct mhi_buf *)netbuf; - list_add(&mhi_buf->node, &head); - buffers++; - } - - /* add the list to main pool */ - spin_lock_bh(&mhi_netdev->bg_lock); - list_splice_init(&head, mhi_netdev->bg_pool); - mhi_netdev->bg_pool_size += buffers; - spin_unlock_bh(&mhi_netdev->bg_lock); - } - - /* replenish the ring */ - napi_schedule(mhi_netdev->napi); - - /* wait for buffers to run low or thread to stop */ - wait_event_interruptible(mhi_netdev->alloc_event, - kthread_should_stop() || - mhi_netdev->bg_pool_size <= mhi_netdev->bg_pool_limit); - } - -exit_alloc: - list_for_each_entry_safe(mhi_buf, tmp_buf, &head, node) { - list_del(&mhi_buf->node); - __free_pages(mhi_buf->page, order); - } - - return 0; + kfree(mhi_netdev->netbuf_pool); + mhi_netdev->netbuf_pool = NULL; } static int mhi_netdev_poll(struct napi_struct *napi, int budget) @@ -501,10 +370,10 @@ static int mhi_netdev_poll(struct napi_struct *napi, int budget) } /* queue new buffers */ - mhi_netdev_queue(mhi_netdev, mhi_dev); + mhi_netdev_queue(mhi_netdev); if (rsc_dev) - mhi_netdev_queue(mhi_netdev, rsc_dev->mhi_dev); + mhi_netdev_queue(rsc_dev); /* complete work if # of packet processed less than allocated budget */ if (rx_work < budget) @@ -798,8 +667,6 @@ static void mhi_netdev_xfer_dl_cb(struct mhi_device *mhi_dev, struct mhi_net_chain *chain = mhi_netdev->chain; netbuf->unmap(dev, mhi_buf->dma_addr, mhi_buf->len, DMA_FROM_DEVICE); - if (likely(netbuf->recycle)) - list_add_tail(&mhi_buf->node, mhi_netdev->recycle_pool); /* modem is down, drop the buffer */ if (mhi_result->transaction_status == -ENOTCONN) { @@ -850,31 +717,6 @@ static void mhi_netdev_status_cb(struct mhi_device *mhi_dev, enum MHI_CB mhi_cb) struct dentry *dentry; -static int mhi_netdev_debugfs_stats_show(struct seq_file *m, void *d) -{ - struct mhi_netdev *mhi_netdev = m->private; - - seq_printf(m, - "mru:%u order:%u pool_size:%d, bg_pool_size:%d bg_pool_limit:%d abuf:%u kbuf:%u rbuf:%u\n", - mhi_netdev->mru, mhi_netdev->order, mhi_netdev->pool_size, - mhi_netdev->bg_pool_size, mhi_netdev->bg_pool_limit, - mhi_netdev->abuffers, mhi_netdev->kbuffers, - mhi_netdev->rbuffers); - - return 0; -} - -static int mhi_netdev_debugfs_stats_open(struct inode *inode, struct file *fp) -{ - return single_open(fp, mhi_netdev_debugfs_stats_show, inode->i_private); -} - -static const struct file_operations debugfs_stats = { - .open = mhi_netdev_debugfs_stats_open, - .release = single_release, - .read = seq_read, -}; - static void mhi_netdev_create_debugfs(struct mhi_netdev *mhi_netdev) { char node_name[32]; @@ -891,9 +733,6 @@ static void mhi_netdev_create_debugfs(struct mhi_netdev *mhi_netdev) mhi_netdev->dentry = debugfs_create_dir(node_name, dentry); if (IS_ERR_OR_NULL(mhi_netdev->dentry)) return; - - debugfs_create_file_unsafe("stats", 0444, mhi_netdev->dentry, - mhi_netdev, &debugfs_stats); } static void mhi_netdev_create_debugfs_dir(void) @@ -925,12 +764,12 @@ static void mhi_netdev_remove(struct mhi_device *mhi_dev) return; } - kthread_stop(mhi_netdev->alloc_task); netif_stop_queue(mhi_netdev->ndev); napi_disable(mhi_netdev->napi); unregister_netdev(mhi_netdev->ndev); netif_napi_del(mhi_netdev->napi); free_netdev(mhi_netdev->ndev); + mhi_netdev_free_pool(mhi_netdev); if (!IS_ERR_OR_NULL(mhi_netdev->dentry)) debugfs_remove_recursive(mhi_netdev->dentry); @@ -952,9 +791,6 @@ static void mhi_netdev_clone_dev(struct mhi_netdev *mhi_netdev, mhi_netdev->ipc_log_lvl = parent->ipc_log_lvl; mhi_netdev->is_rsc_dev = true; mhi_netdev->chain = parent->chain; - mhi_netdev->rsc_parent = parent; - mhi_netdev->recycle_pool = parent->recycle_pool; - mhi_netdev->bg_pool = parent->bg_pool; } static int mhi_netdev_probe(struct mhi_device *mhi_dev, @@ -976,13 +812,6 @@ static int mhi_netdev_probe(struct mhi_device *mhi_dev, if (!mhi_netdev) return -ENOMEM; - /* move mhi channels to start state */ - ret = mhi_prepare_for_transfer(mhi_dev); - if (ret) { - MSG_ERR("Failed to start channels ret %d\n", ret); - return ret; - } - mhi_netdev->mhi_dev = mhi_dev; mhi_device_set_devdata(mhi_dev, mhi_netdev); @@ -1030,38 +859,6 @@ static int mhi_netdev_probe(struct mhi_device *mhi_dev, if (ret) return ret; - /* setup pool size ~2x ring length*/ - nr_tre = mhi_get_no_free_descriptors(mhi_dev, DMA_FROM_DEVICE); - mhi_netdev->pool_size = 1 << __ilog2_u32(nr_tre); - if (nr_tre > mhi_netdev->pool_size) - mhi_netdev->pool_size <<= 1; - mhi_netdev->pool_size <<= 1; - - /* if we expect child device to share then double the pool */ - if (of_parse_phandle(of_node, "mhi,rsc-child", 0)) - mhi_netdev->pool_size <<= 1; - - /* allocate memory pool */ - ret = mhi_netdev_alloc_pool(mhi_netdev); - if (ret) - return -ENOMEM; - - /* create a background task to allocate memory */ - mhi_netdev->bg_pool = kmalloc(sizeof(*mhi_netdev->bg_pool), - GFP_KERNEL); - if (!mhi_netdev->bg_pool) - return -ENOMEM; - - init_waitqueue_head(&mhi_netdev->alloc_event); - INIT_LIST_HEAD(mhi_netdev->bg_pool); - spin_lock_init(&mhi_netdev->bg_lock); - mhi_netdev->bg_pool_limit = mhi_netdev->pool_size / 4; - mhi_netdev->alloc_task = kthread_run(mhi_netdev_alloc_thread, - mhi_netdev, - mhi_netdev->ndev->name); - if (IS_ERR(mhi_netdev->alloc_task)) - return PTR_ERR(mhi_netdev->alloc_task); - /* create ipc log buffer */ snprintf(node_name, sizeof(node_name), "%s_%04x_%02u.%02u.%02u_%u", @@ -1075,6 +872,25 @@ static int mhi_netdev_probe(struct mhi_device *mhi_dev, mhi_netdev_create_debugfs(mhi_netdev); } + /* move mhi channels to start state */ + ret = mhi_prepare_for_transfer(mhi_dev); + if (ret) { + MSG_ERR("Failed to start channels ret %d\n", ret); + goto error_start; + } + + /* setup pool size ~2x ring length*/ + nr_tre = mhi_get_no_free_descriptors(mhi_dev, DMA_FROM_DEVICE); + mhi_netdev->pool_size = 1 << __ilog2_u32(nr_tre); + if (nr_tre > mhi_netdev->pool_size) + mhi_netdev->pool_size <<= 1; + mhi_netdev->pool_size <<= 1; + + /* allocate memory pool */ + ret = mhi_netdev_alloc_pool(mhi_netdev); + if (ret) + goto error_start; + /* link child node with parent node if it's children dev */ if (p_netdev) p_netdev->rsc_dev = mhi_netdev; @@ -1085,6 +901,18 @@ static int mhi_netdev_probe(struct mhi_device *mhi_dev, napi_schedule(mhi_netdev->napi); return 0; + +error_start: + if (phandle) + return ret; + + netif_stop_queue(mhi_netdev->ndev); + napi_disable(mhi_netdev->napi); + unregister_netdev(mhi_netdev->ndev); + netif_napi_del(mhi_netdev->napi); + free_netdev(mhi_netdev->ndev); + + return ret; } static const struct mhi_device_id mhi_netdev_match_table[] = { diff --git a/drivers/char/adsprpc.c b/drivers/char/adsprpc.c index e052a2bf4476f19ca9a9bf9614efc517d8bb8850..3c7f8ddf353e0d0404bb21eeedbee739d4660012 100644 --- a/drivers/char/adsprpc.c +++ b/drivers/char/adsprpc.c @@ -4048,15 +4048,16 @@ static int fastrpc_probe(struct platform_device *pdev) if (range.addr && !of_property_read_bool(dev->of_node, "restrict-access")) { int srcVM[1] = {VMID_HLOS}; - int destVM[3] = {VMID_HLOS, VMID_SSC_Q6, + int destVM[4] = {VMID_HLOS, VMID_MSS_MSA, VMID_SSC_Q6, VMID_ADSP_Q6}; - int destVMperm[3] = {PERM_READ | PERM_WRITE | PERM_EXEC, + int destVMperm[4] = {PERM_READ | PERM_WRITE | PERM_EXEC, + PERM_READ | PERM_WRITE | PERM_EXEC, PERM_READ | PERM_WRITE | PERM_EXEC, PERM_READ | PERM_WRITE | PERM_EXEC, }; VERIFY(err, !hyp_assign_phys(range.addr, range.size, - srcVM, 1, destVM, destVMperm, 3)); + srcVM, 1, destVM, destVMperm, 4)); if (err) goto bail; me->range.addr = range.addr; diff --git a/drivers/char/diag/diag_dci.c b/drivers/char/diag/diag_dci.c index aec1fd692eb9f3f07e4382f4aac4f80c3ef5f900..32566697f599aab5295831cc7c7e8d0285aaa777 100644 --- a/drivers/char/diag/diag_dci.c +++ b/drivers/char/diag/diag_dci.c @@ -726,44 +726,29 @@ int diag_dci_query_event_mask(struct diag_dci_client_tbl *entry, return ((*event_mask_ptr & byte_mask) == byte_mask) ? 1 : 0; } -static int diag_dci_filter_commands(struct diag_pkt_header_t *header, - int header_len) +static int diag_dci_filter_commands(struct diag_pkt_header_t *header) { if (!header) return -ENOMEM; - if (header_len <= 0) - return -EIO; - - if (header_len) { - switch (header->cmd_code) { - case 0x7d: /* Msg Mask Configuration */ - case 0x73: /* Log Mask Configuration */ - case 0x81: /* Event Mask Configuration */ - case 0x82: /* Event Mask Change */ - case 0x60: /* Event Mask Toggle */ - DIAG_LOG(DIAG_DEBUG_DCI, - "diag: command not supported: %d\n", - header->cmd_code); - return 1; - } + switch (header->cmd_code) { + case 0x7d: /* Msg Mask Configuration */ + case 0x73: /* Log Mask Configuration */ + case 0x81: /* Event Mask Configuration */ + case 0x82: /* Event Mask Change */ + case 0x60: /* Event Mask Toggle */ + return 1; } - if (header_len >= (3*sizeof(uint8_t))) { - if (header->cmd_code == 0x4b && header->subsys_id == 0x12) { - switch (header->subsys_cmd_code) { - case 0x60: /* Extended Event Mask Config */ - case 0x61: /* Extended Msg Mask Config */ - case 0x62: /* Extended Log Mask Config */ - case 0x20C: /* Set current Preset ID */ - case 0x20D: /* Get current Preset ID */ - case 0x218: /* HDLC Disabled Command */ - DIAG_LOG(DIAG_DEBUG_DCI, - "diag: command not supported %d %d %d\n", - header->cmd_code, header->subsys_id, - header->subsys_cmd_code); - return 1; - } + if (header->cmd_code == 0x4b && header->subsys_id == 0x12) { + switch (header->subsys_cmd_code) { + case 0x60: /* Extended Event Mask Config */ + case 0x61: /* Extended Msg Mask Config */ + case 0x62: /* Extended Log Mask Config */ + case 0x20C: /* Set current Preset ID */ + case 0x20D: /* Get current Preset ID */ + case 0x218: /* HDLC Disabled Command */ + return 1; } } @@ -1815,7 +1800,7 @@ int diag_dci_send_handshake_pkt(int index) static int diag_dci_process_apps_pkt(struct diag_pkt_header_t *pkt_header, unsigned char *req_buf, int req_len, - int tag, int pkt_header_len) + int tag) { uint8_t cmd_code, subsys_id, i, goto_download = 0; uint8_t header_len = sizeof(struct diag_dci_pkt_header_t); @@ -1825,16 +1810,12 @@ static int diag_dci_process_apps_pkt(struct diag_pkt_header_t *pkt_header, unsigned char *payload_ptr = driver->apps_dci_buf + header_len; struct diag_dci_pkt_header_t dci_header; - if (!pkt_header || !req_buf || req_len <= 0 || tag < 0 || - pkt_header_len <= 0) + if (!pkt_header || !req_buf || req_len <= 0 || tag < 0) return -EIO; - if (pkt_header_len >= (sizeof(uint8_t))) - cmd_code = pkt_header->cmd_code; - if (pkt_header_len >= (2 * sizeof(uint8_t))) - subsys_id = pkt_header->subsys_id; - if (pkt_header_len >= (3 * sizeof(uint8_t))) - ss_cmd_code = pkt_header->subsys_cmd_code; + cmd_code = pkt_header->cmd_code; + subsys_id = pkt_header->subsys_id; + ss_cmd_code = pkt_header->subsys_cmd_code; if (cmd_code == DIAG_CMD_DOWNLOAD) { *payload_ptr = DIAG_CMD_DOWNLOAD; @@ -1955,7 +1936,7 @@ static int diag_dci_process_apps_pkt(struct diag_pkt_header_t *pkt_header, static int diag_process_dci_pkt_rsp(unsigned char *buf, int len) { int ret = DIAG_DCI_TABLE_ERR; - int common_cmd = 0, header_len = 0; + int common_cmd = 0; struct diag_pkt_header_t *header = NULL; unsigned char *temp = buf; unsigned char *req_buf = NULL; @@ -1971,7 +1952,8 @@ static int diag_process_dci_pkt_rsp(unsigned char *buf, int len) if (!buf) return -EIO; - if (len < sizeof(struct dci_pkt_req_t) || + if (len < (sizeof(struct dci_pkt_req_t) + + sizeof(struct diag_pkt_header_t)) || len > DCI_REQ_BUF_SIZE) { pr_err("diag: dci: Invalid length %d len in %s", len, __func__); return -EIO; @@ -1982,6 +1964,13 @@ static int diag_process_dci_pkt_rsp(unsigned char *buf, int len) read_len += sizeof(struct dci_pkt_req_t); req_len -= sizeof(struct dci_pkt_req_t); req_buf = temp; /* Start of the Request */ + header = (struct diag_pkt_header_t *)temp; + read_len += sizeof(struct diag_pkt_header_t); + if (read_len >= DCI_REQ_BUF_SIZE) { + pr_err("diag: dci: In %s, invalid read_len: %d\n", __func__, + read_len); + return -EIO; + } mutex_lock(&driver->dci_mutex); dci_entry = diag_dci_get_client_entry(req_hdr.client_id); @@ -1992,40 +1981,11 @@ static int diag_process_dci_pkt_rsp(unsigned char *buf, int len) return DIAG_DCI_NO_REG; } - header = (void *)temp; - header_len = len - sizeof(struct dci_pkt_req_t); - if (header_len <= 0) { - mutex_unlock(&driver->dci_mutex); - return -EIO; - } - if (header_len >= sizeof(uint8_t)) { - header->cmd_code = (uint16_t)(*(uint8_t *)temp); - read_len += sizeof(uint8_t); - } - if (header_len >= (2 * sizeof(uint8_t))) { - temp += sizeof(uint8_t); - header->subsys_id = (uint16_t)(*(uint8_t *)temp); - read_len += sizeof(uint8_t); - } - if (header_len == (3 * sizeof(uint8_t))) { - temp += sizeof(uint8_t); - header->subsys_cmd_code = (uint16_t)(*(uint8_t *)temp); - read_len += sizeof(uint8_t); - } else if (header_len >= - (2 * sizeof(uint8_t)) + sizeof(uint16_t)) { - temp += sizeof(uint8_t); - header->subsys_cmd_code = (uint16_t)(*(uint16_t *)temp); - read_len += sizeof(uint16_t); - } - if (read_len > DCI_REQ_BUF_SIZE) { - pr_err("diag: dci: In %s, invalid read_len: %d\n", __func__, - read_len); - mutex_unlock(&driver->dci_mutex); - return -EIO; - } - /* Check if the command is allowed on DCI */ - if (diag_dci_filter_commands(header, header_len)) { + if (diag_dci_filter_commands(header)) { + pr_debug("diag: command not supported %d %d %d", + header->cmd_code, header->subsys_id, + header->subsys_cmd_code); mutex_unlock(&driver->dci_mutex); return DIAG_DCI_SEND_DATA_FAIL; } @@ -2079,23 +2039,14 @@ static int diag_process_dci_pkt_rsp(unsigned char *buf, int len) /* Check if it is a dedicated Apps command */ ret = diag_dci_process_apps_pkt(header, req_buf, req_len, - req_entry->tag, header_len); + req_entry->tag); if ((ret == DIAG_DCI_NO_ERROR && !common_cmd) || ret < 0) return ret; - reg_entry.cmd_code = 0; - reg_entry.subsys_id = 0; - reg_entry.cmd_code_hi = 0; - reg_entry.cmd_code_lo = 0; - - if (header_len >= (sizeof(uint8_t))) - reg_entry.cmd_code = header->cmd_code; - if (header_len >= (2 * sizeof(uint8_t))) - reg_entry.subsys_id = header->subsys_id; - if (header_len >= (3 * sizeof(uint8_t))) { - reg_entry.cmd_code_hi = header->subsys_cmd_code; - reg_entry.cmd_code_lo = header->subsys_cmd_code; - } + reg_entry.cmd_code = header->cmd_code; + reg_entry.subsys_id = header->subsys_id; + reg_entry.cmd_code_hi = header->subsys_cmd_code; + reg_entry.cmd_code_lo = header->subsys_cmd_code; mutex_lock(&driver->cmd_reg_mutex); temp_entry = diag_cmd_search(®_entry, ALL_PROC); diff --git a/drivers/char/diag/diag_debugfs.c b/drivers/char/diag/diag_debugfs.c index 73b7f194b984f96e03fcbce3393f045a69d79df3..1cbfb97f9a215cdcd49ff601de667d7340e9301e 100644 --- a/drivers/char/diag/diag_debugfs.c +++ b/drivers/char/diag/diag_debugfs.c @@ -553,7 +553,7 @@ static ssize_t diag_dbgfs_read_socketinfo(struct file *file, char __user *ubuf, struct diag_socket_info *info = NULL; struct diagfwd_info *fwd_ctxt = NULL; - if (diag_dbgfs_socketinfo_index >= NUM_TYPES) { + if (diag_dbgfs_socketinfo_index >= NUM_PERIPHERALS) { /* Done. Reset to prepare for future requests */ diag_dbgfs_socketinfo_index = 0; return 0; @@ -659,7 +659,7 @@ static ssize_t diag_dbgfs_read_rpmsginfo(struct file *file, char __user *ubuf, struct diag_rpmsg_info *info = NULL; struct diagfwd_info *fwd_ctxt = NULL; - if (diag_dbgfs_rpmsginfo_index >= NUM_TYPES) { + if (diag_dbgfs_rpmsginfo_index >= NUM_PERIPHERALS) { /* Done. Reset to prepare for future requests */ diag_dbgfs_rpmsginfo_index = 0; return 0; @@ -697,7 +697,7 @@ static ssize_t diag_dbgfs_read_rpmsginfo(struct file *file, char __user *ubuf, bytes_written = scnprintf(buf+bytes_in_buffer, bytes_remaining, - "name\t\t:\t%s:\t%s\n" + "name\t\t:\t%s\n" "hdl\t\t:\t%pK\n" "inited\t\t:\t%d\n" "opened\t\t:\t%d\n" @@ -712,7 +712,6 @@ static ssize_t diag_dbgfs_read_rpmsginfo(struct file *file, char __user *ubuf, "fwd inited\t:\t%d\n" "fwd opened\t:\t%d\n" "fwd ch_open\t:\t%d\n\n", - info->edge, info->name, info->hdl, info->inited, @@ -794,7 +793,7 @@ static ssize_t diag_dbgfs_read_hsicinfo(struct file *file, char __user *ubuf, unsigned int bytes_in_buffer = 0; struct diag_hsic_info *hsic_info = NULL; - if (diag_dbgfs_hsicinfo_index >= NUM_HSIC_DEV) { + if (diag_dbgfs_hsicinfo_index >= NUM_DIAG_USB_DEV) { /* Done. Reset to prepare for future requests */ diag_dbgfs_hsicinfo_index = 0; return 0; @@ -939,7 +938,7 @@ static ssize_t diag_dbgfs_read_bridge(struct file *file, char __user *ubuf, unsigned int bytes_in_buffer = 0; struct diagfwd_bridge_info *info = NULL; - if (diag_dbgfs_bridgeinfo_index >= NUM_REMOTE_DEV) { + if (diag_dbgfs_bridgeinfo_index >= NUM_DIAG_USB_DEV) { /* Done. Reset to prepare for future requests */ diag_dbgfs_bridgeinfo_index = 0; return 0; diff --git a/drivers/char/diag/diag_masks.c b/drivers/char/diag/diag_masks.c index 362597bceba876754f2a855157e40b2a321adf22..8d24bbba32dd5d804cb321f13199447dacfdc571 100644 --- a/drivers/char/diag/diag_masks.c +++ b/drivers/char/diag/diag_masks.c @@ -1109,7 +1109,7 @@ static int diag_cmd_update_event_mask(unsigned char *src_buf, int src_len, rsp.num_bits = driver->last_event_id + 1; memcpy(dest_buf, &rsp, header_len); write_len += header_len; - memcpy(dest_buf + write_len, src_buf + header_len, mask_len); + memcpy(dest_buf + write_len, mask_info->ptr, mask_len); write_len += mask_len; for (i = 0; i < NUM_MD_SESSIONS; i++) { @@ -1217,9 +1217,10 @@ static int diag_cmd_get_log_mask(unsigned char *src_buf, int src_len, mask_info = (!info) ? &log_mask : info->log_mask; if (!src_buf || !dest_buf || dest_len <= 0 || !mask_info || src_len < sizeof(struct diag_log_config_get_req_t)) { - pr_err("diag: Invalid input in %s, src_buf: %pK, src_len: %d, dest_buf: %pK, dest_len: %d, mask_info: %pK\n", + + pr_err("diag: Invalid input in %s, src_buf: %pK, src_len: %d, dest_buf: %pK, dest_len: %d, mask_info: %pK,structure size %d\n", __func__, src_buf, src_len, dest_buf, dest_len, - mask_info); + mask_info, sizeof(struct diag_log_config_get_req_t)); mutex_unlock(&driver->md_session_lock); return -EINVAL; } diff --git a/drivers/char/diag/diag_memorydevice.c b/drivers/char/diag/diag_memorydevice.c index b44410250420fcc040bfd06b0bbb81521d0fde20..3d2bcf7dc9ddbcd2337a0415e32f382dc947aff2 100644 --- a/drivers/char/diag/diag_memorydevice.c +++ b/drivers/char/diag/diag_memorydevice.c @@ -175,7 +175,7 @@ int diag_md_write(int id, unsigned char *buf, int len, int ctx) { int i, peripheral, pid = 0; uint8_t found = 0; - unsigned long flags, flags_sec; + unsigned long flags; struct diag_md_info *ch = NULL; struct diag_md_session_t *session_info = NULL; @@ -207,16 +207,6 @@ int diag_md_write(int id, unsigned char *buf, int len, int ctx) } spin_lock_irqsave(&ch->lock, flags); - if (peripheral == APPS_DATA) { - spin_lock_irqsave(&driver->diagmem_lock, flags_sec); - if (!hdlc_data.allocated && !non_hdlc_data.allocated) { - spin_unlock_irqrestore(&driver->diagmem_lock, - flags_sec); - spin_unlock_irqrestore(&ch->lock, flags); - mutex_unlock(&driver->md_session_lock); - return -EINVAL; - } - } for (i = 0; i < ch->num_tbl_entries && !found; i++) { if (ch->tbl[i].buf != buf) continue; @@ -228,16 +218,14 @@ int diag_md_write(int id, unsigned char *buf, int len, int ctx) ch->tbl[i].len = 0; ch->tbl[i].ctx = 0; } + spin_unlock_irqrestore(&ch->lock, flags); if (found) { - if (peripheral == APPS_DATA) - spin_unlock_irqrestore(&driver->diagmem_lock, - flags_sec); - spin_unlock_irqrestore(&ch->lock, flags); mutex_unlock(&driver->md_session_lock); return -ENOMEM; } + spin_lock_irqsave(&ch->lock, flags); for (i = 0; i < ch->num_tbl_entries && !found; i++) { if (ch->tbl[i].len == 0) { ch->tbl[i].buf = buf; @@ -247,8 +235,6 @@ int diag_md_write(int id, unsigned char *buf, int len, int ctx) diag_ws_on_read(DIAG_WS_MUX, len); } } - if (peripheral == APPS_DATA) - spin_unlock_irqrestore(&driver->diagmem_lock, flags_sec); spin_unlock_irqrestore(&ch->lock, flags); mutex_unlock(&driver->md_session_lock); diff --git a/drivers/char/diag/diagchar_core.c b/drivers/char/diag/diagchar_core.c index 6aa12b99874f4403f6f348f469d816ab89720d12..52c5027ebeda1e4ed8248315d5eb1cadac138de1 100644 --- a/drivers/char/diag/diagchar_core.c +++ b/drivers/char/diag/diagchar_core.c @@ -457,7 +457,7 @@ static void diag_close_logging_process(const int pid) int i, j; int session_mask = 0; int device_mask = 0; - uint32_t p_mask = 0; + uint32_t p_mask; struct diag_md_session_t *session_info = NULL; struct diag_logging_mode_param_t params; @@ -523,11 +523,9 @@ static void diag_close_logging_process(const int pid) } } } - mutex_lock(&driver->hdlc_disable_mutex); mutex_lock(&driver->md_session_lock); diag_md_session_close(pid); mutex_unlock(&driver->md_session_lock); - mutex_unlock(&driver->hdlc_disable_mutex); diag_switch_logging(¶ms); mutex_unlock(&driver->diagchar_mutex); } @@ -1445,8 +1443,6 @@ static void diag_md_session_close(int pid) driver->md_session_map[proc][i] = NULL; driver->md_session_mask[proc] &= ~session_info->peripheral_mask[proc]; - driver->p_hdlc_disabled[i] = - driver->hdlc_disabled; } } diag_log_mask_free(session_info->log_mask); diff --git a/drivers/char/diag/diagfwd.c b/drivers/char/diag/diagfwd.c index fe9027eaf4787bbea8306d77bb37b7dc1650c373..3b67d3b1fe5ee7347a75034a980e59213e2ac1c0 100644 --- a/drivers/char/diag/diagfwd.c +++ b/drivers/char/diag/diagfwd.c @@ -1025,33 +1025,27 @@ int diag_process_apps_pkt(unsigned char *buf, int len, int pid) } temp = buf; - if (len >= sizeof(uint8_t)) { - entry.cmd_code = (uint16_t)(*(uint8_t *)temp); - DIAG_LOG(DIAG_DEBUG_CMD_INFO, - "diag: received cmd_code %02x\n", entry.cmd_code); - } - if (len >= (2 * sizeof(uint8_t))) { - temp += sizeof(uint8_t); - entry.subsys_id = (uint16_t)(*(uint8_t *)temp); - DIAG_LOG(DIAG_DEBUG_CMD_INFO, - "diag: received subsys_id %02x\n", entry.subsys_id); - } - if (len == (3 * sizeof(uint8_t))) { - temp += sizeof(uint8_t); - entry.cmd_code_hi = (uint16_t)(*(uint8_t *)temp); - entry.cmd_code_lo = (uint16_t)(*(uint8_t *)temp); - DIAG_LOG(DIAG_DEBUG_CMD_INFO, - "diag: received cmd_code_hi %02x\n", entry.cmd_code_hi); - } else if (len >= (2 * sizeof(uint8_t)) + sizeof(uint16_t)) { - temp += sizeof(uint8_t); - entry.cmd_code_hi = (uint16_t)(*(uint16_t *)temp); - entry.cmd_code_lo = (uint16_t)(*(uint16_t *)temp); - DIAG_LOG(DIAG_DEBUG_CMD_INFO, - "diag: received cmd_code_hi %02x\n", entry.cmd_code_hi); - } - - if ((len >= sizeof(uint8_t)) && *buf == DIAG_CMD_LOG_ON_DMND && - driver->log_on_demand_support && + + entry.cmd_code = (uint16_t)(*(uint8_t *)temp); + temp += sizeof(uint8_t); + entry.subsys_id = (uint16_t)(*(uint8_t *)temp); + temp += sizeof(uint8_t); + entry.cmd_code_hi = (uint16_t)(*(uint16_t *)temp); + entry.cmd_code_lo = (uint16_t)(*(uint16_t *)temp); + temp += sizeof(uint16_t); + + + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "diag: In %s, received cmd %02x %02x %04x\n", __func__, + entry.cmd_code, entry.subsys_id, entry.cmd_code_hi); + if (entry.cmd_code == 0x4b && + entry.subsys_id == 0x25 && + entry.cmd_code_hi == 0x0003) { + pr_err("trigger a modem crash by diag command\n"); + dump_stack(); + } + + if (*buf == DIAG_CMD_LOG_ON_DMND && driver->log_on_demand_support && driver->feature[PERIPHERAL_MODEM].rcvd_feature_mask) { write_len = diag_cmd_log_on_demand(buf, len, driver->apps_rsp_buf, @@ -1862,9 +1856,6 @@ static int diagfwd_mux_write_done(unsigned char *buf, int len, int buf_ctxt, DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "No apps data buffer is allocated to be freed\n"); if (temp) { - DIAG_LOG(DIAG_DEBUG_PERIPHERALS, - "Freeing Apps data buffer after write done hdlc.allocated: %d, non_hdlc.allocated: %d\n", - hdlc_data.allocated, non_hdlc_data.allocated); diagmem_free(driver, temp->buf, POOL_TYPE_HDLC); temp->buf = NULL; temp->len = 0; diff --git a/drivers/char/misc.c b/drivers/char/misc.c index 1bb9e7cc82e306a34c970540e58301d0ca2a60ac..b4c4312ab6d2eb072f410853df6fdaa44b2aa697 100644 --- a/drivers/char/misc.c +++ b/drivers/char/misc.c @@ -60,7 +60,7 @@ static DEFINE_MUTEX(misc_mtx); /* * Assigned numbers, used for dynamic minors */ -#define DYNAMIC_MINORS 64 /* like dynamic majors */ +#define DYNAMIC_MINORS 128 /* like dynamic majors */ static DECLARE_BITMAP(misc_minors, DYNAMIC_MINORS); #ifdef CONFIG_PROC_FS diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index c85f6e18cd256ef8b74f2ba9d42f7a3f38f23c41..61ffeb6136c58d701ab29ad322aa6f9909b10ef9 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -568,56 +568,3 @@ config VIRTIO_CLK depends on VIRTIO ---help--- This is the virtual clock driver for virtio. - -config SM_GCC_ATOLL - tristate "ATOLL Global Clock Controller" - depends on COMMON_CLK_QCOM - select QCOM_GDSC - help - Support for the global clock controller on Qualcomm Technologies, Inc - ATOLL devices. - Say Y if you want to use peripheral devices such as UART, SPI, I2C, - USB, UFS, SD/eMMC, PCIe, etc. - -config SM_CAMCC_ATOLL - tristate "ATOLL Camera Clock Controller" - depends on COMMON_CLK_QCOM - help - Support for the camera clock controller on Qualcomm Technologies, Inc - ATOLL devices. - Say Y if you want to support camera devices and functionality such as - capturing pictures. - -config SM_VIDEOCC_ATOLL - tristate "ATOLL Video Clock Controller" - depends on COMMON_CLK_QCOM - help - Support for the video clock controller on Qualcomm Technologies, Inc. - ATOLL devices. - Say Y if you want to support video devices and functionality such as - video encode/decode. - -config SM_DISPCC_ATOLL - tristate "ATOLL Display Clock Controller" - depends on COMMON_CLK_QCOM - help - Support for the display clock controller on Qualcomm Technologies, Inc - ATOLL devices. - Say Y if you want to support display devices and functionality such as - splash screen. - -config SM_NPUCC_ATOLL - tristate "ATOLL NPU Clock Controller" - depends on COMMON_CLK_QCOM - help - Support for the NPU clock controller on Qualcomm Technologies, Inc - ATOLL devices. - Say Y if you want to enable use of the Network Processing Unit. - -config SM_DEBUGCC_ATOLL - tristate "ATOLL Debug Clock Controller" - depends on COMMON_CLK_QCOM - help - Support for the debug clock controller on Qualcomm Technologies, Inc - ATOLL devices. - Say Y if you want to support the clock measurement functionality. diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 84f42e13f73f73327ef40b2ea411ff291bf0673e..157a9f7e2cbbf328de2bdd7785c40b92f6642fdf 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -72,16 +72,10 @@ obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o obj-$(CONFIG_QCOM_CLK_VIRT) += clk-virt.o clk-virt-sm8150.o clk-virt-sm6150.o obj-$(CONFIG_QCS_CMN_BLK_PLL) += cmn-blk-pll.o -obj-$(CONFIG_SM_CAMCC_ATOLL) += camcc-atoll.o -obj-$(CONFIG_SM_DEBUGCC_ATOLL) += debugcc-atoll.o obj-$(CONFIG_SM_DEBUGCC_TRINKET) += debugcc-trinket.o -obj-$(CONFIG_SM_DISPCC_ATOLL) += dispcc-atoll.o obj-$(CONFIG_SM_DISPCC_TRINKET) += dispcc-trinket.o -obj-$(CONFIG_SM_GCC_ATOLL) += gcc-atoll.o obj-$(CONFIG_SM_GCC_TRINKET) += gcc-trinket.o obj-$(CONFIG_SM_GPUCC_TRINKET) += gpucc-trinket.o -obj-$(CONFIG_SM_NPUCC_ATOLL) += npucc-atoll.o -obj-$(CONFIG_SM_VIDEOCC_ATOLL) += videocc-atoll.o obj-$(CONFIG_SM_VIDEOCC_TRINKET) += videocc-trinket.o obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o obj-$(CONFIG_VIRTIO_CLK) += virtio_clk.o virtio_clk_sm8150.o virtio_clk_sm6150.o virtio_clk_sa8195p.o diff --git a/drivers/clk/qcom/clk-cpu-osm.c b/drivers/clk/qcom/clk-cpu-osm.c index a397013479f1b4af9ea85d9d5d8597e2b261903e..8d49a370ce99a41c4ae77fd0836a46b7ca0c8013 100644 --- a/drivers/clk/qcom/clk-cpu-osm.c +++ b/drivers/clk/qcom/clk-cpu-osm.c @@ -89,7 +89,6 @@ static bool is_sdmshrike; static bool is_sm6150; static bool is_sdmmagpie; static bool is_trinket; -static bool is_atoll; static inline struct clk_osm *to_clk_osm(struct clk_hw *_hw) { @@ -1032,8 +1031,7 @@ static int clk_osm_resources_init(struct platform_device *pdev) return -ENOMEM; } - if (is_sdmshrike || is_sm6150 || is_sdmmagpie || - is_trinket || is_atoll) + if (is_sdmshrike || is_sm6150 || is_sdmmagpie || is_trinket) return 0; res = platform_get_resource_byname(pdev, IORESOURCE_MEM, @@ -1126,13 +1124,9 @@ static int clk_cpu_osm_driver_probe(struct platform_device *pdev) is_sdmshrike = of_device_is_compatible(pdev->dev.of_node, "qcom,clk-cpu-osm-sdmshrike"); - - is_atoll = of_device_is_compatible(pdev->dev.of_node, - "qcom,clk-cpu-osm-atoll"); - if (is_sdmshrike) clk_cpu_osm_driver_sdmshrike_fixup(); - else if (is_sm6150 || is_sdmmagpie || is_atoll) + else if (is_sm6150 || is_sdmmagpie) clk_cpu_osm_driver_sm6150_fixup(); else if (is_trinket) clk_cpu_osm_driver_trinket_fixup(); @@ -1189,8 +1183,7 @@ static int clk_cpu_osm_driver_probe(struct platform_device *pdev) return rc; } - if (!is_sdmshrike && !is_sm6150 && !is_sdmmagpie && - !is_trinket && !is_atoll) { + if (!is_sdmshrike && !is_sm6150 && !is_sdmmagpie && !is_trinket) { rc = clk_osm_read_lut(pdev, &perfpcl_clk); if (rc) { dev_err(&pdev->dev, "Unable to read OSM LUT for perf plus cluster, rc=%d\n", @@ -1272,7 +1265,6 @@ static const struct of_device_id match_table[] = { { .compatible = "qcom,clk-cpu-osm-sdmmagpie" }, { .compatible = "qcom,clk-cpu-osm-trinket" }, { .compatible = "qcom,clk-cpu-osm-sdmshrike" }, - { .compatible = "qcom,clk-cpu-osm-atoll" }, {} }; diff --git a/drivers/clk/qcom/clk-debug.c b/drivers/clk/qcom/clk-debug.c index 4cc851ed438a057c2871c85d7c704d35b0348a0b..1a2155c821f00c831565afe5d047ed664a28276a 100644 --- a/drivers/clk/qcom/clk-debug.c +++ b/drivers/clk/qcom/clk-debug.c @@ -307,6 +307,19 @@ static int clk_debug_measure_get(void *data, u64 *val) DEFINE_SIMPLE_ATTRIBUTE(clk_measure_fops, clk_debug_measure_get, NULL, "%lld\n"); +// tedlin@ASTI, 2019/06/12 add for ddrfreq query +void clk_get_ddr_freq(u64* val) +{ + struct clk_debug_mux *meas = to_clk_measure(measure); + u32 regval; + *val = 0; + if (likely(meas)) { + regmap_read(meas->regmap[7], 80, ®val); + *val = 1000000000000UL; + do_div(*val, regval); + } +} + static int clk_debug_read_period(void *data, u64 *val) { struct clk_hw *hw = data; diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index b7e69b449d809c4d3ff8639ca871bd821d8cb6c1..97d761daf08e0170a99bec8f0db6095b9c9176a4 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -522,7 +522,6 @@ static const struct of_device_id clk_rpmh_match_table[] = { { .compatible = "qcom,rpmh-clk-sdmmagpie", .data = &clk_rpmh_sm6150}, { .compatible = "qcom,rpmh-clk-sdxprairie", .data = &clk_rpmh_sdxprairie}, - { .compatible = "qcom,rpmh-clk-atoll", .data = &clk_rpmh_sm6150}, { } }; MODULE_DEVICE_TABLE(of, clk_rpmh_match_table); diff --git a/drivers/clk/qcom/gcc-sdmshrike.c b/drivers/clk/qcom/gcc-sdmshrike.c index ec5cd2cd6266b335923e6fb69012258f85cc9484..1d42142095fc18d5b6cb278283113c27f7b9a902 100644 --- a/drivers/clk/qcom/gcc-sdmshrike.c +++ b/drivers/clk/qcom/gcc-sdmshrike.c @@ -5051,8 +5051,6 @@ static const struct qcom_reset_map gcc_sdmshrike_resets[] = { [GCC_USB30_SEC_BCR] = { 0x10000 }, [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, [GCC_VIDEO_AXIC_CLK_BCR] = { 0xb02c, 2 }, - [GCC_VIDEO_AXI0_CLK_BCR] = { 0xb024, 2 }, - [GCC_VIDEO_AXI1_CLK_BCR] = { 0xb028, 2 }, }; diff --git a/drivers/clk/qcom/gpucc-sdmmagpie.c b/drivers/clk/qcom/gpucc-sdmmagpie.c index 0c48b27022dcaf00ad1dd69d874106a5c885293c..0d814dc0bd81a9fe03fa3b231faf090c4be7df1f 100644 --- a/drivers/clk/qcom/gpucc-sdmmagpie.c +++ b/drivers/clk/qcom/gpucc-sdmmagpie.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -578,7 +578,6 @@ static const struct qcom_cc_desc gpu_cc_sdmmagpie_desc = { static const struct of_device_id gpu_cc_sdmmagpie_match_table[] = { { .compatible = "qcom,gpucc-sdmmagpie" }, - { .compatible = "qcom,atoll-gpucc" }, { } }; MODULE_DEVICE_TABLE(of, gpu_cc_sdmmagpie_match_table); diff --git a/drivers/clk/qcom/mdss/mdss-pll-util.c b/drivers/clk/qcom/mdss/mdss-pll-util.c index 3e60d93f08f495575e259c4b26d456369d923cb3..4d797729bb75e08d4dd82a5e7076cf12ea11906a 100644 --- a/drivers/clk/qcom/mdss/mdss-pll-util.c +++ b/drivers/clk/qcom/mdss/mdss-pll-util.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. +/* Copyright (c) 2013-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -337,7 +337,7 @@ static void mdss_pll_free_bootmem(u32 mem_addr, u32 size) free_reserved_page(pfn_to_page(pfn_idx)); } -static int mdss_pll_util_parse_dt_dfps_sub(struct platform_device *pdev, +static int mdss_pll_util_parse_dt_dfps(struct platform_device *pdev, struct mdss_pll_resources *pll_res) { int rc = 0; @@ -424,6 +424,9 @@ int mdss_pll_util_resource_parse(struct platform_device *pdev, goto clk_err; } + if (mdss_pll_util_parse_dt_dfps(pdev, pll_res)) + pr_err("dfps not enabled!\n"); + return rc; clk_err: @@ -432,13 +435,3 @@ int mdss_pll_util_resource_parse(struct platform_device *pdev, end: return rc; } - -void mdss_pll_util_parse_dt_dfps(struct platform_device *pdev, - struct mdss_pll_resources *pll_res) -{ - int rc = 0; - - rc = mdss_pll_util_parse_dt_dfps_sub(pdev, pll_res); - if (rc) - pr_err("dfps not enabled!\n"); -} diff --git a/drivers/clk/qcom/mdss/mdss-pll.c b/drivers/clk/qcom/mdss/mdss-pll.c index 7c4d0446a5d16f69412a51bebc718d751ea78506..d07f5c262b1713f463885ebae54526008b72751d 100644 --- a/drivers/clk/qcom/mdss/mdss-pll.c +++ b/drivers/clk/qcom/mdss/mdss-pll.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. +/* Copyright (c) 2013-2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -366,8 +366,6 @@ static int mdss_pll_probe(struct platform_device *pdev) goto clock_register_error; } - mdss_pll_util_parse_dt_dfps(pdev, pll_res); - return rc; clock_register_error: diff --git a/drivers/clk/qcom/mdss/mdss-pll.h b/drivers/clk/qcom/mdss/mdss-pll.h index dc3a66dd07943d20f75d84cd503548955a131af4..397229d3c5c85ba5ed2289bd6a82abb777c464de 100644 --- a/drivers/clk/qcom/mdss/mdss-pll.h +++ b/drivers/clk/qcom/mdss/mdss-pll.h @@ -251,8 +251,6 @@ int mdss_pll_util_resource_enable(struct mdss_pll_resources *pll_res, bool enable); int mdss_pll_util_resource_parse(struct platform_device *pdev, struct mdss_pll_resources *pll_res); -void mdss_pll_util_parse_dt_dfps(struct platform_device *pdev, - struct mdss_pll_resources *pll_res); struct dss_vreg *mdss_pll_get_mp_by_reg_name(struct mdss_pll_resources *pll_res , char *name); #endif diff --git a/drivers/clk/qcom/scc-sm8150.c b/drivers/clk/qcom/scc-sm8150.c index 554d5590eabac98b746813636b4a7c3d43ae66ef..9cf33169f26864e8a3963c46050bfc42171a8dd6 100644 --- a/drivers/clk/qcom/scc-sm8150.c +++ b/drivers/clk/qcom/scc-sm8150.c @@ -576,19 +576,10 @@ static const struct qcom_cc_desc scc_sm8150_desc = { static const struct of_device_id scc_sm8150_match_table[] = { { .compatible = "qcom,scc-sm8150" }, { .compatible = "qcom,scc-sm8150-v2" }, - { .compatible = "qcom,scc-sa8195" }, { } }; MODULE_DEVICE_TABLE(of, scc_sm8150_match_table); -static void scc_sa8195_fixup(struct platform_device *pdev) -{ - if (of_device_is_compatible(pdev->dev.of_node, "qcom,scc-sa8195")) { - vdd_scc_cx.num_levels = VDD_MM_NUM; - vdd_scc_cx.cur_level = VDD_MM_NUM; - } -} - static void scc_sm8150_fixup_sm8150v2(struct regmap *regmap) { scc_pll.config = &scc_pll_config_sm8150_v2; @@ -644,8 +635,7 @@ static int scc_sm8150_fixup(struct platform_device *pdev, struct regmap *regmap) if (!compat || (compatlen <= 0)) return -EINVAL; - if (!strcmp(compat, "qcom,scc-sm8150-v2") || - !strcmp(compat, "qcom,scc-sa8195")) + if (!strcmp(compat, "qcom,scc-sm8150-v2")) scc_sm8150_fixup_sm8150v2(regmap); return 0; @@ -662,8 +652,6 @@ static int scc_sm8150_probe(struct platform_device *pdev) return PTR_ERR(regmap); } - scc_sa8195_fixup(pdev); - vdd_scc_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_scc_cx"); if (IS_ERR(vdd_scc_cx.regulator[0])) { ret = PTR_ERR(vdd_scc_cx.regulator[0]); diff --git a/drivers/clk/qcom/virtio_clk.c b/drivers/clk/qcom/virtio_clk.c index 3630755e5bcb6cb1356f182bc54ddba02354accb..ea1c6fc1835bbbf3c54310e0dec994c43ec20b0a 100644 --- a/drivers/clk/qcom/virtio_clk.c +++ b/drivers/clk/qcom/virtio_clk.c @@ -718,7 +718,7 @@ static void __exit virtio_clk_fini(void) { unregister_virtio_driver(&virtio_clk_driver); } -subsys_initcall_sync(virtio_clk_init); +subsys_initcall(virtio_clk_init); module_exit(virtio_clk_fini); MODULE_DEVICE_TABLE(virtio, id_table); diff --git a/drivers/clk/qcom/virtio_clk_sa8195p.c b/drivers/clk/qcom/virtio_clk_sa8195p.c index 90c07bf8f7cae16a7bd51c3ea319ffe9bdb18145..2be46624a73da5da66339a2d327d8da70283eac2 100644 --- a/drivers/clk/qcom/virtio_clk_sa8195p.c +++ b/drivers/clk/qcom/virtio_clk_sa8195p.c @@ -45,26 +45,11 @@ static const char * const sa8195p_gcc_virtio_clocks[] = { [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = "gcc_cfg_noc_usb3_prim_axi_clk", [GCC_AGGRE_USB3_PRIM_AXI_CLK] = "gcc_aggre_usb3_prim_axi_clk", [GCC_USB30_PRIM_MOCK_UTMI_CLK] = "gcc_usb30_prim_mock_utmi_clk", - [GCC_USB30_PRIM_SLEEP_CLK] = "gcc_usb30_prim_sleep_clk", - [GCC_USB3_PRIM_PHY_AUX_CLK] = "gcc_usb3_prim_phy_aux_clk", - [GCC_USB3_PRIM_PHY_PIPE_CLK] = "gcc_usb3_prim_phy_pipe_clk", - [GCC_USB3_PRIM_CLKREF_CLK] = "gcc_usb3_prim_clkref_en", - [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = "gcc_usb3_prim_phy_com_aux_clk", - [GCC_USB30_SEC_MASTER_CLK] = "gcc_usb30_sec_master_clk", - [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = "gcc_cfg_noc_usb3_sec_axi_clk", - [GCC_AGGRE_USB3_SEC_AXI_CLK] = "gcc_aggre_usb3_sec_axi_clk", - [GCC_USB30_SEC_MOCK_UTMI_CLK] = "gcc_usb30_sec_mock_utmi_clk", - [GCC_USB30_SEC_SLEEP_CLK] = "gcc_usb30_sec_sleep_clk", - [GCC_USB3_SEC_PHY_AUX_CLK] = "gcc_usb3_sec_phy_aux_clk", - [GCC_USB3_SEC_PHY_PIPE_CLK] = "gcc_usb3_sec_phy_pipe_clk", - [GCC_USB3_SEC_CLKREF_CLK] = "gcc_usb3_sec_clkref_en", - [GCC_USB3_SEC_PHY_COM_AUX_CLK] = "gcc_usb3_sec_phy_com_aux_clk", [GCC_PCIE_0_PIPE_CLK] = "gcc_pcie_0_pipe_clk", [GCC_PCIE_0_AUX_CLK] = "gcc_pcie_0_aux_clk", [GCC_PCIE_0_CFG_AHB_CLK] = "gcc_pcie_0_cfg_ahb_clk", [GCC_PCIE_0_MSTR_AXI_CLK] = "gcc_pcie_0_mstr_axi_clk", [GCC_PCIE_0_SLV_AXI_CLK] = "gcc_pcie_0_slv_axi_clk", - [GCC_PCIE_0_CLKREF_CLK] = "gcc_pcie_0_clkref_en", [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = "gcc_pcie_0_slv_q2a_axi_clk", [GCC_AGGRE_NOC_PCIE_TBU_CLK] = "gcc_aggre_noc_pcie_tbu_clk", [GCC_PCIE0_PHY_REFGEN_CLK] = "gcc_pcie0_phy_refgen_clk", @@ -75,9 +60,7 @@ static const char * const sa8195p_gcc_virtio_clocks[] = { static const char * const sa8195p_gcc_virtio_resets[] = { [GCC_QUSB2PHY_PRIM_BCR] = "gcc_qusb2phy_prim_bcr", - [GCC_QUSB2PHY_SEC_BCR] = "gcc_qusb2phy_sec_bcr", [GCC_USB30_PRIM_BCR] = "gcc_usb30_prim_master_clk", - [GCC_USB30_SEC_BCR] = "gcc_usb30_sec_master_clk", [GCC_PCIE_0_BCR] = "gcc_pcie_0_mstr_axi_clk", [GCC_PCIE_0_PHY_BCR] = "gcc_pcie_0_phy_bcr", }; diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 9e653f0bfa6c9747e01b09e6afc9a03c591bd84d..dd9614496f536e0558e5842cd6551208b6517022 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -301,13 +301,6 @@ static u64 notrace arm64_858921_read_cntvct_el0(void) } #endif -#ifdef CONFIG_ARM64_ERRATUM_1188873 -static u64 notrace arm64_1188873_read_cntvct_el0(void) -{ - return read_sysreg(cntvct_el0); -} -#endif - #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *, timer_unstable_counter_workaround); @@ -391,14 +384,6 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = { .read_cntvct_el0 = arm64_858921_read_cntvct_el0, }, #endif -#ifdef CONFIG_ARM64_ERRATUM_1188873 - { - .match_type = ate_match_local_cap_id, - .id = (void *)ARM64_WORKAROUND_1188873, - .desc = "ARM erratum 1188873", - .read_cntvct_el0 = arm64_1188873_read_cntvct_el0, - }, -#endif }; typedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *, diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c index 4c57bff0fe95fadfa9c7cd916a5c684045916711..a8e9fb2c1e2031450b810711f978d79f4bd2ab00 100644 --- a/drivers/cpufreq/cpufreq.c +++ b/drivers/cpufreq/cpufreq.c @@ -33,7 +33,10 @@ #include #include +#include #include +#define GOLD_CPU_NUMBER 4 +#define GOLD_PLUS_CPU_NUMBER 7 static LIST_HEAD(cpufreq_policy_list); @@ -60,6 +63,29 @@ static LIST_HEAD(cpufreq_governor_list); #define for_each_governor(__governor) \ list_for_each_entry(__governor, &cpufreq_governor_list, governor_list) +struct qos_request_value { + bool flag; + unsigned int max_cpufreq; + unsigned int min_cpufreq; +}; +static struct qos_request_value c0_qos_request_value = { + .flag = false, + .max_cpufreq = INT_MAX, + .min_cpufreq = MIN_CPUFREQ, +}; +static struct qos_request_value c1_qos_request_value = { + .flag = false, + .max_cpufreq = INT_MAX, + .min_cpufreq = MIN_CPUFREQ, +}; +static struct qos_request_value c2_qos_request_value = { + .flag = false, + .max_cpufreq = INT_MAX, + .min_cpufreq = MIN_CPUFREQ, +}; +unsigned int cluster1_first_cpu = GOLD_CPU_NUMBER; +unsigned int cluster2_first_cpu = GOLD_PLUS_CPU_NUMBER; + /** * The "cpufreq driver" - the arch- or hardware-dependent low * level driver of CPUFreq support, and its spinlock. This lock @@ -342,8 +368,11 @@ static void __cpufreq_notify_transition(struct cpufreq_policy *policy, pr_debug("FREQ: %lu - CPU: %lu\n", (unsigned long)freqs->new, (unsigned long)freqs->cpu); trace_cpu_frequency(freqs->new, freqs->cpu); - cpufreq_stats_record_transition(policy, freqs->new); + + if (freqs->new != policy->cur) + cpufreq_stats_record_transition(policy, freqs->new); cpufreq_times_record_transition(policy, freqs->new); + srcu_notifier_call_chain(&cpufreq_transition_notifier_list, CPUFREQ_POSTCHANGE, freqs); if (likely(policy) && likely(policy->cpu == freqs->cpu)) @@ -1145,6 +1174,10 @@ static struct cpufreq_policy *cpufreq_policy_alloc(unsigned int cpu) INIT_LIST_HEAD(&policy->policy_list); init_rwsem(&policy->rwsem); spin_lock_init(&policy->transition_lock); +// tedlin@ASTI 2019/06/12 add for CONFIG_CONTROL_CENTER +#ifdef CONFIG_CONTROL_CENTER + spin_lock_init(&policy->cc_lock); +#endif init_waitqueue_head(&policy->transition_wait); init_completion(&policy->kobj_unregister); INIT_WORK(&policy->update, handle_update); @@ -1271,6 +1304,13 @@ static int cpufreq_online(unsigned int cpu) } else { policy->min = policy->user_policy.min; policy->max = policy->user_policy.max; +// tedlin@ASTI 2019/06/12 add for CONFIG_CONTROL_CENTER +#ifdef CONFIG_CONTROL_CENTER + spin_lock(&policy->cc_lock); + policy->cc_min = policy->min; + policy->cc_max = policy->max; + spin_unlock(&policy->cc_lock); +#endif } if (cpufreq_driver->get && !cpufreq_driver->setpolicy) { @@ -1891,8 +1931,22 @@ EXPORT_SYMBOL(cpufreq_unregister_notifier); unsigned int cpufreq_driver_fast_switch(struct cpufreq_policy *policy, unsigned int target_freq) { + struct qos_request_value *qos; int ret; + +#ifdef CONFIG_CONTROL_CENTER + if (likely(policy->cc_enable)) + target_freq = clamp_val(target_freq, policy->cc_min, policy->cc_max); +#endif target_freq = clamp_val(target_freq, policy->min, policy->max); + if (policy->cpu >= cluster2_first_cpu) + qos = &c2_qos_request_value; + else { + qos = policy->cpu >= cluster1_first_cpu ? + &c1_qos_request_value : &c0_qos_request_value; + } + target_freq = clamp_val(target_freq, qos->min_cpufreq, + qos->max_cpufreq); ret = cpufreq_driver->fast_switch(policy, target_freq); if (ret) @@ -1995,6 +2049,10 @@ int __cpufreq_driver_target(struct cpufreq_policy *policy, if (cpufreq_disabled()) return -ENODEV; +#ifdef CONFIG_CONTROL_CENTER + if (likely(policy->cc_enable)) + target_freq = clamp_val(target_freq, policy->cc_min, policy->cc_max); +#endif /* Make sure that target_freq is within supported range */ target_freq = clamp_val(target_freq, policy->min, policy->max); @@ -2273,6 +2331,14 @@ static int cpufreq_set_policy(struct cpufreq_policy *policy, policy->min = new_policy->min; policy->max = new_policy->max; +// tedlin@ASTI 2019/06/12 add for CONFIG_CONTROL_CENTER +#ifdef CONFIG_CONTROL_CENTER + spin_lock(&policy->cc_lock); + policy->cc_min = policy->min; + policy->cc_max = policy->max; + spin_unlock(&policy->cc_lock); +#endif + arch_set_max_freq_scale(policy->cpus, policy->max); trace_cpu_frequency_limits(policy->max, policy->min, policy->cpu); @@ -2657,3 +2723,285 @@ static int __init cpufreq_core_init(void) } module_param(off, int, 0444); core_initcall(cpufreq_core_init); + +static int get_c0_available_cpufreq(struct cpufreq_policy *policy) +{ + int max_cpufreq_index = -1, min_cpufreq_index = -1; + int max_index = -1; + int index_max = 0, index_min = 0; + struct cpufreq_frequency_table *table, *pos; + + table = policy->freq_table; + if (!table) { + pr_err("cpufreq:Failed to get frequency table for CPU%u\n", 0); + return -EINVAL; + } + + max_cpufreq_index = (unsigned int)pm_qos_request(PM_QOS_C0_CPUFREQ_MAX); + min_cpufreq_index = (unsigned int)pm_qos_request(PM_QOS_C0_CPUFREQ_MIN); + + /* you can limit the min cpufreq*/ + if (min_cpufreq_index > max_cpufreq_index) + max_cpufreq_index = min_cpufreq_index; + + /* get the available cpufreq + * lock for the max available cpufreq + */ + cpufreq_for_each_valid_entry(pos, table) { + max_index = pos - table; + } + if (max_cpufreq_index & MASK_CPUFREQ) { + index_max = MAX_CPUFREQ - max_cpufreq_index; + if (index_max > max_index) + index_max = 0; + index_max = max_index - index_max; + } else { + if (max_cpufreq_index > max_index) + index_max = max_index; + } + if (min_cpufreq_index & MASK_CPUFREQ) { + index_min = MAX_CPUFREQ - min_cpufreq_index; + if (index_min > max_index) + index_min = 0; + index_min = max_index - index_min; + } else { + if (min_cpufreq_index > max_index) + index_min = max_index; + } + c0_qos_request_value.max_cpufreq = table[index_max].frequency; + c0_qos_request_value.min_cpufreq = table[index_min].frequency; + pr_debug("c0::: m:%d, ii:%d-, mm:%d-", max_index, index_min, index_max); + + return 0; +} + +static int get_c1_available_cpufreq(struct cpufreq_policy *policy) +{ + int max_cpufreq_index = -1, min_cpufreq_index = -1; + int max_index = -1; + int index_max = 0, index_min = 0; + struct cpufreq_frequency_table *table, *pos; + + table = policy->freq_table; + if (!table) { + pr_err("cpufreq: Failed to get frequency table for CPU\n"); + return -EINVAL; + } + + max_cpufreq_index = (unsigned int)pm_qos_request(PM_QOS_C1_CPUFREQ_MAX); + min_cpufreq_index = (unsigned int)pm_qos_request(PM_QOS_C1_CPUFREQ_MIN); + + /* you can limit the min cpufreq*/ + if (min_cpufreq_index > max_cpufreq_index) + max_cpufreq_index = min_cpufreq_index; + + /* get the available cpufreq + * lock for the max available cpufreq + */ + cpufreq_for_each_valid_entry(pos, table) { + max_index = pos - table; + } + + /* add limits */ + if (max_cpufreq_index & MASK_CPUFREQ) { + index_max = MAX_CPUFREQ - max_cpufreq_index; + if (index_max > max_index) + index_max = 0; + index_max = max_index - index_max; + } else { + if (max_cpufreq_index > max_index) + index_max = max_index; + } + if (min_cpufreq_index & MASK_CPUFREQ) { + index_min = MAX_CPUFREQ - min_cpufreq_index; + if (index_min > max_index) + index_min = 0; + index_min = max_index - index_min; + } else { + if (min_cpufreq_index > max_index) + index_min = max_index; + } + c1_qos_request_value.max_cpufreq = table[index_max].frequency; + c1_qos_request_value.min_cpufreq = table[index_min].frequency; + pr_debug("c1::: m:%d, ii:%d-, mm:%d-", max_index, index_min, index_max); + + return 0; +} + +static int get_c2_available_cpufreq(struct cpufreq_policy *policy) +{ + int max_cpufreq_index = -1, min_cpufreq_index = -1; + int max_index = -1; + int index_max = 0, index_min = 0; + struct cpufreq_frequency_table *table, *pos; + + table = policy->freq_table; + if (!table) { + pr_err("cpufreq: Failed to get frequency table for CPU\n"); + return -EINVAL; + } + + max_cpufreq_index = (unsigned int)pm_qos_request(PM_QOS_C2_CPUFREQ_MAX); + min_cpufreq_index = (unsigned int)pm_qos_request(PM_QOS_C2_CPUFREQ_MIN); + + /* you can limit the min cpufreq*/ + if (min_cpufreq_index > max_cpufreq_index) + max_cpufreq_index = min_cpufreq_index; + + /* get the available cpufreq + * lock for the max available cpufreq + */ + cpufreq_for_each_valid_entry(pos, table) { + max_index = pos - table; + } + + /* add limits */ + if (max_cpufreq_index & MASK_CPUFREQ) { + index_max = MAX_CPUFREQ - max_cpufreq_index; + if (index_max > max_index) + index_max = 0; + index_max = max_index - index_max; + } else { + if (max_cpufreq_index > max_index) + index_max = max_index; + } + if (min_cpufreq_index & MASK_CPUFREQ) { + index_min = MAX_CPUFREQ - min_cpufreq_index; + if (index_min > max_index) + index_min = 0; + index_min = max_index - index_min; + } else { + if (min_cpufreq_index > max_index) + index_min = max_index; + } + c2_qos_request_value.max_cpufreq = table[index_max].frequency; + c2_qos_request_value.min_cpufreq = table[index_min].frequency; + pr_debug("c2::: m:%d, ii:%d-, mm:%d-", max_index, index_min, index_max); + + return 0; +} + +static int c0_cpufreq_qos_handler(struct notifier_block *b, + unsigned long val, void *v) +{ + struct cpufreq_policy *policy; + int ret = -1; + + policy = cpufreq_cpu_get(0); + + if (!policy) + return NOTIFY_BAD; + + if (!policy->governor) { + cpufreq_cpu_put(policy); + return NOTIFY_BAD; + } + + if (strcmp(policy->governor->name, "schedutil")) { + cpufreq_cpu_put(policy); + return NOTIFY_OK; + } + + ret = get_c0_available_cpufreq(policy); + if (ret) { + cpufreq_cpu_put(policy); + return NOTIFY_BAD; + } + cpufreq_driver_fast_switch(policy, c0_qos_request_value.min_cpufreq); + + cpufreq_cpu_put(policy); + return NOTIFY_OK; +} + +static struct notifier_block c0_cpufreq_qos_notifier = { + .notifier_call = c0_cpufreq_qos_handler, +}; + +static int c1_cpufreq_qos_handler(struct notifier_block *b, + unsigned long val, void *v) +{ + struct cpufreq_policy *policy; + int ret = -1; + + policy = cpufreq_cpu_get(cluster1_first_cpu); + + if (!policy) + return NOTIFY_BAD; + + if (!policy->governor) { + cpufreq_cpu_put(policy); + return NOTIFY_BAD; + } + + if (strcmp(policy->governor->name, "schedutil")) { + cpufreq_cpu_put(policy); + return NOTIFY_OK; + } + + ret = get_c1_available_cpufreq(policy); + if (ret) { + cpufreq_cpu_put(policy); + return NOTIFY_BAD; + } + + cpufreq_driver_fast_switch(policy, c1_qos_request_value.min_cpufreq); + + cpufreq_cpu_put(policy); + + return NOTIFY_OK; +} + +static struct notifier_block c1_cpufreq_qos_notifier = { + .notifier_call = c1_cpufreq_qos_handler, +}; + +static int c2_cpufreq_qos_handler(struct notifier_block *b, + unsigned long val, void *v) +{ + struct cpufreq_policy *policy; + int ret = -1; + + policy = cpufreq_cpu_get(cluster2_first_cpu); + + if (!policy) + return NOTIFY_BAD; + + if (!policy->governor) { + cpufreq_cpu_put(policy); + return NOTIFY_BAD; + } + + if (strcmp(policy->governor->name, "schedutil")) { + cpufreq_cpu_put(policy); + return NOTIFY_OK; + } + + ret = get_c2_available_cpufreq(policy); + if (ret) { + cpufreq_cpu_put(policy); + return NOTIFY_BAD; + } + + cpufreq_driver_fast_switch(policy, c2_qos_request_value.min_cpufreq); + + cpufreq_cpu_put(policy); + + return NOTIFY_OK; +} + +static struct notifier_block c2_cpufreq_qos_notifier = { + .notifier_call = c2_cpufreq_qos_handler, +}; + +static int __init pm_qos_notifier_init(void) +{ + /* add cpufreq qos notify */ + pm_qos_add_notifier(PM_QOS_C0_CPUFREQ_MAX, &c0_cpufreq_qos_notifier); + pm_qos_add_notifier(PM_QOS_C0_CPUFREQ_MIN, &c0_cpufreq_qos_notifier); + pm_qos_add_notifier(PM_QOS_C1_CPUFREQ_MAX, &c1_cpufreq_qos_notifier); + pm_qos_add_notifier(PM_QOS_C1_CPUFREQ_MIN, &c1_cpufreq_qos_notifier); + pm_qos_add_notifier(PM_QOS_C2_CPUFREQ_MAX, &c2_cpufreq_qos_notifier); + pm_qos_add_notifier(PM_QOS_C2_CPUFREQ_MIN, &c2_cpufreq_qos_notifier); + return 0; +} +subsys_initcall(pm_qos_notifier_init); diff --git a/drivers/cpufreq/cpufreq_performance.c b/drivers/cpufreq/cpufreq_performance.c index dafb679adc589ed533ef6dd02c186fb5ed03f4cc..7f0def1a811830320f968bf46468f01450cba4f2 100644 --- a/drivers/cpufreq/cpufreq_performance.c +++ b/drivers/cpufreq/cpufreq_performance.c @@ -15,11 +15,43 @@ #include #include #include +#include +#define CPUFREQ_INDEX 5 static void cpufreq_gov_performance_limits(struct cpufreq_policy *policy) { + unsigned int index = 0; + unsigned int valid_freq; + struct cpufreq_frequency_table *table, *pos; + static unsigned int first_cpu = 1010; pr_debug("setting to %u kHz\n", policy->max); - __cpufreq_driver_target(policy, policy->max, CPUFREQ_RELATION_H); + if (get_boot_mode() == MSM_BOOT_MODE__WLAN + || (get_boot_mode() == MSM_BOOT_MODE__RF) + || (get_boot_mode() == MSM_BOOT_MODE__FACTORY)) { + if (first_cpu != cpumask_first(policy->related_cpus)) + first_cpu = cpumask_first(policy->related_cpus); + table = policy->freq_table; + if (!table) { + pr_err("Failed to get freqtable\n"); + } else { + for (pos = table; pos->frequency + != CPUFREQ_TABLE_END; pos++) + index++; + if (index > CPUFREQ_INDEX) + index = index - CPUFREQ_INDEX; + valid_freq = table[index].frequency; + if (valid_freq) + __cpufreq_driver_target(policy, + valid_freq, + CPUFREQ_RELATION_H); + else + __cpufreq_driver_target(policy, + policy->max, + CPUFREQ_RELATION_H); + } + } else + __cpufreq_driver_target(policy, policy->max, + CPUFREQ_RELATION_H); } static struct cpufreq_governor cpufreq_gov_performance = { diff --git a/drivers/cpufreq/cpufreq_stats.c b/drivers/cpufreq/cpufreq_stats.c index e75880eb037d3b358b8afcfa80fa5d8b41353610..994e630ed91085033e4e737b927c8fcae24b34a2 100644 --- a/drivers/cpufreq/cpufreq_stats.c +++ b/drivers/cpufreq/cpufreq_stats.c @@ -29,12 +29,13 @@ struct cpufreq_stats { static int cpufreq_stats_update(struct cpufreq_stats *stats) { + unsigned long flags; unsigned long long cur_time = get_jiffies_64(); - spin_lock(&cpufreq_stats_lock); + spin_lock_irqsave(&cpufreq_stats_lock, flags); stats->time_in_state[stats->last_index] += cur_time - stats->last_time; stats->last_time = cur_time; - spin_unlock(&cpufreq_stats_lock); + spin_unlock_irqrestore(&cpufreq_stats_lock, flags); return 0; } @@ -59,8 +60,6 @@ static ssize_t show_time_in_state(struct cpufreq_policy *policy, char *buf) ssize_t len = 0; int i; - if (policy->fast_switch_enabled) - return 0; cpufreq_stats_update(stats); for (i = 0; i < stats->state_num; i++) { @@ -85,8 +84,6 @@ static ssize_t show_trans_table(struct cpufreq_policy *policy, char *buf) ssize_t len = 0; int i, j; - if (policy->fast_switch_enabled) - return 0; len += snprintf(buf + len, PAGE_SIZE - len, " From : To\n"); len += snprintf(buf + len, PAGE_SIZE - len, " : "); @@ -235,7 +232,7 @@ void cpufreq_stats_record_transition(struct cpufreq_policy *policy, new_index = freq_table_get_index(stats, new_freq); /* We can't do stats->time_in_state[-1]= .. */ - if (old_index == -1 || new_index == -1 || old_index == new_index) + if (new_index == -1) return; cpufreq_stats_update(stats); diff --git a/drivers/cpuidle/lpm-levels.c b/drivers/cpuidle/lpm-levels.c index ac2c6f7ea8d0511b2d9b1273782753a749321e25..a570d34e6af055fbb37e6c7e2b215be63822d7bc 100644 --- a/drivers/cpuidle/lpm-levels.c +++ b/drivers/cpuidle/lpm-levels.c @@ -127,6 +127,12 @@ module_param_named(print_parsed_dt, print_parsed_dt, bool, 0664); static bool sleep_disabled; module_param_named(sleep_disabled, sleep_disabled, bool, 0664); +void msm_cpuidle_set_sleep_disable(bool disable) +{ + sleep_disabled = disable; + pr_info("%s:sleep_disabled=%d\n", __func__, disable); +} + /** * msm_cpuidle_get_deep_idle_latency - Get deep idle latency value * diff --git a/drivers/devfreq/arm-memlat-mon.c b/drivers/devfreq/arm-memlat-mon.c index 740dc6f8d04f9d94df9cb037f4e2345414608d27..a80d6c2bebe368708275668e452e26b8297ea487 100644 --- a/drivers/devfreq/arm-memlat-mon.c +++ b/drivers/devfreq/arm-memlat-mon.c @@ -34,6 +34,9 @@ #include #include +// tedlin@ASTI, 2019/06/12 add for CONFIG_HOUSTON +#include + enum ev_index { INST_IDX, CM_IDX, @@ -123,6 +126,10 @@ static void read_perf_counters(int cpu, struct cpu_grp_info *cpu_grp) } else { devstats->stall_pct = 100; } + +// tedlin@ASTI, 2019/06/12 add to update hw events (CONFIG_HOUSTON) + ht_update_hw_events(devstats->inst_count, devstats->mem_count, cyc_cnt); + } static unsigned long get_cnt(struct memlat_hwmon *hw) diff --git a/drivers/devfreq/bimc-bwmon.c b/drivers/devfreq/bimc-bwmon.c index af19be8c6628ad4ed208537238c2119d7c0fb477..698c60000fe80c6d3fdedf8a66289f2e565fb606 100644 --- a/drivers/devfreq/bimc-bwmon.c +++ b/drivers/devfreq/bimc-bwmon.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -28,7 +28,6 @@ #include #include #include -#include #include "governor_bw_hwmon.h" #define GLB_INT_STATUS(m) ((m)->global_base + 0x100) @@ -100,8 +99,6 @@ struct bwmon { void __iomem *global_base; unsigned int mport; int irq; - int nr_clks; - struct clk **clks; const struct bwmon_spec *spec; struct device *dev; struct bw_hwmon hw; @@ -591,16 +588,15 @@ unsigned long get_zone_count(struct bwmon *m, unsigned int zone, WARN(1, "Invalid\n"); return 0; case MON2: - count = readl_relaxed(MON2_ZONE_MAX(m, zone)); + count = readl_relaxed(MON2_ZONE_MAX(m, zone)) + 1; break; case MON3: count = readl_relaxed(MON3_ZONE_MAX(m, zone)); + if (count) + count++; break; } - if (count) - count++; - return count; } @@ -786,27 +782,6 @@ void mon_set_byte_count_filter(struct bwmon *m, enum mon_reg_type type) } } -static __always_inline int mon_clk_enable(struct bwmon *m) -{ - int ret; - int i; - - for (i = 0; i < m->nr_clks; i++) { - ret = clk_prepare_enable(m->clks[i]); - if (ret) { - dev_err(m->dev, "BWMON clk not enabled %d\n", ret); - goto err; - } - } - - return 0; -err: - for (i--; i >= 0; i--) - clk_disable_unprepare(m->clks[i]); - - return ret; -} - static __always_inline int __start_bw_hwmon(struct bw_hwmon *hw, unsigned long mbps, enum mon_reg_type type) { @@ -815,12 +790,6 @@ static __always_inline int __start_bw_hwmon(struct bw_hwmon *hw, int ret; irq_handler_t handler; - ret = mon_clk_enable(m); - if (ret) { - dev_err(m->dev, "Unable to turn on bwmon clks! (%d)\n", ret); - return ret; - } - switch (type) { case MON1: handler = bwmon_intr_handler; @@ -887,14 +856,6 @@ static int start_bw_hwmon3(struct bw_hwmon *hw, unsigned long mbps) return __start_bw_hwmon(hw, mbps, MON3); } -static __always_inline void mon_clk_disable(struct bwmon *m) -{ - int i; - - for (i = m->nr_clks - 1; i >= 0; i--) - clk_disable_unprepare(m->clks[i]); -} - static __always_inline void __stop_bw_hwmon(struct bw_hwmon *hw, enum mon_reg_type type) { @@ -905,7 +866,6 @@ void __stop_bw_hwmon(struct bw_hwmon *hw, enum mon_reg_type type) mon_disable(m, type); mon_clear(m, true, type); mon_irq_clear(m, type); - mon_clk_disable(m); } static void stop_bw_hwmon(struct bw_hwmon *hw) @@ -958,12 +918,6 @@ int __resume_bw_hwmon(struct bw_hwmon *hw, enum mon_reg_type type) int ret; irq_handler_t handler; - ret = mon_clk_enable(m); - if (ret) { - dev_err(m->dev, "Unable to turn on bwmon clks! (%d)\n", ret); - return ret; - } - switch (type) { case MON1: handler = bwmon_intr_handler; @@ -1067,7 +1021,6 @@ static int bimc_bwmon_driver_probe(struct platform_device *pdev) struct bwmon *m; int ret; u32 data, count_unit; - unsigned int len, i; m = devm_kzalloc(dev, sizeof(*m), GFP_KERNEL); if (!m) @@ -1113,42 +1066,6 @@ static int bimc_bwmon_driver_probe(struct platform_device *pdev) m->mport = data; } - if (of_find_property(dev->of_node, "qcom,bwmon_clks", &len)) { - m->nr_clks = of_property_count_strings(dev->of_node, - "qcom,bwmon_clks"); - if (!m->nr_clks) { - dev_err(dev, "Failed to get clock names\n"); - return -EINVAL; - } - - m->clks = devm_kzalloc(dev, sizeof(struct clk *) * m->nr_clks, - GFP_KERNEL); - if (!m->clks) - return -ENOMEM; - - for (i = 0; i < m->nr_clks; i++) { - const char *clock_name; - - ret = of_property_read_string_index(dev->of_node, - "qcom,bwmon_clks", i, - &clock_name); - if (ret) { - pr_err("failed to read clk index %d ret %d\n", - i, ret); - return ret; - } - m->clks[i] = devm_clk_get(dev, clock_name); - if (IS_ERR(m->clks[i])) { - ret = PTR_ERR(m->clks[i]); - if (ret != -EPROBE_DEFER) - dev_err(dev, "Error to get %s clk %d\n", - clock_name, ret); - return ret; - } - } - } else - m->nr_clks = 0; - m->irq = platform_get_irq(pdev, 0); if (m->irq < 0) { dev_err(dev, "Unable to get IRQ number\n"); diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c index 586691521ec2377a20a90871b74b637fd45cde2b..0320a15ba7063a2020c84b6dc0793ad44b740146 100644 --- a/drivers/devfreq/devfreq.c +++ b/drivers/devfreq/devfreq.c @@ -28,6 +28,8 @@ #include #include "governor.h" +#include + static struct class *devfreq_class; /* @@ -253,7 +255,9 @@ int update_devfreq(struct devfreq *devfreq) unsigned long freq, cur_freq; int err = 0; u32 flags = 0; - +#ifdef CONFIG_CONTROL_CENTER + unsigned long freq_tmp; +#endif if (!mutex_is_locked(&devfreq->lock)) { WARN(true, "devfreq->lock must be locked by the caller.\n"); return -EINVAL; @@ -283,7 +287,20 @@ int update_devfreq(struct devfreq *devfreq) freq = devfreq->max_freq; flags |= DEVFREQ_FLAG_LEAST_UPPER_BOUND; /* Use LUB */ } - +#ifdef CONFIG_CONTROL_CENTER + if (cc_ddr_set_enable) { + if (devfreq->dev.cc_marked) { + freq = max((unsigned long)atomic_read(&cc_expect_ddrfreq), freq); + } + } + if (cc_ddr_lock_enable) { + if (devfreq->dev.cc_marked) { + freq_tmp = atomic_read(&cc_expect_ddrfreq); + if (freq_tmp) + freq = freq_tmp; + } + } +#endif if (devfreq->profile->get_cur_freq) devfreq->profile->get_cur_freq(devfreq->dev.parent, &cur_freq); else @@ -464,7 +481,8 @@ void devfreq_interval_update(struct devfreq *devfreq, unsigned int *delay) mutex_unlock(&devfreq->lock); cancel_delayed_work_sync(&devfreq->work); mutex_lock(&devfreq->lock); - if (!devfreq->stop_polling) + if (!devfreq->stop_polling + && !delayed_work_pending(&devfreq->work)) queue_delayed_work(devfreq_wq, &devfreq->work, msecs_to_jiffies(devfreq->profile->polling_ms)); } @@ -586,6 +604,11 @@ struct devfreq *devfreq_add_device(struct device *dev, devfreq_set_freq_limits(devfreq); dev_set_name(&devfreq->dev, "%s", dev_name(dev)); +#ifdef CONFIG_CONTROL_CENTER + if (dev_name(dev)) + devfreq->dev.cc_marked = cc_is_ddrfreq_related(dev_name(dev)); +#endif + err = device_register(&devfreq->dev); if (err) { mutex_unlock(&devfreq->lock); diff --git a/drivers/devfreq/devfreq_devbw.c b/drivers/devfreq/devfreq_devbw.c index a6b8b9fe1cc72f9313b99595143bdb1643012bad..4e479490ce07e8cebe4324ede912469ab960e4c1 100644 --- a/drivers/devfreq/devfreq_devbw.c +++ b/drivers/devfreq/devfreq_devbw.c @@ -37,6 +37,19 @@ #define MAX_PATHS 2 #define DBL_BUF 2 +#include +struct qos_request_v { + int max_state; + int max_devfreq; + int min_devfreq; +}; + +static bool cpubw_flag; +static struct qos_request_v qos_request_value = { + .max_state = 0, + .max_devfreq = INT_MAX, + .min_devfreq = 0, +}; struct dev_data { struct msm_bus_vectors vectors[MAX_PATHS * DBL_BUF]; struct msm_bus_paths bw_levels[DBL_BUF]; @@ -80,6 +93,50 @@ static int set_bw(struct device *dev, int new_ib, int new_ab) return ret; } +static void find_freq_cpubw(struct devfreq_dev_profile *p, unsigned long *freq, + u32 flags) +{ + int i; + unsigned long atmost, atleast, f; + int min_index, max_index; + + min_index = qos_request_value.min_devfreq; + if (p->max_state > qos_request_value.max_devfreq) + max_index = qos_request_value.max_devfreq; + else + max_index = p->max_state; + + atmost = p->freq_table[min_index]; + atleast = p->freq_table[max_index-1]; + + for (i = min_index; i < max_index; i++) { + f = p->freq_table[i]; + if (f <= *freq) + atmost = max(f, atmost); + if (f >= *freq) + atleast = min(f, atleast); + } + + if (flags & DEVFREQ_FLAG_LEAST_UPPER_BOUND) + *freq = atmost; + else + *freq = atleast; +} + +static int devbw_target_cpubw(struct device *dev, unsigned long *freq, + u32 flags) +{ + struct dev_data *d = dev_get_drvdata(dev); + struct dev_pm_opp *opp; + + opp = devfreq_recommended_opp(dev, freq, flags); + if (!IS_ERR(opp)) + dev_pm_opp_put(opp); + find_freq_cpubw(&d->dp, freq, flags); + + return set_bw(dev, *freq, d->gov_ab); +} + static int devbw_target(struct device *dev, unsigned long *freq, u32 flags) { struct dev_data *d = dev_get_drvdata(dev); @@ -101,6 +158,44 @@ static int devbw_get_dev_status(struct device *dev, return 0; } +static int devfreq_qos_handler(struct notifier_block *b, unsigned long val, + void *v) +{ + unsigned int max_devfreq_index, min_devfreq_index; + unsigned int index_max = 0, index_min = 0; + + max_devfreq_index = (unsigned int)pm_qos_request(PM_QOS_DEVFREQ_MAX); + min_devfreq_index = (unsigned int)pm_qos_request(PM_QOS_DEVFREQ_MIN); + + /* add limit */ + if (max_devfreq_index & MASK_CPUFREQ) { + index_max = MAX_CPUFREQ - max_devfreq_index; + if (index_max > qos_request_value.max_state) + index_max = 0; + index_max = qos_request_value.max_state - index_max; + } else { + if (max_devfreq_index > qos_request_value.max_state) + index_max = qos_request_value.max_state; + } + if (min_devfreq_index & MASK_CPUFREQ) { + index_min = MAX_CPUFREQ - min_devfreq_index; + if (index_min > (qos_request_value.max_state-1)) + index_min = 0; + index_min = qos_request_value.max_state - 1 - index_min; + } else { + if (min_devfreq_index > qos_request_value.max_state) + index_min = qos_request_value.max_state - 1; + } + + qos_request_value.min_devfreq = index_min; + qos_request_value.max_devfreq = index_max; + + return NOTIFY_OK; +} +static struct notifier_block devfreq_qos_notifier = { + .notifier_call = devfreq_qos_handler, +}; + #define PROP_OPERATING_POINTS_V2 "operating-points-v2" static int add_opp_prop_from_child(struct device *dev, @@ -212,7 +307,13 @@ int devfreq_add_devbw(struct device *dev) p = &d->dp; p->polling_ms = 50; - p->target = devbw_target; + + if (strnstr(d->bw_data.name, "soc:qcom,cpu-cpu-llcc-bw", + strlen(d->bw_data.name)) != NULL) { + p->target = devbw_target_cpubw; + cpubw_flag = true; + } else + p->target = devbw_target; p->get_dev_status = devbw_get_dev_status; if (of_get_child_count(dev->of_node)) ret = parse_child_nodes_for_opp(dev); @@ -237,6 +338,12 @@ int devfreq_add_devbw(struct device *dev) return PTR_ERR(d->df); } + if (cpubw_flag) { + cpubw_flag = false; + qos_request_value.max_state = p->max_state; + qos_request_value.min_devfreq = 0; + qos_request_value.max_devfreq = p->max_state; + } return 0; } @@ -284,10 +391,20 @@ static struct platform_driver devbw_driver = { .driver = { .name = "devbw", .of_match_table = devbw_match_table, + .owner = THIS_MODULE, .suppress_bind_attrs = true, }, }; -module_platform_driver(devbw_driver); +static int __init devbw_init(void) +{ + /* add cpufreq qos notify */ + cpubw_flag = false; + pm_qos_add_notifier(PM_QOS_DEVFREQ_MAX, &devfreq_qos_notifier); + pm_qos_add_notifier(PM_QOS_DEVFREQ_MIN, &devfreq_qos_notifier); + platform_driver_register(&devbw_driver); + return 0; +} +device_initcall(devbw_init); MODULE_DESCRIPTION("Device DDR bandwidth voting driver MSM SoCs"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/devfreq/governor_bw_hwmon.c b/drivers/devfreq/governor_bw_hwmon.c index 330c45a8c1fe30a5994761b1c29b925c59f8447b..164d622c3a5034e3e826680b0da2c3ba7a793fe7 100644 --- a/drivers/devfreq/governor_bw_hwmon.c +++ b/drivers/devfreq/governor_bw_hwmon.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2013-2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -617,8 +617,7 @@ static int gov_start(struct devfreq *df) node->orig_data = df->data; df->data = node; - ret = start_monitor(df, true); - if (ret) + if (start_monitor(df, true)) goto err_start; ret = sysfs_create_group(&df->dev.kobj, node->attr_grp); diff --git a/drivers/dma/qcom/gpi.c b/drivers/dma/qcom/gpi.c index ca1028e7ab455abf1c3c06ada249c0097f707eb9..eab48c682d850a14ee43e61289dae30a9a34fe38 100644 --- a/drivers/dma/qcom/gpi.c +++ b/drivers/dma/qcom/gpi.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -441,7 +441,6 @@ struct gpi_dev { struct device *dev; struct resource *res; void __iomem *regs; - void __iomem *ee_base; /*ee register base address*/ u32 max_gpii; /* maximum # of gpii instances available per gpi block */ u32 gpii_mask; /* gpii instances available for apps */ u32 ev_factor; /* ev ring length factor */ @@ -2650,7 +2649,6 @@ static int gpi_probe(struct platform_device *pdev) { struct gpi_dev *gpi_dev; int ret, i; - u32 gpi_ee_offset; gpi_dev = devm_kzalloc(&pdev->dev, sizeof(*gpi_dev), GFP_KERNEL); if (!gpi_dev) @@ -2671,8 +2669,6 @@ static int gpi_probe(struct platform_device *pdev) return -EFAULT; } - gpi_dev->ee_base = gpi_dev->regs; - ret = of_property_read_u32(gpi_dev->dev->of_node, "qcom,max-num-gpii", &gpi_dev->max_gpii); if (ret) { @@ -2687,14 +2683,6 @@ static int gpi_probe(struct platform_device *pdev) return ret; } - ret = of_property_read_u32(gpi_dev->dev->of_node, - "qcom,gpi-ee-offset", &gpi_ee_offset); - if (ret) - GPI_LOG(gpi_dev, "No variable ee offset present\n"); - else - gpi_dev->ee_base = - gpi_dev->ee_base - gpi_ee_offset; - ret = of_property_read_u32(gpi_dev->dev->of_node, "qcom,ev-factor", &gpi_dev->ev_factor); if (ret) { @@ -2744,6 +2732,7 @@ static int gpi_probe(struct platform_device *pdev) if (!gpi_dev->gpiis) return -ENOMEM; + /* setup all the supported gpii */ INIT_LIST_HEAD(&gpi_dev->dma_device.channels); for (i = 0; i < gpi_dev->max_gpii; i++) { @@ -2754,9 +2743,9 @@ static int gpi_probe(struct platform_device *pdev) continue; /* set up ev cntxt register map */ - gpii->ev_cntxt_base_reg = gpi_dev->ee_base + + gpii->ev_cntxt_base_reg = gpi_dev->regs + GPI_GPII_n_EV_CH_k_CNTXT_0_OFFS(i, 0); - gpii->ev_cntxt_db_reg = gpi_dev->ee_base + + gpii->ev_cntxt_db_reg = gpi_dev->regs + GPI_GPII_n_EV_CH_k_DOORBELL_0_OFFS(i, 0); gpii->ev_ring_base_lsb_reg = gpii->ev_cntxt_base_reg + CNTXT_2_RING_BASE_LSB; @@ -2764,11 +2753,11 @@ static int gpi_probe(struct platform_device *pdev) CNTXT_4_RING_RP_LSB; gpii->ev_ring_wp_lsb_reg = gpii->ev_cntxt_base_reg + CNTXT_6_RING_WP_LSB; - gpii->ev_cmd_reg = gpi_dev->ee_base + + gpii->ev_cmd_reg = gpi_dev->regs + GPI_GPII_n_EV_CH_CMD_OFFS(i); - gpii->ieob_src_reg = gpi_dev->ee_base + + gpii->ieob_src_reg = gpi_dev->regs + GPI_GPII_n_CNTXT_SRC_IEOB_IRQ_OFFS(i); - gpii->ieob_clr_reg = gpi_dev->ee_base + + gpii->ieob_clr_reg = gpi_dev->regs + GPI_GPII_n_CNTXT_SRC_IEOB_IRQ_CLR_OFFS(i); /* set up irq */ @@ -2785,9 +2774,9 @@ static int gpi_probe(struct platform_device *pdev) struct gpii_chan *gpii_chan = &gpii->gpii_chan[chan]; /* set up ch cntxt register map */ - gpii_chan->ch_cntxt_base_reg = gpi_dev->ee_base + + gpii_chan->ch_cntxt_base_reg = gpi_dev->regs + GPI_GPII_n_CH_k_CNTXT_0_OFFS(i, chan); - gpii_chan->ch_cntxt_db_reg = gpi_dev->ee_base + + gpii_chan->ch_cntxt_db_reg = gpi_dev->regs + GPI_GPII_n_CH_k_DOORBELL_0_OFFS(i, chan); gpii_chan->ch_ring_base_lsb_reg = gpii_chan->ch_cntxt_base_reg + @@ -2798,7 +2787,7 @@ static int gpi_probe(struct platform_device *pdev) gpii_chan->ch_ring_wp_lsb_reg = gpii_chan->ch_cntxt_base_reg + CNTXT_6_RING_WP_LSB; - gpii_chan->ch_cmd_reg = gpi_dev->ee_base + + gpii_chan->ch_cmd_reg = gpi_dev->regs + GPI_GPII_n_CH_CMD_OFFS(i); /* vchan setup */ @@ -2814,7 +2803,7 @@ static int gpi_probe(struct platform_device *pdev) (unsigned long)gpii); init_completion(&gpii->cmd_completion); gpii->gpii_id = i; - gpii->regs = gpi_dev->ee_base; + gpii->regs = gpi_dev->regs; gpii->gpi_dev = gpi_dev; atomic_set(&gpii->dbg_index, 0); } diff --git a/drivers/esoc/esoc-mdm-4x.c b/drivers/esoc/esoc-mdm-4x.c index 2ff2972d454bbae57eaf4e5a2c4ee7afc35142f2..eb9399724211e8856e7f496fe248f79ea8ae50c7 100644 --- a/drivers/esoc/esoc-mdm-4x.c +++ b/drivers/esoc/esoc-mdm-4x.c @@ -16,6 +16,8 @@ #include #include #include "esoc-mdm.h" +#include +#include enum gpio_update_config { GPIO_UPDATE_BOOTING_CONFIG = 1, @@ -264,12 +266,20 @@ static int mdm_cmd_exe(enum esoc_cmd cmd, struct esoc_clink *esoc) if (esoc->statusline_not_a_powersource == false) { esoc_mdm_log( "ESOC_FORCE_PWR_OFF: setting AP2MDM_STATUS = 0\n"); - gpio_set_value(MDM_GPIO(mdm, AP2MDM_STATUS), 0); + dev_err(mdm->dev, + "ESOC_FORCE_PWR_OFF: setting AP2MDM_STATUS = 0\n"); + //gpio_set_value(MDM_GPIO(mdm, AP2MDM_STATUS), 0); } esoc_mdm_log( "ESOC_FORCE_PWR_OFF: Queueing request: ESOC_REQ_SHUTDOWN\n"); + dev_err(mdm->dev, + "ESOC_FORCE_PWR_OFF: Queueing request: ESOC_REQ_SHUTDOWN\n"); esoc_clink_queue_request(ESOC_REQ_SHUTDOWN, esoc); + dev_err(mdm->dev, + "ESOC_FORCE_PWR_OFF: mdm_power_down start!\n"); mdm_power_down(mdm); + dev_err(mdm->dev, + "ESOC_FORCE_PWR_OFF: mdm_power_down end!\n"); mdm_update_gpio_configs(mdm, GPIO_UPDATE_BOOTING_CONFIG); break; case ESOC_RESET: @@ -394,6 +404,26 @@ static void mdm_get_restart_reason(struct work_struct *work) __func__, ret); } mdm->get_restart_reason = false; + + if (is_oem_esoc_ssr() == 1) { + oem_set_esoc_ssr(0); + } + + if (oem_get_download_mode()) { + char detial_buf[] = "\nSDX5x esoc0 modem crash"; + + oem_set_esoc_ssr(0); + if ((strlen(sfr_buf)+sizeof(detial_buf)) < RD_BUF_SIZE) + strncat(sfr_buf, detial_buf, strlen(detial_buf)); + + esoc_mdm_log( + "[OEM_MDM] Trigger panic by OEM to get SDX5x dump!\n"); + dev_err(dev, + "[OEM_MDM] Trigger panic by OEM to get SDX5x dump!\n"); + msleep(5000); + mdm_power_down(mdm); + panic(sfr_buf); + } } void mdm_wait_for_status_low(struct mdm_ctrl *mdm, bool atomic) @@ -846,6 +876,23 @@ static void mdm_free_irq(struct mdm_ctrl *mdm) free_irq(mdm->status_irq, mdm); } +static int esoc_ssr_reason_feature_enable =0; +int get_ssr_reason_state(void) +{ + return esoc_ssr_reason_feature_enable; +} + +static int esoc_ssr_occur =0; +int oem_set_esoc_ssr(int enable) +{ + esoc_ssr_occur = enable; + return 0; +} +int is_oem_esoc_ssr(void) +{ + return esoc_ssr_occur; +} + static int mdm9x55_setup_hw(struct mdm_ctrl *mdm, const struct mdm_ops *ops, struct platform_device *pdev) @@ -1014,6 +1061,10 @@ static int sdx50m_setup_hw(struct mdm_ctrl *mdm, mdm->skip_restart_for_mdm_crash = of_property_read_bool(node, "qcom,esoc-skip-restart-for-mdm-crash"); + esoc_ssr_reason_feature_enable = of_property_read_bool(node, + "oem,esoc_ssr_reason_feature_enable"); + + esoc->clink_ops = clink_ops; esoc->parent = mdm->dev; esoc->owner = THIS_MODULE; @@ -1115,6 +1166,12 @@ static int mdm_probe(struct platform_device *pdev) struct mdm_ctrl *mdm; int ret; + if (get_second_board_absent() == 1) { + pr_err("%s second board absent, don't probe esoc-mdm-4x", + __func__); + ret = -1; + return ret; + } match = of_match_node(mdm_dt_match, node); if (IS_ERR_OR_NULL(match)) return PTR_ERR(match); @@ -1145,6 +1202,12 @@ static struct platform_driver mdm_driver = { static int __init mdm_register(void) { + if (get_second_board_absent() == 1) { + pr_err("%s second board absent, don't probe esoc-mdm-4x", + __func__); + return false; + } + return platform_driver_register(&mdm_driver); } module_init(mdm_register); diff --git a/drivers/esoc/esoc-mdm-dbg-eng.c b/drivers/esoc/esoc-mdm-dbg-eng.c index d3b4bd7fa717c613f75c16cd5974d904bb5be5b5..8eb4fea0ec0aeefc7d9cf235a4cd9f22ac38834d 100644 --- a/drivers/esoc/esoc-mdm-dbg-eng.c +++ b/drivers/esoc/esoc-mdm-dbg-eng.c @@ -12,6 +12,7 @@ #include #include #include "esoc.h" +#include /* * cmd_mask : Specifies if a command/notifier is masked, and @@ -342,6 +343,12 @@ int mdm_dbg_eng_init(struct esoc_drv *esoc_drv, int ret; struct device_driver *drv = &esoc_drv->driver; + if (get_second_board_absent() == 1) { + pr_err("%s second board absent, don't probe esoc-mdm-dbg-eng", + __func__); + ret = -1; + return ret; + } ret = driver_create_file(drv, &driver_attr_command_mask); if (ret) { pr_err("Unable to create command mask file\n"); diff --git a/drivers/esoc/esoc-mdm-drv.c b/drivers/esoc/esoc-mdm-drv.c index 827b84b71cdca8d941c15a6545e51e080e0f19b4..b85872ab873eeb5a5e4e6904e8beeb1578ba4ece 100755 --- a/drivers/esoc/esoc-mdm-drv.c +++ b/drivers/esoc/esoc-mdm-drv.c @@ -18,6 +18,7 @@ #include "esoc.h" #include "esoc-mdm.h" #include "mdm-dbg.h" +#include /* Default number of powerup trial requests per session */ #define ESOC_DEF_PON_REQ 3 @@ -26,6 +27,8 @@ #define BOOT_FAIL_ACTION_DEF BOOT_FAIL_ACTION_PANIC +bool modem_5G_panic; + enum esoc_pon_state { PON_INIT, PON_SUCCESS, @@ -184,6 +187,7 @@ static void mdm_handle_clink_evt(enum esoc_evt evt, esoc_mdm_log("Modem not up. Ignoring.\n"); if (mdm_drv->mode == CRASH || mdm_drv->mode != RUN) return; + mdm_drv->mode = CRASH; queue_work(mdm_drv->mdm_queue, &mdm_drv->ssr_work); break; case ESOC_REQ_ENG_ON: @@ -205,9 +209,7 @@ static void mdm_ssr_fn(struct work_struct *work) mdm_wait_for_status_low(mdm, false); - esoc_mdm_log("Starting SSR work and setting crash state\n"); - mdm_drv->mode = CRASH; - + esoc_mdm_log("Starting SSR work\n"); /* * If restarting esoc fails, the SSR framework triggers a kernel panic */ @@ -284,7 +286,7 @@ static void mdm_crash_shutdown(const struct subsys_desc *mdm_subsys) static int mdm_subsys_shutdown(const struct subsys_desc *crashed_subsys, bool force_stop) { - int ret = 0; + int ret; struct esoc_clink *esoc_clink = container_of(crashed_subsys, struct esoc_clink, subsys); struct mdm_drv *mdm_drv = esoc_get_drv_data(esoc_clink); @@ -292,16 +294,14 @@ static int mdm_subsys_shutdown(const struct subsys_desc *crashed_subsys, esoc_mdm_log("Shutdown request from SSR\n"); - mutex_lock(&mdm_drv->poff_lock); if (mdm_drv->mode == CRASH || mdm_drv->mode == PEER_CRASH) { esoc_mdm_log("Shutdown in crash mode\n"); - if (mdm_dbg_stall_cmd(ESOC_PREPARE_DEBUG)) { + if (mdm_dbg_stall_cmd(ESOC_PREPARE_DEBUG)) /* We want to mask debug command. * In this case return success * to move to next stage */ - goto unlock; - } + return 0; esoc_clink_queue_request(ESOC_REQ_CRASH_SHUTDOWN, esoc_clink); esoc_client_link_power_off(esoc_clink, ESOC_HOOK_MDM_CRASH); @@ -312,14 +312,16 @@ static int mdm_subsys_shutdown(const struct subsys_desc *crashed_subsys, if (ret) { esoc_mdm_log("ESOC_PREPARE_DEBUG command failed\n"); dev_err(&esoc_clink->dev, "failed to enter debug\n"); - goto unlock; + return ret; } mdm_drv->mode = IN_DEBUG; } else if (!force_stop) { esoc_mdm_log("Graceful shutdown mode\n"); + mutex_lock(&mdm_drv->poff_lock); if (mdm_drv->mode == PWR_OFF) { + mutex_unlock(&mdm_drv->poff_lock); esoc_mdm_log("mdm already powered-off\n"); - goto unlock; + return 0; } if (esoc_clink->subsys.sysmon_shutdown_ret) { esoc_mdm_log( @@ -332,7 +334,8 @@ static int mdm_subsys_shutdown(const struct subsys_desc *crashed_subsys, * we return success, and leave the state * of the command engine as is. */ - goto unlock; + mutex_unlock(&mdm_drv->poff_lock); + return 0; } dev_dbg(&esoc_clink->dev, "Sending sysmon-shutdown\n"); esoc_mdm_log("Executing the ESOC_PWR_OFF command\n"); @@ -342,18 +345,17 @@ static int mdm_subsys_shutdown(const struct subsys_desc *crashed_subsys, esoc_mdm_log( "Executing the ESOC_PWR_OFF command failed\n"); dev_err(&esoc_clink->dev, "failed to exe power off\n"); - goto unlock; + mutex_unlock(&mdm_drv->poff_lock); + return ret; } esoc_client_link_power_off(esoc_clink, ESOC_HOOK_MDM_DOWN); /* Pull the reset line low to turn off the device */ clink_ops->cmd_exe(ESOC_FORCE_PWR_OFF, esoc_clink); mdm_drv->mode = PWR_OFF; + mutex_unlock(&mdm_drv->poff_lock); } esoc_mdm_log("Shutdown completed\n"); - -unlock: - mutex_unlock(&mdm_drv->poff_lock); - return ret; + return 0; } static void mdm_subsys_retry_powerup_cleanup(struct esoc_clink *esoc_clink, @@ -411,7 +413,10 @@ static int mdm_handle_boot_fail(struct esoc_clink *esoc_clink, u8 *pon_trial) break; case BOOT_FAIL_ACTION_PANIC: esoc_mdm_log("Calling panic!!\n"); - panic("Panic requested on external modem boot failure\n"); + if (get_second_board_absent() == 0 && oem_get_download_mode()) + panic("Panic requested on external modem boot failure\n"); + else + pr_err("Panic requested on external modem boot failure\n"); break; case BOOT_FAIL_ACTION_NOP: esoc_mdm_log("Leaving the modem in its curent state\n"); @@ -436,8 +441,11 @@ static int mdm_subsys_powerup(const struct subsys_desc *crashed_subsys) subsys); struct mdm_drv *mdm_drv = esoc_get_drv_data(esoc_clink); const struct esoc_clink_ops * const clink_ops = esoc_clink->clink_ops; + struct mdm_ctrl *mdm = get_esoc_clink_data(mdm_drv->esoc_clink); int timeout = INT_MAX; + u8 pon_trial = 0; + modem_5G_panic = false; esoc_mdm_log("Powerup request from SSR\n"); @@ -508,11 +516,33 @@ static int mdm_subsys_powerup(const struct subsys_desc *crashed_subsys) "Boot failed. Doing cleanup and attempting to retry\n"); pon_trial++; mdm_subsys_retry_powerup_cleanup(esoc_clink, 0); + + /* PON_RETRY : SDX5X jump to normal mode from dump mode */ + if (!oem_get_download_mode()) { + pr_err("[MDM] DumpMode is disabled. Skip trigger 5G dump\n"); + } else if (is_oem_esoc_ssr() == 1 || get_ssr_reason_state() == 1) { + pr_err("[MDM] Skip trigger during the oem esoc SSR\n"); + } else { + pr_err("[MDM] Trigger kernel panic to get SDX5X dump\n"); + modem_5G_panic = true; + } } else if (mdm_drv->pon_state == PON_SUCCESS) { break; } } while (pon_trial <= atomic_read(&mdm_drv->n_pon_tries)); + //because two times powerup flow, make sure SDX50 is ready + pr_err("[MDM] Roland: check 5G dump gpio\n"); + if (gpio_get_value(MDM_GPIO(mdm, MDM2AP_STATUS)) == 1) { + pr_err("[MDM] gpio check pass, 5g flag [%d]\n", modem_5G_panic); + if (modem_5G_panic == true) { + pr_err("[MDM] Power done SDX50 and wait 5s\n"); + msleep(5000); + mdm_power_down(mdm); + panic("get the SDX50 dump"); // warm reset device + } + } + return 0; } @@ -557,6 +587,12 @@ int esoc_ssr_probe(struct esoc_clink *esoc_clink, struct esoc_drv *drv) struct mdm_drv *mdm_drv; struct esoc_eng *esoc_eng; + if (get_second_board_absent() == 1) { + pr_err("%s second board absent, don't probe esoc-mdm-drv", + __func__); + ret = -1; + return ret; + } mdm_drv = devm_kzalloc(&esoc_clink->dev, sizeof(*mdm_drv), GFP_KERNEL); if (IS_ERR_OR_NULL(mdm_drv)) return PTR_ERR(mdm_drv); @@ -633,6 +669,11 @@ static struct esoc_drv esoc_ssr_drv = { int __init esoc_ssr_init(void) { + if (get_second_board_absent() == 1) { + pr_err("%s second board absent, don't probe esoc-mdm-drv", + __func__); + return false; + } return esoc_drv_register(&esoc_ssr_drv); } module_init(esoc_ssr_init); diff --git a/drivers/esoc/esoc-mdm-pon.c b/drivers/esoc/esoc-mdm-pon.c index 6e75fb5a4dbd80f971fb32e21e276ba97b7a79e4..31033f425324dd103a46900a0a9c836a1f1585a5 100644 --- a/drivers/esoc/esoc-mdm-pon.c +++ b/drivers/esoc/esoc-mdm-pon.c @@ -11,6 +11,7 @@ */ #include "esoc-mdm.h" +#include /* This function can be called from atomic context. */ static int mdm9x55_toggle_soft_reset(struct mdm_ctrl *mdm, bool atomic) @@ -205,7 +206,11 @@ static int mdm9x55_pon_dt_init(struct mdm_ctrl *mdm) struct device_node *node = mdm->dev->of_node; enum of_gpio_flags flags = OF_GPIO_ACTIVE_LOW; - + if (get_second_board_absent() == 1) { + pr_err("%s second board absent, don't probe esoc-mdm-pon", + __func__); + return false; + } val = of_property_read_u32(node, "qcom,reset-time-ms", &mdm->reset_time_ms); if (val) @@ -228,6 +233,11 @@ static int mdm4x_pon_dt_init(struct mdm_ctrl *mdm) struct device_node *node = mdm->dev->of_node; enum of_gpio_flags flags = OF_GPIO_ACTIVE_LOW; + if (get_second_board_absent() == 1) { + pr_err("%s second board absent, don't probe esoc-mdm-pon", + __func__); + return false; + } val = of_get_named_gpio_flags(node, "qcom,ap2mdm-soft-reset-gpio", 0, &flags); if (val >= 0) { diff --git a/drivers/esoc/esoc_bus.c b/drivers/esoc/esoc_bus.c index 39060590b72fef40ecb728c9b76f14193676f44d..fbb2f500ace607f7f067e600e044206eb0ac7f93 100644 --- a/drivers/esoc/esoc_bus.c +++ b/drivers/esoc/esoc_bus.c @@ -13,6 +13,7 @@ #include #include #include "esoc.h" +#include static DEFINE_IDA(esoc_ida); @@ -387,6 +388,11 @@ static int __init esoc_init(void) { int ret; + if (get_second_board_absent() == 1) { + pr_err("%s second board absent, don't probe esoc", __func__); + ret = -1; + return ret; + } ret = device_register(&esoc_bus); if (ret) { pr_err("esoc bus device register fail\n"); diff --git a/drivers/esoc/esoc_dev.c b/drivers/esoc/esoc_dev.c index bd3929074eea04a1c6b4532c62860818916813fd..b252d8746ffb0fec75b610aea5d7c745361436f9 100644 --- a/drivers/esoc/esoc_dev.c +++ b/drivers/esoc/esoc_dev.c @@ -16,6 +16,7 @@ #include #include #include "esoc.h" +#include /** * struct esoc_udev: Userspace char interface @@ -469,6 +470,12 @@ int __init esoc_dev_init(void) { int ret = 0; + if (get_second_board_absent() == 1) { + pr_err("%s second board absent,don't probe esoc_dev", + __func__); + ret = -1; + return ret; + } esoc_class = class_create(THIS_MODULE, "esoc-dev"); if (IS_ERR_OR_NULL(esoc_class)) { pr_err("coudn't create class"); diff --git a/drivers/firmware/qcom/tz_log.c b/drivers/firmware/qcom/tz_log.c index 55444788ba5046bc52d2e79e90c4b556448a6bf3..2339c16c613b953be6bc998d356db2f023e8ce49 100644 --- a/drivers/firmware/qcom/tz_log.c +++ b/drivers/firmware/qcom/tz_log.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include @@ -904,6 +905,103 @@ static void tzdbg_register_qsee_log_buf(struct platform_device *pdev) return; } +//add tz and qsee log to logkit +static ssize_t proc_qsee_log_func(struct file *file, char __user *user_buf, + size_t count, loff_t *ppos) +{ + int len = 0; + + memcpy_fromio((void *)tzdbg.diag_buf, tzdbg.virt_iobase, + debug_rw_buf_size); + memcpy_fromio((void *)tzdbg.hyp_diag_buf, tzdbg.hyp_virt_iobase, + tzdbg.hyp_debug_rw_buf_size); + len = _disp_qsee_log_stats(count); + *ppos = 0; + + if (len > count) + len = count; + + return simple_read_from_buffer(user_buf, len, ppos, + tzdbg.stat[6].data, len); +} + + +static const struct file_operations proc_qsee_log_fops = { + .read = proc_qsee_log_func, + .open = simple_open, + .owner = THIS_MODULE, +}; + +static ssize_t proc_tz_log_func(struct file *file, char __user *user_buf, + size_t count, loff_t *ppos) +{ + int len = 0; + + memcpy_fromio((void *)tzdbg.diag_buf, tzdbg.virt_iobase, + debug_rw_buf_size); + memcpy_fromio((void *)tzdbg.hyp_diag_buf, tzdbg.hyp_virt_iobase, + tzdbg.hyp_debug_rw_buf_size); + + if (TZBSP_DIAG_MAJOR_VERSION_LEGACY < + (tzdbg.diag_buf->version >> 16)) { + len = _disp_tz_log_stats(count); + *ppos = 0; + } else { + len = _disp_tz_log_stats_legacy(); + } + + if (len > count) + len = count; + + return simple_read_from_buffer(user_buf, len, ppos, + tzdbg.stat[5].data, len); +} + +static const struct file_operations proc_tz_log_fops = { + .read = proc_tz_log_func, + .open = simple_open, + .owner = THIS_MODULE, +}; + +static int tzprocfs_init(struct platform_device *pdev) +{ + int rc = 0; + struct proc_dir_entry *prEntry_tmp = NULL; + struct proc_dir_entry *prEntry_dir = NULL; + + prEntry_dir = proc_mkdir("tzdbg", NULL); + + if (prEntry_dir == NULL) { + dev_err(&pdev->dev, "tzdbg procfs_create_dir failed\n"); + return -ENOMEM; + } + + prEntry_tmp = proc_create("qsee_log", 0666, + prEntry_dir, &proc_qsee_log_fops); + + if (prEntry_tmp == NULL) { + dev_err(&pdev->dev, "TZ procfs_create_file qsee_log failed\n"); + rc = -ENOMEM; + goto err; + } + + prEntry_tmp = proc_create("tz_log", 0666, + prEntry_dir, &proc_tz_log_fops); + + if (prEntry_tmp == NULL) { + dev_err(&pdev->dev, "TZ procfs_create_file tz_log failed\n"); + rc = -ENOMEM; + goto err; + } + + return 0; +err: + proc_remove(prEntry_dir); + + return rc; +} + + static int tzdbgfs_init(struct platform_device *pdev) { int rc = 0; @@ -1099,6 +1197,11 @@ static int tz_log_probe(struct platform_device *pdev) if (tzdbgfs_init(pdev)) goto err; + //add tz and qsee log to logkit + if (tzprocfs_init(pdev)) + goto err; + + tzdbg_register_qsee_log_buf(pdev); tzdbg_get_tz_version(); diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index 9317f66d48451c55733c26f5177929d485248f7f..9a3ba3047b0bb0acb6965954c0acf3265f05873b 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -245,8 +245,6 @@ source "drivers/gpu/drm/msm/Kconfig" source "drivers/gpu/drm/msm-hyp/Kconfig" -source "drivers/gpu/drm/msm-lease/Kconfig" - source "drivers/gpu/drm/fsl-dcu/Kconfig" source "drivers/gpu/drm/tegra/Kconfig" diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index 74efa90f47425945b5d6593f498ad863cb04db61..e6ef7a7c1139dcc30f87764d3f74ab852d5f2b9a 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -85,7 +85,6 @@ obj-$(CONFIG_DRM_BOCHS) += bochs/ obj-$(CONFIG_DRM_VIRTIO_GPU) += virtio/ obj-$(CONFIG_DRM_MSM) += msm/ obj-$(CONFIG_DRM_MSM_HYP) += msm-hyp/ -obj-$(CONFIG_DRM_MSM_LEASE) += msm-lease/ obj-$(CONFIG_DRM_TEGRA) += tegra/ obj-$(CONFIG_DRM_STM) += stm/ obj-$(CONFIG_DRM_STI) += sti/ diff --git a/drivers/gpu/drm/drm_internal.h b/drivers/gpu/drm/drm_internal.h index fbc3f308fa1997ab5889f3f25fb7357106ea5909..1e86b08a7ea3abd51a79b9688587b4a5f52411e2 100644 --- a/drivers/gpu/drm/drm_internal.h +++ b/drivers/gpu/drm/drm_internal.h @@ -106,6 +106,67 @@ int drm_gem_open_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); void drm_gem_open(struct drm_device *dev, struct drm_file *file_private); void drm_gem_release(struct drm_device *dev, struct drm_file *file_private); +int dsi_display_set_hbm_mode(struct drm_connector *connector, int level); +int dsi_display_get_hbm_mode(struct drm_connector *connector); + + +int dsi_display_get_serial_number(struct drm_connector *connector); +int dsi_display_get_serial_number_year(struct drm_connector *connector); +int dsi_display_get_serial_number_mon(struct drm_connector *connector); +int dsi_display_get_serial_number_day(struct drm_connector *connector); +int dsi_display_get_serial_number_hour(struct drm_connector *connector); +int dsi_display_get_serial_number_min(struct drm_connector *connector); +int dsi_display_set_acl_mode(struct drm_connector *connector, int level); +int dsi_display_get_acl_mode(struct drm_connector *connector); +int dsi_display_set_hbm_mode(struct drm_connector *connector, int level); +int dsi_display_get_hbm_mode(struct drm_connector *connector); +int dsi_display_set_hbm_brightness(struct drm_connector *connector, int level); +int dsi_display_get_hbm_brightness(struct drm_connector *connector); +int dsi_display_set_aod_mode(struct drm_connector *connector, int level); +int dsi_display_get_aod_mode(struct drm_connector *connector); +int dsi_display_set_dci_p3_mode(struct drm_connector *connector, int level); +int dsi_display_get_dci_p3_mode(struct drm_connector *connector); +int dsi_display_set_night_mode(struct drm_connector *connector, int level); +int dsi_display_get_night_mode(struct drm_connector *connector); +int dsi_display_get_serial_number(struct drm_connector *connector); +int dsi_display_get_serial_number_year(struct drm_connector *connector); +int dsi_display_get_serial_number_mon(struct drm_connector *connector); +int dsi_display_get_serial_number_day(struct drm_connector *connector); +int dsi_display_get_serial_number_hour(struct drm_connector *connector); +int dsi_display_get_serial_number_min(struct drm_connector *connector); +int dsi_display_get_serial_number_sec(struct drm_connector *connector); +uint64_t dsi_display_get_serial_number_id(uint64_t serial_number); +int dsi_display_get_code_info(struct drm_connector *connector); +int dsi_display_get_stage_info(struct drm_connector *connector); +int dsi_display_get_production_info(struct drm_connector *connector); +int dsi_display_panel_mismatch_check(struct drm_connector *connector); +int dsi_display_panel_mismatch(struct drm_connector *connector); +int dsi_display_set_aod_disable(struct drm_connector *connector, int disable); +int dsi_display_get_aod_disable(struct drm_connector *connector); +int dsi_display_set_fp_hbm_mode(struct drm_connector *connector, int level); +int dsi_display_get_fp_hbm_mode(struct drm_connector *connector); +int dsi_display_update_dsi_on_command(struct drm_connector *connector, const char *buf, size_t count); +int dsi_display_get_dsi_on_command(struct drm_connector *connector, char *buf); +int dsi_display_update_dsi_panel_command(struct drm_connector *connector, const char *buf, size_t count); +int dsi_display_get_dsi_panel_command(struct drm_connector *connector, char *buf); +int dsi_display_update_dsi_seed_command(struct drm_connector *connector, const char *buf, size_t count); +int dsi_display_get_dsi_seed_command(struct drm_connector *connector, char *buf); +int dsi_display_set_native_display_p3_mode(struct drm_connector *connector, int level); +int dsi_display_get_native_display_p3_mode(struct drm_connector *connector); +int dsi_display_set_native_display_wide_color_mode(struct drm_connector *connector, int level); +int dsi_display_get_native_display_wide_color_mode(struct drm_connector *connector); +int dsi_display_set_native_display_srgb_color_mode(struct drm_connector *connector, int level); +int dsi_display_get_native_display_srgb_color_mode(struct drm_connector *connector); +int dsi_display_set_native_loading_effect_mode(struct drm_connector *connector, int level); +int dsi_display_get_native_display_loading_effect_mode(struct drm_connector *connector); +int dsi_display_set_customer_srgb_mode(struct drm_connector *connector, int level); +int dsi_display_set_customer_p3_mode(struct drm_connector *connector, int level); +int dsi_display_get_customer_srgb_mode(struct drm_connector *connector); +int dsi_display_get_customer_p3_mode(struct drm_connector *connector); + + + + /* drm_debugfs.c drm_debugfs_crc.c */ #if defined(CONFIG_DEBUG_FS) diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c index 0746ac89fcc59672bd8f15b78f318ce36c11c876..e5621b91bac039514209b26db6f3c65a7856f661 100644 --- a/drivers/gpu/drm/drm_mipi_dsi.c +++ b/drivers/gpu/drm/drm_mipi_dsi.c @@ -561,8 +561,8 @@ EXPORT_SYMBOL(mipi_dsi_set_maximum_return_packet_size); * Return: The number of bytes transmitted on success or a negative error code * on failure. */ -ssize_t mipi_dsi_generic_write(struct mipi_dsi_device *dsi, const void *payload, - size_t size) +ssize_t mipi_dsi_generic_write(struct mipi_dsi_device *dsi, void *payload, + size_t size) { struct mipi_dsi_msg msg = { .channel = dsi->channel, @@ -606,8 +606,9 @@ EXPORT_SYMBOL(mipi_dsi_generic_write); * Return: The number of bytes successfully read or a negative error code on * failure. */ -ssize_t mipi_dsi_generic_read(struct mipi_dsi_device *dsi, const void *params, - size_t num_params, void *data, size_t size) +ssize_t mipi_dsi_generic_read(struct mipi_dsi_device *dsi, void *params, + size_t num_params, void *data, size_t size) + { struct mipi_dsi_msg msg = { .channel = dsi->channel, @@ -651,7 +652,8 @@ EXPORT_SYMBOL(mipi_dsi_generic_read); * code on failure. */ ssize_t mipi_dsi_dcs_write_buffer(struct mipi_dsi_device *dsi, - const void *data, size_t len) + void *data, size_t len) + { struct mipi_dsi_msg msg = { .channel = dsi->channel, @@ -1093,6 +1095,43 @@ int mipi_dsi_dcs_get_display_brightness(struct mipi_dsi_device *dsi, } EXPORT_SYMBOL(mipi_dsi_dcs_get_display_brightness); +/** + * mipi_dsi_dcs_set_display_brightness_samsung() - sets the brightness value of the + * display + * @dsi: DSI peripheral device + * @brightness: brightness value + * + * Return: 0 on success or a negative error code on failure. + */ +int mipi_dsi_dcs_set_display_brightness_samsung(struct mipi_dsi_device *dsi, + u16 brightness) +{ + u8 payload[2] = {brightness >> 8, brightness & 0xff}; + ssize_t err; + + err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_DISPLAY_BRIGHTNESS, + payload, sizeof(payload)); + if (err < 0) + return err; + + return 0; +} +EXPORT_SYMBOL(mipi_dsi_dcs_set_display_brightness_samsung); + +int mipi_dsi_dcs_write_c1(struct mipi_dsi_device *dsi, + u16 read_number) +{ + u8 payload[3] = {0x0A, read_number >> 8, read_number & 0xff}; + ssize_t err; + + err = mipi_dsi_dcs_write(dsi, 0xC1,payload, sizeof(payload)); + if (err < 0) + return err; + + return 0; +} +EXPORT_SYMBOL(mipi_dsi_dcs_write_c1); + static int mipi_dsi_drv_probe(struct device *dev) { struct mipi_dsi_driver *drv = to_mipi_dsi_driver(dev->driver); diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c index 1c5b5ce1fd7f4861f40064cfcaf73963ebd0fcee..a67a0f21445f5d606841bfea02ef259aac4bf758 100644 --- a/drivers/gpu/drm/drm_sysfs.c +++ b/drivers/gpu/drm/drm_sysfs.c @@ -21,10 +21,24 @@ #include #include #include "drm_internal.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include #define to_drm_minor(d) dev_get_drvdata(d) #define to_drm_connector(d) dev_get_drvdata(d) +#define DSI_PANEL_SAMSUNG_S6E3HC2 0 +#define DSI_PANEL_SAMSUNG_S6E3FC2X01 1 +#define DSI_PANEL_SAMSUNG_SOFEF03F_M 2 +extern char gamma_para[2][413]; +extern char dsi_panel_name; /** * DOC: overview * @@ -43,6 +57,10 @@ static struct device_type drm_sysfs_device_minor = { .name = "drm_minor" }; +static struct input_dev *dc_mode_input_dev; +static struct proc_dir_entry *prEntry_dc; +static int dc_mode_report_enable; + struct class *drm_class; static char *drm_devnode(struct device *dev, umode_t *mode) @@ -52,6 +70,71 @@ static char *drm_devnode(struct device *dev, umode_t *mode) static CLASS_ATTR_STRING(version, S_IRUGO, "drm 1.1.0 20060810"); +static ssize_t dc_mode_event_num_read(struct file *file, char __user *user_buf, size_t count, loff_t *ppos) +{ + int ret = 0; + const char *devname = NULL; + struct input_handle *handle; + + if (!dc_mode_input_dev) + return count; + + list_for_each_entry(handle, &(dc_mode_input_dev->h_list), d_node) { + if (strncmp(handle->name, "event", 5) == 0) { + devname = handle->name; + break; + } + } + ret = simple_read_from_buffer(user_buf, count, ppos, devname, strlen(devname)); + return ret; +} + +static const struct file_operations dc_mode_event_num_fops = { + .read = dc_mode_event_num_read, + .open = simple_open, + .owner = THIS_MODULE, +}; + +static ssize_t dc_mode_report_enable_read(struct file *file, char __user *user_buf, size_t count, loff_t *ppos) +{ + ssize_t ret = 0; + char page[4]; + + pr_info("the dc_mode_report_enable is: %d\n", dc_mode_report_enable); + ret = snprintf(page, 4, "%d\n", dc_mode_report_enable); + ret = simple_read_from_buffer(user_buf, count, ppos, page, strlen(page)); + return ret; + +} + +static ssize_t dc_mode_report_enable_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos) +{ + char buf[8] = {0}; + + if (count > 2) + count = 2; + + if (copy_from_user(buf, buffer, count)) { + pr_err("%s: read proc input error.\n", __func__); + return count; + } + + if ('0' == buf[0]) + dc_mode_report_enable = 0; + else if ('1' == buf[0]) + dc_mode_report_enable = 1; + + + return count; +} + +static const struct file_operations dc_mode_report_enable_fops = { + .read = dc_mode_report_enable_read, + .write = dc_mode_report_enable_write, + .open = simple_open, + .owner = THIS_MODULE, +}; + /** * drm_sysfs_init - initialize sysfs helpers * @@ -65,6 +148,7 @@ static CLASS_ATTR_STRING(version, S_IRUGO, "drm 1.1.0 20060810"); int drm_sysfs_init(void) { int err; + struct proc_dir_entry *prEntry_tmp = NULL; drm_class = class_create(THIS_MODULE, "drm"); if (IS_ERR(drm_class)) @@ -76,8 +160,48 @@ int drm_sysfs_init(void) drm_class = NULL; return err; } - drm_class->devnode = drm_devnode; + + prEntry_dc = proc_mkdir("dc_for_sensor", NULL); + if (prEntry_dc == NULL) { + pr_err("Couldn't create dc_for_sensor directory\n"); + return 0; + } + + //create dc_mode_event_num + prEntry_tmp = proc_create("dc_mode_event_num", 0664, + prEntry_dc, &dc_mode_event_num_fops); + if (prEntry_tmp == NULL) { + pr_err("Couldn't create dc_mode_event_num_fops\n"); + return 0; + } + + //create dc_mode_report_enable + prEntry_tmp = proc_create("dc_mode_report_enable", 0666, + prEntry_dc, &dc_mode_report_enable_fops); + if (prEntry_tmp == NULL) { + pr_err("Couldn't create dc_mode_report_enable_fops\n"); + return 0; + } + + //create input event + dc_mode_input_dev = input_allocate_device(); + if (dc_mode_input_dev == NULL) { + pr_err("Failed to allocate dc mode input device\n"); + return 0; + } + + dc_mode_input_dev->name = "oneplus,dc_mode"; + + set_bit(EV_MSC, dc_mode_input_dev->evbit); + set_bit(MSC_RAW, dc_mode_input_dev->mscbit); + + if (input_register_device(dc_mode_input_dev)) { + pr_err("%s: Failed to register dc mode input device\n", __func__); + input_free_device(dc_mode_input_dev); + return 0; + } + return 0; } @@ -88,6 +212,9 @@ int drm_sysfs_init(void) */ void drm_sysfs_destroy(void) { + input_unregister_device(dc_mode_input_dev); + input_free_device(dc_mode_input_dev); + if (IS_ERR_OR_NULL(drm_class)) return; class_remove_file(drm_class, &class_attr_version.attr); @@ -228,17 +355,1009 @@ static ssize_t modes_show(struct device *device, return written; } +static ssize_t acl_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int acl_mode = 0; + + acl_mode = dsi_display_get_acl_mode(connector); + + ret = scnprintf(buf, PAGE_SIZE, "acl mode = %d\n" + "0--acl mode(off)\n" + "1--acl mode(5)\n" + "2--acl mode(10)\n" + "3--acl mode(15)\n", + acl_mode); + return ret; +} + +static ssize_t acl_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int acl_mode = 0; + + ret = kstrtoint(buf, 10, &acl_mode); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + ret = dsi_display_set_acl_mode(connector, acl_mode); + if (ret) + pr_err("set acl mode(%d) fail\n", acl_mode); + + return count; +} +static ssize_t hbm_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int hbm_mode = 0; + + hbm_mode = dsi_display_get_hbm_mode(connector); + + ret = scnprintf(buf, PAGE_SIZE, "hbm mode = %d\n" + "0--hbm mode(off)\n" + "1--hbm mode(XX)\n" + "2--hbm mode(XX)\n" + "3--hbm mode(XX)\n" + "4--hbm mode(XX)\n" + "5--hbm mode(670)\n", + hbm_mode); + return ret; +} + +static ssize_t hbm_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int hbm_mode = 0; + + ret = kstrtoint(buf, 10, &hbm_mode); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + ret = dsi_display_set_hbm_mode(connector, hbm_mode); + if (ret) + pr_err("set hbm mode(%d) fail\n", hbm_mode); + + return count; +} + +static ssize_t hbm_brightness_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int hbm_brightness = 0; + + hbm_brightness = dsi_display_get_hbm_brightness(connector); + + ret = scnprintf(buf, PAGE_SIZE, "%d\n", hbm_brightness); + return ret; +} + +static ssize_t hbm_brightness_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int hbm_brightness = 0; + + ret = kstrtoint(buf, 10, &hbm_brightness); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + ret = dsi_display_set_hbm_brightness(connector, hbm_brightness); + if (ret) + pr_err("set hbm brightness (%d) failed\n", hbm_brightness); + return count; +} + +static ssize_t op_friginer_print_hbm_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int op_hbm_mode = 0; + + op_hbm_mode = dsi_display_get_fp_hbm_mode(connector); + + ret = scnprintf(buf, PAGE_SIZE, "OP_FP mode = %d\n" + "0--finger-hbm mode(off)\n" + "1--finger-hbm mode(600)\n", + op_hbm_mode); + return ret; +} + +static ssize_t op_friginer_print_hbm_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int op_hbm_mode = 0; + + ret = kstrtoint(buf, 10, &op_hbm_mode); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + ret = dsi_display_set_fp_hbm_mode(connector, op_hbm_mode); + if (ret) + pr_err("set hbm mode(%d) fail\n", op_hbm_mode); + + return count; +} + +static ssize_t aod_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int aod_mode = 0; + + aod_mode = dsi_display_get_aod_mode(connector); + + ret = scnprintf(buf, PAGE_SIZE, "%d\n", aod_mode); + return ret; +} + +static ssize_t aod_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int aod_mode = 0; + + ret = kstrtoint(buf, 10, &aod_mode); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + ret = dsi_display_set_aod_mode(connector, aod_mode); + if (ret) + pr_err("set AOD mode(%d) fail\n", aod_mode); + return count; +} + +static ssize_t aod_disable_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int aod_disable = 0; + + aod_disable = dsi_display_get_aod_disable(connector); + + ret = scnprintf(buf, PAGE_SIZE, "AOD disable = %d\n" + "0--AOD enable\n" + "1--AOD disable\n", + aod_disable); + return ret; +} + +static ssize_t aod_disable_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int aod_disable = 0; + + ret = kstrtoint(buf, 10, &aod_disable); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + ret = dsi_display_set_aod_disable(connector, aod_disable); + if (ret) + pr_err("set AOD disable(%d) fail\n", aod_disable); + + return count; +} + +static ssize_t DCI_P3_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int dci_p3_mode = 0; + + dci_p3_mode = dsi_display_get_dci_p3_mode(connector); + + ret = scnprintf(buf, PAGE_SIZE, "dci-p3 mode = %d\n" + "0--dci-p3 mode Off\n" + "1--dci-p3 mode On\n", + dci_p3_mode); + return ret; +} + +static ssize_t DCI_P3_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int dci_p3_mode = 0; + + ret = kstrtoint(buf, 10, &dci_p3_mode); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + ret = dsi_display_set_dci_p3_mode(connector, dci_p3_mode); + if (ret) { + pr_err("set dci-p3 mode(%d) fail\n", dci_p3_mode); + } + return count; +} + +static ssize_t night_mode_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int night_mode = 0; + + night_mode = dsi_display_get_night_mode(connector); + + ret = scnprintf(buf, PAGE_SIZE, "night mode = %d\n" + "0--night mode Off\n" + "1--night mode On\n", + night_mode); + return ret; +} + +static ssize_t night_mode_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int night_mode = 0; + + ret = kstrtoint(buf, 10, &night_mode); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + ret = dsi_display_set_night_mode(connector, night_mode); + if (ret) { + pr_err("set night mode(%d) fail\n", night_mode); + } + return count; +} + +static ssize_t native_display_p3_mode_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int native_display_p3_mode = 0; + + native_display_p3_mode = dsi_display_get_native_display_p3_mode(connector); + + ret = scnprintf(buf, PAGE_SIZE, "native display p3 mode = %d\n" + "0--native display p3 mode Off\n" + "1--native display p3 mode On\n", + native_display_p3_mode); + return ret; +} + +static ssize_t native_display_p3_mode_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int native_display_p3_mode = 0; + + ret = kstrtoint(buf, 10, &native_display_p3_mode); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + ret = dsi_display_set_native_display_p3_mode(connector, native_display_p3_mode); + if (ret) { + pr_err("set native_display_p3 mode(%d) fail\n", native_display_p3_mode); + } + return count; +} +static ssize_t native_display_wide_color_mode_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int native_display_wide_color_mode = 0; + + native_display_wide_color_mode = dsi_display_get_native_display_wide_color_mode(connector); + + ret = scnprintf(buf, PAGE_SIZE, "native display wide color mode = %d\n" + "0--native display wide color mode Off\n" + "1--native display wide color mode On\n", + native_display_wide_color_mode); + return ret; +} + +static ssize_t native_display_loading_effect_mode_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int native_display_loading_effect_mode = 0; + + ret = kstrtoint(buf, 10, &native_display_loading_effect_mode); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + ret = dsi_display_set_native_loading_effect_mode(connector, native_display_loading_effect_mode); + if (ret) { + pr_err("set loading effect mode(%d) fail\n", native_display_loading_effect_mode); + } + return count; +} + +static ssize_t native_display_loading_effect_mode_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int native_display_loading_effect_mode = 0; + + native_display_loading_effect_mode = dsi_display_get_native_display_loading_effect_mode(connector); + + ret = scnprintf(buf, PAGE_SIZE, "native display loading effect mode = %d\n" + "0--native display loading effect mode Off\n" + "1--native display loading effect mode On\n", + native_display_loading_effect_mode); + return ret; +} + +static ssize_t native_display_customer_p3_mode_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int native_display_customer_p3_mode = 0; + + ret = kstrtoint(buf, 10, &native_display_customer_p3_mode); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + ret = dsi_display_set_customer_p3_mode(connector, native_display_customer_p3_mode); + if (ret) { + pr_err("set customer p3 mode(%d) fail\n", native_display_customer_p3_mode); + } + return count; +} + +static ssize_t native_display_customer_p3_mode_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int native_display_customer_p3_mode = 0; + + native_display_customer_p3_mode = dsi_display_get_customer_p3_mode(connector); + + ret = scnprintf(buf, PAGE_SIZE, "native display customer p3 mode = %d\n" + "0--native display customer p3 mode Off\n" + "1--native display customer p3 mode On\n", + native_display_customer_p3_mode); + return ret; +} +static ssize_t native_display_customer_srgb_mode_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int native_display_customer_srgb_mode = 0; + + ret = kstrtoint(buf, 10, &native_display_customer_srgb_mode); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + ret = dsi_display_set_customer_srgb_mode(connector, native_display_customer_srgb_mode); + if (ret) { + pr_err("set customer srgb mode(%d) fail\n", native_display_customer_srgb_mode); + } + return count; +} + +static ssize_t native_display_customer_srgb_mode_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int native_display_customer_srgb_mode = 0; + + native_display_customer_srgb_mode = dsi_display_get_customer_srgb_mode(connector); + + ret = scnprintf(buf, PAGE_SIZE, "native display customer srgb mode = %d\n" + "0--native display customer srgb mode Off\n" + "1--native display customer srgb mode On\n", + native_display_customer_srgb_mode); + return ret; +} + + +static ssize_t native_display_wide_color_mode_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int native_display_wide_color_mode = 0; + + ret = kstrtoint(buf, 10, &native_display_wide_color_mode); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + ret = dsi_display_set_native_display_wide_color_mode(connector, native_display_wide_color_mode); + if (ret) { + pr_err("set native_display_p3 mode(%d) fail\n", native_display_wide_color_mode); + } + return count; +} + +static ssize_t native_display_srgb_color_mode_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int native_display_srgb_color_mode = 0; + + native_display_srgb_color_mode = dsi_display_get_native_display_srgb_color_mode(connector); + + ret = scnprintf(buf, PAGE_SIZE, "native display srgb color mode = %d\n" + "0--native display srgb color mode Off\n" + "1--native display srgb color mode On\n", + native_display_srgb_color_mode); + return ret; +} + +static ssize_t native_display_srgb_color_mode_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int native_display_srgb_color_mode = 0; + + ret = kstrtoint(buf, 10, &native_display_srgb_color_mode); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + ret = dsi_display_set_native_display_srgb_color_mode(connector, native_display_srgb_color_mode); + if (ret) { + pr_err("set native_display_srgb mode(%d) fail\n", native_display_srgb_color_mode); + } + return count; +} + +static ssize_t gamma_test_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int gamma_test_flag = 0; + int panel_stage_info = 0; + int pvt_mp_panel_flag = 0; + + if (dsi_panel_name == DSI_PANEL_SAMSUNG_S6E3HC2) { + if ((gamma_para[0][18] == 0xFF) && (gamma_para[0][19] == 0xFF) && (gamma_para[0][20] == 0xFF)) { + gamma_test_flag = 0; + } + else { + gamma_test_flag = 1; + } + + panel_stage_info = dsi_display_get_stage_info(connector); + if ((0x07 == panel_stage_info) || (0x10 == panel_stage_info) || (0x11 == panel_stage_info)) { + pvt_mp_panel_flag = 1; + } + else { + pvt_mp_panel_flag = 0; + } + + ret = scnprintf(buf, PAGE_SIZE, "%d\n", (gamma_test_flag << 1) + pvt_mp_panel_flag); + return ret; + } + else { + ret = scnprintf(buf, PAGE_SIZE, "%d\n", 3); + pr_err("It is not S6E3HC2 panel!\n"); + return ret; + } +} + +static ssize_t panel_serial_number_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int panel_year = 0; + int panel_mon = 0; + int panel_day = 0; + int panel_hour = 0; + int panel_min = 0; + int panel_sec = 0; + int panel_code_info = 0; + int panel_stage_info = 0; + int panel_production_info = 0; + char * production_string_info = NULL; + char * stage_string_info = NULL; + int ret = 0; + + dsi_display_get_serial_number(connector); + + panel_year = dsi_display_get_serial_number_year(connector); + panel_mon = dsi_display_get_serial_number_mon(connector); + panel_day = dsi_display_get_serial_number_day(connector); + panel_hour = dsi_display_get_serial_number_hour(connector); + panel_min = dsi_display_get_serial_number_min(connector); + panel_sec = dsi_display_get_serial_number_sec(connector); + panel_code_info = dsi_display_get_code_info(connector); + panel_stage_info = dsi_display_get_stage_info(connector); + panel_production_info = dsi_display_get_production_info(connector); + + if (dsi_panel_name == DSI_PANEL_SAMSUNG_S6E3HC2) { + if (panel_code_info == 0xED) { + if (panel_stage_info == 0x02) + stage_string_info = "STAGE: EVT2"; + else if (panel_stage_info == 0x03) + stage_string_info = "STAGE: EVT2(NEW_DIMMING_SET)"; + else if (panel_stage_info == 0x99) + stage_string_info = "STAGE: EVT2(113MHZ_OSC)"; + else if (panel_stage_info == 0x04) + stage_string_info = "STAGE: DVT1"; + else if (panel_stage_info == 0x05) + stage_string_info = "STAGE: DVT2"; + else if (panel_stage_info == 0x06) + stage_string_info = "STAGE: DVT3"; + else if (panel_stage_info == 0x07) + stage_string_info = "STAGE: PVT(112MHZ_OSC)"; + else if (panel_stage_info == 0x10) + stage_string_info = "STAGE: PVT(113MHZ_OSC)"; + else if (panel_stage_info == 0x11) + stage_string_info = "STAGE: PVT(113MHZ_OSC+X_TALK_IMPROVEMENT)"; + else + stage_string_info = "STAGE: UNKNOWN"; + + if (panel_production_info == 0x0C) + production_string_info = "TPIC: LSI\nCOVER: JNTC\nOTP_GAMMA: 90HZ"; + else if (panel_production_info == 0x0E) + production_string_info = "TPIC: LSI\nCOVER: LENS\nOTP_GAMMA: 90HZ"; + else if (panel_production_info == 0x1C) + production_string_info = "TPIC: STM\nCOVER: JNTC\nOTP_GAMMA: 90HZ"; + else if (panel_production_info == 0x6C) + production_string_info = "TPIC: LSI\nCOVER: JNTC\nOTP_GAMMA: 60HZ"; + else if (panel_production_info == 0x6E) + production_string_info = "TPIC: LSI\nCOVER: LENS\nOTP_GAMMA: 60HZ"; + else if (panel_production_info == 0x1E) + production_string_info = "TPIC: STM\nCOVER: LENS\nOTP_GAMMA: 90HZ"; + else if (panel_production_info == 0x0D) + production_string_info = "TPIC: LSI\nID3: 0x0D\nOTP_GAMMA: 90HZ"; + else + production_string_info = "TPIC: UNKNOWN\nCOVER: UNKNOWN\nOTP_GAMMA: UNKNOWN"; + + ret = scnprintf(buf, PAGE_SIZE, "%04d/%02d/%02d %02d:%02d:%02d\n%s\n%s\nID: %02X %02X %02X\n", + panel_year, panel_mon, panel_day, panel_hour, panel_min, panel_sec, + stage_string_info, production_string_info, panel_code_info, + panel_stage_info, panel_production_info); + } + + if (panel_code_info == 0xEE) { + if (panel_stage_info == 0x12) + stage_string_info = "STAGE: T0/EVT1"; + else if (panel_stage_info == 0x13) + stage_string_info = "STAGE: EVT2"; + else if (panel_stage_info == 0x14) + stage_string_info = "STAGE: EVT2"; + else if (panel_stage_info == 0x15) + stage_string_info = "STAGE: EVT3"; + else if (panel_stage_info == 0x16) + stage_string_info = "STAGE: DVT"; + else if (panel_stage_info == 0x17) + stage_string_info = "STAGE: DVT"; + else if (panel_stage_info == 0x19) + stage_string_info = "STAGE: PVT"; + else + stage_string_info = "STAGE: UNKNOWN"; + + ret = scnprintf(buf, PAGE_SIZE, "%04d/%02d/%02d %02d:%02d:%02d\n%s\nID: %02X %02X %02X\n", + panel_year, panel_mon, panel_day, panel_hour, panel_min, panel_sec, + stage_string_info, production_string_info, panel_code_info, + panel_stage_info, panel_production_info); + } + + } else if (dsi_panel_name == DSI_PANEL_SAMSUNG_SOFEF03F_M) { + if (panel_stage_info == 0x01) + stage_string_info = "STAGE: T0"; + else if (panel_stage_info == 0x21) + stage_string_info = "STAGE: EVT1"; + else if (panel_stage_info == 0x22) + stage_string_info = "STAGE: EVT2"; + else if (panel_stage_info == 0x24) + stage_string_info = "STAGE: DVT1-1"; + else if (panel_stage_info == 0x26) + stage_string_info = "STAGE: DVT1-2"; + else if (panel_stage_info == 0x25) + stage_string_info = "STAGE: DVT2"; + else if (panel_stage_info == 0x28) + stage_string_info = "STAGE: DVT3"; + else if (panel_stage_info == 0x27) + stage_string_info = "STAGE: PVT/MP"; + + ret = scnprintf(buf, PAGE_SIZE, "%04d/%02d/%02d %02d:%02d:%02d\n%s\nID: %02X %02X %02X\n", + panel_year, panel_mon, panel_day, panel_hour, panel_min, panel_sec, stage_string_info, + panel_code_info, panel_stage_info, panel_production_info); + } + else { + ret = scnprintf(buf, PAGE_SIZE, "%04d/%02d/%02d %02d:%02d:%02d\n", + panel_year, panel_mon, panel_day, panel_hour, panel_min, panel_sec); + } + + pr_err("panel year = %d, mon = %d, day = %d, hour = %d, min = %d\n", + panel_year, panel_mon, panel_day, panel_hour, panel_min); + + return ret; +} + +static ssize_t panel_serial_number_AT_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + + int ret = 0; + uint64_t serial_number = 0; + + ret = scnprintf(buf, PAGE_SIZE, "%llu\n",dsi_display_get_serial_number_id(serial_number)); + + return ret; +} + +static ssize_t dsi_on_command_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + + ret = dsi_display_get_dsi_on_command(connector, buf); + + return ret; +} + +static ssize_t dsi_on_command_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + + ret = dsi_display_update_dsi_on_command(connector, buf, count); + if (ret) + pr_err("Failed to update dsi on command, ret=%d\n", ret); + + return count; +} + +static ssize_t dsi_panel_command_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + + ret = dsi_display_get_dsi_panel_command(connector, buf); + + return ret; +} + +static ssize_t dsi_panel_command_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + + ret = dsi_display_update_dsi_panel_command(connector, buf, count); + if (ret) + pr_err("Failed to update dsi panel command, ret=%d\n", ret); + + return count; +} + +static ssize_t dsi_seed_command_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + + ret = dsi_display_get_dsi_seed_command(connector, buf); + + return ret; +} + +static ssize_t dsi_seed_command_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + + ret = dsi_display_update_dsi_seed_command(connector, buf, count); + if (ret) + pr_err("Failed to update dsi seed command, ret=%d\n", ret); + + return count; +} + +int current_freq = 0; +static ssize_t dynamic_dsitiming_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int ret = 0; + + ret = scnprintf(buf, PAGE_SIZE, "current_freq = %d\n", + current_freq); + return ret; +} + +static ssize_t dynamic_dsitiming_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + int ret = 0; + int freq_value = 0; + + ret = kstrtoint(buf, 10, &freq_value); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + current_freq = freq_value; + + pr_err("freq setting=%d\n", current_freq); + + if (ret) { + pr_err("set dsi freq (%d) fail\n", current_freq); + } + return count; +} + +extern u32 mode_fps; +static ssize_t dynamic_fps_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int ret = 0; + + ret = scnprintf(buf, PAGE_SIZE, "%d\n", mode_fps); + + return ret; +} + +static ssize_t panel_mismatch_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int wrong_panel = 0; + + dsi_display_panel_mismatch_check(connector); + + wrong_panel = dsi_display_panel_mismatch(connector); + ret = scnprintf(buf, PAGE_SIZE, "panel mismatch = %d\n" + "0--(panel match)\n" + "1--(panel mismatch)\n", + wrong_panel); + return ret; +} + +int oneplus_panel_alpha =0; +int oneplus_force_screenfp = 0; +int op_dimlayer_bl_enable = 0; +int op_dp_enable = 0; +int op_dither_enable = 0; +extern int oneplus_get_panel_brightness_to_alpha(void); + +static ssize_t oneplus_display_get_dim_alpha(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", oneplus_get_panel_brightness_to_alpha()); +} + +static ssize_t oneplus_display_set_dim_alpha(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + sscanf(buf, "%d", &oneplus_panel_alpha); + return count; +} + +static ssize_t oneplus_display_get_forcescreenfp(struct device *dev, + struct device_attribute *attr, char *buf) +{ + + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + oneplus_force_screenfp = dsi_display_get_fp_hbm_mode(connector); + + ret = scnprintf(buf, PAGE_SIZE, "OP_FP mode = %d\n" + "0--finger-hbm mode(off)\n" + "1--finger-hbm mode(600)\n", + oneplus_force_screenfp); + return sprintf(buf, "%d\n", oneplus_force_screenfp); + +} + +static ssize_t oneplus_display_set_forcescreenfp(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + //sscanf(buf, "%x", &oneplus_force_screenfp); + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + ret = kstrtoint(buf, 10, &oneplus_force_screenfp); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + ret = dsi_display_set_fp_hbm_mode(connector, oneplus_force_screenfp); + if (ret) + pr_err("set hbm mode(%d) fail\n", oneplus_force_screenfp); + return count; +} + + +static ssize_t op_display_get_dimlayer_enable(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", op_dimlayer_bl_enable); +} + +static ssize_t op_display_set_dimlayer_enable(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + sscanf(buf, "%d", &op_dimlayer_bl_enable); + + pr_err("op_dimlayer_bl_enable : %d\n", op_dimlayer_bl_enable); + + if (dc_mode_report_enable) { + input_event(dc_mode_input_dev, EV_MSC, MSC_RAW, op_dimlayer_bl_enable); + input_sync(dc_mode_input_dev); + } + + return count; +} + +static ssize_t op_display_get_dither_enable(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", op_dither_enable); +} + +static ssize_t op_display_set_dither_enable(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + sscanf(buf, "%d", &op_dither_enable); + + return count; +} + +static ssize_t op_display_get_dp_enable(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", op_dp_enable); +} + +static ssize_t op_display_set_dp_enable(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + sscanf(buf, "%d", &op_dp_enable); + + return count; +} + +extern ssize_t oneplus_display_notify_fp_press(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count); + +extern ssize_t oneplus_display_notify_dim(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count); + +extern ssize_t oneplus_display_notify_aod_hid(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count); static DEVICE_ATTR_RW(status); static DEVICE_ATTR_RO(enabled); static DEVICE_ATTR_RO(dpms); static DEVICE_ATTR_RO(modes); +static DEVICE_ATTR_RW(acl); +static DEVICE_ATTR_RW(hbm); +static DEVICE_ATTR_RW(hbm_brightness); +static DEVICE_ATTR_RW(op_friginer_print_hbm); +static DEVICE_ATTR_RW(aod); +static DEVICE_ATTR_RW(aod_disable); +static DEVICE_ATTR_RW(DCI_P3); +static DEVICE_ATTR_RW(night_mode); +static DEVICE_ATTR_RW(native_display_p3_mode); +static DEVICE_ATTR_RW(native_display_wide_color_mode); +static DEVICE_ATTR_RW(native_display_loading_effect_mode); +static DEVICE_ATTR_RW(native_display_srgb_color_mode); +static DEVICE_ATTR_RW(native_display_customer_p3_mode); +static DEVICE_ATTR_RW(native_display_customer_srgb_mode); +static DEVICE_ATTR_RO(gamma_test); +static DEVICE_ATTR_RO(panel_serial_number); +static DEVICE_ATTR_RO(panel_serial_number_AT); +static DEVICE_ATTR_RW(dsi_on_command); +static DEVICE_ATTR_RW(dsi_panel_command); +static DEVICE_ATTR_RW(dsi_seed_command); +static DEVICE_ATTR_RW(dynamic_dsitiming); +static DEVICE_ATTR_RO(panel_mismatch); +static DEVICE_ATTR_RO(dynamic_fps); +static DEVICE_ATTR(dim_alpha, S_IRUGO|S_IWUSR, oneplus_display_get_dim_alpha, oneplus_display_set_dim_alpha); +static DEVICE_ATTR(force_screenfp, S_IRUGO|S_IWUSR, oneplus_display_get_forcescreenfp, oneplus_display_set_forcescreenfp); +static DEVICE_ATTR(notify_fppress, S_IRUGO|S_IWUSR, NULL, oneplus_display_notify_fp_press); +static DEVICE_ATTR(notify_dim, S_IRUGO|S_IWUSR, NULL, oneplus_display_notify_dim); +static DEVICE_ATTR(notify_aod, S_IRUGO|S_IWUSR, NULL, oneplus_display_notify_aod_hid); +static DEVICE_ATTR(dimlayer_bl_en, S_IRUGO|S_IWUSR, op_display_get_dimlayer_enable, op_display_set_dimlayer_enable); +static DEVICE_ATTR(dp_en, S_IRUGO|S_IWUSR, op_display_get_dp_enable, op_display_set_dp_enable); +static DEVICE_ATTR(dither_en, S_IRUGO|S_IWUSR, op_display_get_dither_enable, op_display_set_dither_enable); static struct attribute *connector_dev_attrs[] = { &dev_attr_status.attr, &dev_attr_enabled.attr, &dev_attr_dpms.attr, &dev_attr_modes.attr, + &dev_attr_acl.attr, + &dev_attr_hbm.attr, + &dev_attr_hbm_brightness.attr, + &dev_attr_op_friginer_print_hbm.attr, + &dev_attr_aod.attr, + &dev_attr_aod_disable.attr, + &dev_attr_DCI_P3.attr, + &dev_attr_night_mode.attr, + &dev_attr_native_display_p3_mode.attr, + &dev_attr_native_display_wide_color_mode.attr, + &dev_attr_native_display_loading_effect_mode.attr, + &dev_attr_native_display_srgb_color_mode.attr, + &dev_attr_native_display_customer_p3_mode.attr, + &dev_attr_native_display_customer_srgb_mode.attr, + &dev_attr_gamma_test.attr, + &dev_attr_panel_serial_number.attr, + &dev_attr_panel_serial_number_AT.attr, + &dev_attr_dsi_on_command.attr, + &dev_attr_dsi_panel_command.attr, + &dev_attr_dsi_seed_command.attr, + &dev_attr_dynamic_dsitiming.attr, + &dev_attr_panel_mismatch.attr, + &dev_attr_force_screenfp.attr, + &dev_attr_dim_alpha.attr, + &dev_attr_dynamic_fps.attr, + &dev_attr_notify_fppress.attr, + &dev_attr_notify_dim.attr, + &dev_attr_notify_aod.attr, + &dev_attr_dimlayer_bl_en.attr, + &dev_attr_dp_en.attr, + &dev_attr_dither_en.attr, NULL }; diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index aa832242ffab3b1b55988c3100e8a1d4643b5cff..85f348c954581e07f1520600836caebae9315b12 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -85,7 +85,6 @@ msm_drm-$(CONFIG_DRM_MSM_MDP5) += mdp/mdp_format.o \ msm_drm-$(CONFIG_DRM_SDE_RSC) += sde_rsc.o \ sde_rsc_hw.o \ - sde_rsc_hw_v3.o \ # use drm gpu driver only if qcom_kgsl driver not available ifneq ($(CONFIG_QCOM_KGSL),y) diff --git a/drivers/gpu/drm/msm/dp/dp_audio.c b/drivers/gpu/drm/msm/dp/dp_audio.c index 649b5c761b2f49dc98cb851a451fdb2970a61b0b..1813012412ad6337387904c2d269abaa2f8f771a 100644 --- a/drivers/gpu/drm/msm/dp/dp_audio.c +++ b/drivers/gpu/drm/msm/dp/dp_audio.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -31,7 +31,7 @@ struct dp_audio_private { struct dp_panel *panel; bool ack_enabled; - atomic_t session_on; + bool session_on; bool engine_on; u32 channels; @@ -302,11 +302,6 @@ static void dp_audio_isrc_sdp(struct dp_audio_private *audio) static void dp_audio_setup_sdp(struct dp_audio_private *audio) { - if (!atomic_read(&audio->session_on)) { - pr_warn("session inactive\n"); - return; - } - /* always program stream 0 first before actual stream cfg */ audio->catalog->stream_id = DP_STREAM_0; audio->catalog->config_sdp(audio->catalog); @@ -328,11 +323,6 @@ static void dp_audio_setup_acr(struct dp_audio_private *audio) u32 select = 0; struct dp_catalog_audio *catalog = audio->catalog; - if (!atomic_read(&audio->session_on)) { - pr_warn("session inactive\n"); - return; - } - switch (audio->dp_audio.bw_code) { case DP_LINK_BW_1_62: select = 0; @@ -360,14 +350,10 @@ static void dp_audio_enable(struct dp_audio_private *audio, bool enable) { struct dp_catalog_audio *catalog = audio->catalog; - audio->engine_on = enable; - if (!atomic_read(&audio->session_on)) { - pr_warn("session inactive. enable=%d\n", enable); - return; - } - catalog->data = enable; catalog->enable(catalog); + + audio->engine_on = enable; } static struct dp_audio_private *dp_audio_get_data(struct platform_device *pdev) @@ -467,7 +453,7 @@ static int dp_audio_get_cable_status(struct platform_device *pdev, u32 vote) goto end; } - return atomic_read(&audio->session_on); + return audio->session_on; end: return rc; } @@ -729,7 +715,7 @@ static int dp_audio_on(struct dp_audio *dp_audio) ext = &audio->ext_audio_data; - atomic_set(&audio->session_on, 1); + audio->session_on = true; rc = dp_audio_config(audio, EXT_DISPLAY_CABLE_CONNECT); if (rc) @@ -771,7 +757,7 @@ static int dp_audio_off(struct dp_audio *dp_audio) end: dp_audio_config(audio, EXT_DISPLAY_CABLE_DISCONNECT); - atomic_set(&audio->session_on, 0); + audio->session_on = false; audio->engine_on = false; dp_audio_deregister_ext_disp(audio); diff --git a/drivers/gpu/drm/msm/dp/dp_aux.c b/drivers/gpu/drm/msm/dp/dp_aux.c index d60ee5471754542fea0f7687e281600260c78a7b..cb9b268f4dc684544284d0ba87df68c8a66d80cf 100644 --- a/drivers/gpu/drm/msm/dp/dp_aux.c +++ b/drivers/gpu/drm/msm/dp/dp_aux.c @@ -514,7 +514,7 @@ static ssize_t dp_aux_transfer_debug(struct drm_dp_aux *drm_aux, if (aux->read) { timeout = wait_for_completion_timeout(&aux->comp, HZ); if (!timeout) { - pr_err("read timeout 0x%x\n", msg->address); + pr_err("aux timeout for 0x%x\n", msg->address); atomic_set(&aux->aborted, 1); ret = -ETIMEDOUT; goto end; @@ -528,7 +528,7 @@ static ssize_t dp_aux_transfer_debug(struct drm_dp_aux *drm_aux, timeout = wait_for_completion_timeout(&aux->comp, HZ); if (!timeout) { - pr_err("write timeout 0x%x\n", msg->address); + pr_err("aux timeout for 0x%x\n", msg->address); atomic_set(&aux->aborted, 1); ret = -ETIMEDOUT; goto end; @@ -565,8 +565,6 @@ static ssize_t dp_aux_transfer_debug(struct drm_dp_aux *drm_aux, memset(msg->buffer, 0, msg->size); ret = msg->size; end: - if (ret == -ETIMEDOUT) - aux->dp_aux.state |= DP_STATE_AUX_TIMEOUT; aux->dp_aux.reg = 0xFFFF; aux->dp_aux.read = true; aux->dp_aux.size = 0; diff --git a/drivers/gpu/drm/msm/dp/dp_aux.h b/drivers/gpu/drm/msm/dp/dp_aux.h index bfce976da8d53b9184bf41e54fe882683407ad0b..d683241e36cf29220261fffecc5409ece5a80d03 100644 --- a/drivers/gpu/drm/msm/dp/dp_aux.h +++ b/drivers/gpu/drm/msm/dp/dp_aux.h @@ -30,7 +30,6 @@ #define DP_STATE_LINK_MAINTENANCE_STARTED BIT(9) #define DP_STATE_LINK_MAINTENANCE_COMPLETED BIT(10) #define DP_STATE_LINK_MAINTENANCE_FAILED BIT(11) -#define DP_STATE_AUX_TIMEOUT BIT(12) enum dp_aux_error { DP_AUX_ERR_NONE = 0, diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c index 856465d4932c3f483449e9d2cf46c2e8b2dfa383..036bf45e71c2ab734728f79a34c582c95f99dc26 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -761,7 +761,6 @@ static void dp_catalog_ctrl_config_ctrl(struct dp_catalog_ctrl *ctrl, u8 ln_cnt) cfg = dp_read(catalog->exe_mode, io_data, DP_CONFIGURATION_CTRL); cfg &= ~(BIT(4) | BIT(5)); cfg |= (ln_cnt - 1) << 4; - cfg &= ~BIT(10); dp_write(catalog->exe_mode, io_data, DP_CONFIGURATION_CTRL, cfg); cfg = dp_read(catalog->exe_mode, io_data, DP_MAINLINK_CTRL); diff --git a/drivers/gpu/drm/msm/dp/dp_debug.c b/drivers/gpu/drm/msm/dp/dp_debug.c index acb205dec57bdba44e87f6139a1a19c724ee01f9..cd57bb0202aa9bed7a842156eb375b0a3c74fc93 100644 --- a/drivers/gpu/drm/msm/dp/dp_debug.c +++ b/drivers/gpu/drm/msm/dp/dp_debug.c @@ -200,7 +200,8 @@ static ssize_t dp_debug_write_dpcd(struct file *file, goto bail; size = min_t(size_t, count, SZ_2K); - if (size < 4) + + if (size <= char_to_nib) goto bail; buf = kzalloc(size, GFP_KERNEL); @@ -230,8 +231,6 @@ static ssize_t dp_debug_write_dpcd(struct file *file, } size -= 4; - if (size == 0) - goto bail; dpcd_size = size / char_to_nib; data_len = dpcd_size; @@ -317,7 +316,6 @@ static ssize_t dp_debug_read_dpcd(struct file *file, debug->aux->dpcd_updated(debug->aux); } - len = min_t(size_t, count, len); if (!copy_to_user(user_buff, buf, len)) *ppos += len; @@ -649,7 +647,6 @@ static ssize_t dp_debug_max_pclk_khz_read(struct file *file, debug->dp_debug.max_pclk_khz, debug->parser->max_pclk_khz); - len = min_t(size_t, count, len); if (copy_to_user(user_buff, buf, len)) { kfree(buf); return -EFAULT; @@ -811,7 +808,6 @@ static ssize_t dp_debug_read_connected(struct file *file, len += snprintf(buf, SZ_8, "%d\n", debug->hpd->hpd_high); - len = min_t(size_t, count, len); if (copy_to_user(user_buff, buf, len)) return -EFAULT; @@ -862,7 +858,6 @@ static ssize_t dp_debug_read_hdcp(struct file *file, len = sizeof(debug->dp_debug.hdcp_status); - len = min_t(size_t, count, len); if (copy_to_user(user_buff, debug->dp_debug.hdcp_status, len)) return -EFAULT; @@ -926,7 +921,6 @@ static ssize_t dp_debug_read_edid_modes(struct file *file, } mutex_unlock(&connector->dev->mode_config.mutex); - len = min_t(size_t, count, len); if (copy_to_user(user_buff, buf, len)) { kfree(buf); rc = -EFAULT; @@ -1002,7 +996,6 @@ static ssize_t dp_debug_read_edid_modes_mst(struct file *file, } mutex_unlock(&connector->dev->mode_config.mutex); - len = min_t(size_t, count, len); if (copy_to_user(user_buff, buf, len)) { kfree(buf); rc = -EFAULT; @@ -1043,7 +1036,6 @@ static ssize_t dp_debug_read_mst_con_id(struct file *file, ret = snprintf(buf, max_size, "%u\n", debug->mst_con_id); len += ret; - len = min_t(size_t, count, len); if (copy_to_user(user_buff, buf, len)) { kfree(buf); rc = -EFAULT; @@ -1107,7 +1099,6 @@ static ssize_t dp_debug_read_mst_conn_info(struct file *file, } mutex_unlock(&debug->dp_debug.dp_mst_connector_list.lock); - len = min_t(size_t, count, len); if (copy_to_user(user_buff, buf, len)) { kfree(buf); rc = -EFAULT; @@ -1197,7 +1188,6 @@ static ssize_t dp_debug_read_info(struct file *file, char __user *user_buff, if (dp_debug_check_buffer_overflow(rc, &max_size, &len)) goto error; - len = min_t(size_t, count, len); if (copy_to_user(user_buff, buf, len)) goto error; @@ -1230,7 +1220,6 @@ static ssize_t dp_debug_bw_code_read(struct file *file, len += snprintf(buf + len, (SZ_4K - len), "max_bw_code = %d\n", debug->panel->max_bw_code); - len = min_t(size_t, count, len); if (copy_to_user(user_buff, buf, len)) { kfree(buf); return -EFAULT; @@ -1256,7 +1245,6 @@ static ssize_t dp_debug_tpg_read(struct file *file, len += snprintf(buf, SZ_8, "%d\n", debug->dp_debug.tpg_state); - len = min_t(size_t, count, len); if (copy_to_user(user_buff, buf, len)) return -EFAULT; @@ -1447,7 +1435,6 @@ static ssize_t dp_debug_read_hdr(struct file *file, goto error; } - len = min_t(size_t, count, len); if (copy_to_user(user_buff, buf, len)) { kfree(buf); rc = -EFAULT; @@ -1625,7 +1612,6 @@ static ssize_t dp_debug_read_dump(struct file *file, print_hex_dump(KERN_DEBUG, prefix, DUMP_PREFIX_NONE, 16, 4, buf, len, false); - len = min_t(size_t, count, len); if (copy_to_user(user_buff, buf, len)) return -EFAULT; diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 78fd2b693cb9000b4dc28b2cdd2cfb87ab9b317e..62c73ba93ba6ad1f723f97c9f3a68dc37734862b 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -974,16 +974,13 @@ static void dp_display_clean(struct dp_display_private *dp) dp_panel = dp->active_panels[idx]; - if (dp_panel->audio_supported) - dp_panel->audio->off(dp_panel->audio); - dp_display_stream_pre_disable(dp, dp_panel); dp_display_stream_disable(dp, dp_panel); dp_panel->deinit(dp_panel, 0); } dp->power_on = false; - dp->is_connected = false; + dp->ctrl->off(dp->ctrl); } diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_drm.c index 82ed2481562e0a03a79df7f193245dadae9fcca3..da04cb64ea603c5f8b0c2ae8c2df4fda89e29231 100644 --- a/drivers/gpu/drm/msm/dp/dp_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_drm.c @@ -432,7 +432,7 @@ int dp_connector_get_info(struct drm_connector *connector, return 0; } - +extern int op_dp_enable; enum drm_connector_status dp_connector_detect(struct drm_connector *conn, bool force, void *display) @@ -461,6 +461,12 @@ enum drm_connector_status dp_connector_detect(struct drm_connector *conn, conn->display_info.width_mm = info.width_mm; conn->display_info.height_mm = info.height_mm; + if (status == 1) + op_dp_enable = 1; + else + op_dp_enable = 0; + + pr_err("%s:op_dp_enable=%d\n", __func__, op_dp_enable); return status; } diff --git a/drivers/gpu/drm/msm/dp/dp_usbpd.c b/drivers/gpu/drm/msm/dp/dp_usbpd.c index a9da3219e247b4c34e0d311a6428d68760c6db0c..c5dfb5c722c303dcb3df6d6516335e6623193df7 100644 --- a/drivers/gpu/drm/msm/dp/dp_usbpd.c +++ b/drivers/gpu/drm/msm/dp/dp_usbpd.c @@ -321,7 +321,7 @@ static int dp_usbpd_validate_callback(u8 cmd, static int dp_usbpd_get_ss_lanes(struct dp_usbpd_private *pd) { int rc = 0; - int timeout = 250; + int timeout = 10; /* * By default, USB reserves two lanes for Super Speed. @@ -341,7 +341,7 @@ static int dp_usbpd_get_ss_lanes(struct dp_usbpd_private *pd) pr_warn("USB busy, retry\n"); /* wait for hw recommended delay for usb */ - msleep(20); + msleep(200); timeout--; } } diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c b/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c index 7f786eb8b731c55e51ac7d3c9ed7f93457e644a4..60371f37cf3c1af6829fc3602780ee3a476d011f 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c @@ -111,7 +111,6 @@ static void dsi_catalog_cmn_init(struct dsi_ctrl_hw *ctrl, break; case DSI_CTRL_VERSION_2_2: case DSI_CTRL_VERSION_2_3: - case DSI_CTRL_VERSION_2_4: ctrl->ops.phy_reset_config = dsi_ctrl_hw_22_phy_reset_config; ctrl->ops.config_clk_gating = dsi_ctrl_hw_22_config_clk_gating; ctrl->ops.get_cont_splash_status = @@ -176,7 +175,6 @@ int dsi_catalog_ctrl_setup(struct dsi_ctrl_hw *ctrl, case DSI_CTRL_VERSION_2_0: case DSI_CTRL_VERSION_2_2: case DSI_CTRL_VERSION_2_3: - case DSI_CTRL_VERSION_2_4: ctrl->phy_isolation_enabled = phy_isolation_enabled; dsi_catalog_cmn_init(ctrl, version); break; diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c index 47e34769345215c49d3adae4b059f22e0319ac1d..4fe76613df7a61eaec9695ce9eedc9b6b6d42d68 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c @@ -55,7 +55,6 @@ static const enum dsi_ctrl_version dsi_ctrl_v1_4 = DSI_CTRL_VERSION_1_4; static const enum dsi_ctrl_version dsi_ctrl_v2_0 = DSI_CTRL_VERSION_2_0; static const enum dsi_ctrl_version dsi_ctrl_v2_2 = DSI_CTRL_VERSION_2_2; static const enum dsi_ctrl_version dsi_ctrl_v2_3 = DSI_CTRL_VERSION_2_3; -static const enum dsi_ctrl_version dsi_ctrl_v2_4 = DSI_CTRL_VERSION_2_4; static const struct of_device_id msm_dsi_of_match[] = { { @@ -74,10 +73,6 @@ static const struct of_device_id msm_dsi_of_match[] = { .compatible = "qcom,dsi-ctrl-hw-v2.3", .data = &dsi_ctrl_v2_3, }, - { - .compatible = "qcom,dsi-ctrl-hw-v2.4", - .data = &dsi_ctrl_v2_4, - }, {} }; @@ -480,7 +475,6 @@ static int dsi_ctrl_init_regmap(struct platform_device *pdev, break; case DSI_CTRL_VERSION_2_2: case DSI_CTRL_VERSION_2_3: - case DSI_CTRL_VERSION_2_4: ptr = msm_ioremap(pdev, "disp_cc_base", ctrl->name); if (IS_ERR(ptr)) { pr_err("disp_cc base address not found for [%s]\n", @@ -583,7 +577,6 @@ static int dsi_ctrl_clocks_init(struct platform_device *pdev, if (IS_ERR(hs_link->byte_clk)) { rc = PTR_ERR(hs_link->byte_clk); pr_err("failed to get byte_clk, rc=%d\n", rc); - hs_link->byte_clk = NULL; goto fail; } @@ -591,7 +584,6 @@ static int dsi_ctrl_clocks_init(struct platform_device *pdev, if (IS_ERR(hs_link->pixel_clk)) { rc = PTR_ERR(hs_link->pixel_clk); pr_err("failed to get pixel_clk, rc=%d\n", rc); - hs_link->pixel_clk = NULL; goto fail; } @@ -599,7 +591,6 @@ static int dsi_ctrl_clocks_init(struct platform_device *pdev, if (IS_ERR(lp_link->esc_clk)) { rc = PTR_ERR(lp_link->esc_clk); pr_err("failed to get esc_clk, rc=%d\n", rc); - lp_link->esc_clk = NULL; goto fail; } @@ -613,7 +604,6 @@ static int dsi_ctrl_clocks_init(struct platform_device *pdev, if (IS_ERR(rcg->byte_clk)) { rc = PTR_ERR(rcg->byte_clk); pr_err("failed to get byte_clk_rcg, rc=%d\n", rc); - rcg->byte_clk = NULL; goto fail; } @@ -621,7 +611,6 @@ static int dsi_ctrl_clocks_init(struct platform_device *pdev, if (IS_ERR(rcg->pixel_clk)) { rc = PTR_ERR(rcg->pixel_clk); pr_err("failed to get pixel_clk_rcg, rc=%d\n", rc); - rcg->pixel_clk = NULL; goto fail; } @@ -854,7 +843,6 @@ static int dsi_ctrl_update_link_freqs(struct dsi_ctrl *dsi_ctrl, if (config->bit_clk_rate_hz_override == 0) { if (config->panel_mode == DSI_OP_CMD_MODE) { h_period = DSI_H_ACTIVE_DSC(timing); - h_period += timing->overlap_pixels; v_period = timing->v_active; do_div(refresh_rate, timing->mdp_transfer_time_us); @@ -1110,6 +1098,38 @@ int dsi_message_validate_tx_mode(struct dsi_ctrl *dsi_ctrl, return rc; } +#if 0 +static void print_cmd_desc(const struct mipi_dsi_msg *msg) +{ + + char buf[1024]; + int len = 0; + size_t i; + + /* Packet Info */ + len += snprintf(buf, sizeof(buf) - len, "%02x ", msg->type); + len += snprintf(buf + len, sizeof(buf) - len, "%02x ", + (msg->flags & MIPI_DSI_MSG_LASTCOMMAND) ? 1 : 0); /* Last bit */ + len += snprintf(buf + len, sizeof(buf) - len, "%02x ", msg->channel); + len += snprintf(buf + len, sizeof(buf) - len, "%02x ", + (unsigned int)msg->flags); + len += snprintf(buf + len, sizeof(buf) - len, "%02x ", 0); /* Delay */ + len += snprintf(buf + len, sizeof(buf) - len, "%02x ", + (unsigned int)msg->tx_len); + + /* Packet Payload */ + for (i = 0 ; i < msg->tx_len ; i++) { + len += snprintf(buf + len, sizeof(buf) - len, + "%02x ", msg->tx_buf[i]); + /* Break to prevent show too long command */ + if (i > 250) + break; + } + + printk(KERN_ERR"(%02d) %s\n", (unsigned int)msg->tx_len, buf); +} +#endif + static int dsi_message_tx(struct dsi_ctrl *dsi_ctrl, const struct mipi_dsi_msg *msg, u32 flags) @@ -1125,6 +1145,7 @@ static int dsi_message_tx(struct dsi_ctrl *dsi_ctrl, u8 *cmdbuf; struct dsi_mode_info *timing; struct dsi_ctrl_hw_ops dsi_hw_ops = dsi_ctrl->hw.ops; + //print_cmd_desc(msg); /* Select the tx mode to transfer the command */ dsi_message_setup_tx_mode(dsi_ctrl, msg->tx_len, &flags); @@ -2941,12 +2962,10 @@ int dsi_ctrl_update_host_config(struct dsi_ctrl *ctrl, pr_debug("[DSI_%d]Host config updated\n", ctrl->cell_index); memcpy(&ctrl->host_config, config, sizeof(ctrl->host_config)); - ctrl->mode_bounds.x = (ctrl->host_config.video_timing.h_active + - ctrl->host_config.video_timing.overlap_pixels) * - ctrl->horiz_index; + ctrl->mode_bounds.x = ctrl->host_config.video_timing.h_active * + ctrl->horiz_index; ctrl->mode_bounds.y = 0; - ctrl->mode_bounds.w = ctrl->host_config.video_timing.h_active + - ctrl->host_config.video_timing.overlap_pixels; + ctrl->mode_bounds.w = ctrl->host_config.video_timing.h_active; ctrl->mode_bounds.h = ctrl->host_config.video_timing.v_active; memcpy(&ctrl->roi, &ctrl->mode_bounds, sizeof(ctrl->mode_bounds)); ctrl->modeupdated = true; diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw.h b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw.h index 4446bba8f16ca5e291f44560afad0482ca83275f..aa6b52a9ee4e6491c45aa18511c7ac43bb5fc3a0 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw.h +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw.h @@ -36,7 +36,6 @@ * @DSI_CTRL_VERSION_2_0: DSI host v2.0 controller * @DSI_CTRL_VERSION_2_2: DSI host v2.2 controller * @DSI_CTRL_VERSION_2_3: DSI host v2.3 controller - * @DSI_CTRL_VERSION_2_4: DSI host v2.4 controller * @DSI_CTRL_VERSION_MAX: max version */ enum dsi_ctrl_version { @@ -45,7 +44,6 @@ enum dsi_ctrl_version { DSI_CTRL_VERSION_2_0, DSI_CTRL_VERSION_2_2, DSI_CTRL_VERSION_2_3, - DSI_CTRL_VERSION_2_4, DSI_CTRL_VERSION_MAX }; diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_cmn.c b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_cmn.c index 909a6840dcc72ebd15b150f78fffa90407ecfab3..725dbd101fb9d01db89f34bc654ed9cf8738a16c 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_cmn.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_cmn.c @@ -310,7 +310,7 @@ void dsi_ctrl_hw_cmn_set_video_timing(struct dsi_ctrl_hw *ctrl, reg |= 1; DSI_W32(ctrl, DSI_VIDEO_COMPRESSION_MODE_CTRL, reg); } else { - width = mode->h_active + mode->overlap_pixels; + width = mode->h_active; } hs_end = mode->h_sync_width; @@ -421,8 +421,8 @@ void dsi_ctrl_hw_cmn_setup_cmd_stream(struct dsi_ctrl_hw *ctrl, stride_final = roi->w * 3; height_final = roi->h; } else { - width_final = mode->h_active + mode->overlap_pixels; - stride_final = h_stride + mode->overlap_pixels * 3; + width_final = mode->h_active; + stride_final = h_stride; height_final = mode->v_active; } diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h b/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h index 213142263d58958e60a95840c947e2e11071901f..50fc239cce1d4163254d14baa0fa03b017bc57e7 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h @@ -288,6 +288,72 @@ enum dsi_cmd_set_type { DSI_CMD_SET_POST_TIMING_SWITCH, DSI_CMD_SET_QSYNC_ON, DSI_CMD_SET_QSYNC_OFF, + DSI_CMD_SET_HBM_BRIGHTNESS_ON, + DSI_CMD_SET_HBM_BRIGHTNESS_OFF, + DSI_CMD_SET_HBM_ON_1, + DSI_CMD_SET_HBM_ON_2, + DSI_CMD_SET_HBM_ON_3, + DSI_CMD_SET_HBM_ON_4, + DSI_CMD_SET_HBM_ON_5, + DSI_CMD_SET_HBM_OFF, + DSI_CMD_SET_PANEL_SERIAL_NUMBER, + DSI_CMD_SET_AOD_ON_1, + DSI_CMD_SET_AOD_ON_2, + DSI_CMD_SET_AOD_OFF, + DSI_CMD_AOD_OFF_HBM_ON_SETTING, + DSI_CMD_SET_AOD_OFF_NEW, + DSI_CMD_HBM_OFF_AOD_ON_SETTING, + DSI_CMD_SET_AOD_OFF_SAMSUNG, +// DSI_CMD_SET_SRGB_ON, +// DSI_CMD_SET_SRGB_OFF, + DSI_CMD_SET_DCI_P3_ON, + DSI_CMD_SET_DCI_P3_OFF, + DSI_CMD_SET_NIGHT_ON, + DSI_CMD_SET_NIGHT_OFF, + DSI_CMD_SET_PANEL_ID, + DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_ON, + DSI_CMD_SET_PANEL_ID1, + DSI_CMD_SET_PANEL_ID2, + DSI_CMD_SET_PANEL_ID3, + DSI_CMD_SET_PANEL_ID4, + DSI_CMD_SET_PANEL_ID5, + DSI_CMD_SET_PANEL_ID6, + DSI_CMD_SET_PANEL_ID7, + DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_OFF, + DSI_CMD_SET_ACL_MODE, + DSI_CMD_SET_LCDINFO_PRE, + DSI_CMD_SET_LCDINFO_POST, + DSI_CMD_SET_CODE_INFO, + DSI_CMD_SET_STAGE_INFO, + DSI_CMD_SET_PRODUCTION_INFO, + DSI_CMD_SET_ESD_LOGREAD_PREREAD, + DSI_CMD_SET_GAMMA_FLASH_PRE_READ_1, + DSI_CMD_SET_GAMMA_FLASH_PRE_READ_2, + DSI_CMD_SET_GAMMA_FLASH_READ_FB, + DSI_CMD_SET_LEVEL2_KEY_ENABLE, + DSI_CMD_SET_GAMMA_OTP_READ_C8_SMRPS, + DSI_CMD_SET_GAMMA_OTP_READ_C8, + DSI_CMD_SET_GAMMA_OTP_READ_C9_SMRPS, + DSI_CMD_SET_GAMMA_OTP_READ_C9, + DSI_CMD_SET_GAMMA_OTP_READ_B3_SMRPS, + DSI_CMD_SET_GAMMA_OTP_READ_B3, + DSI_CMD_SET_LEVEL2_KEY_DISABLE, + DSI_CMD_SET_NATIVE_DISPLAY_P3_ON, + DSI_CMD_SET_NATIVE_DISPLAY_P3_OFF, + DSI_CMD_SET_NATIVE_DISPLAY_WIDE_COLOR_ON, + DSI_CMD_SET_NATIVE_DISPLAY_WIDE_COLOR_OFF, + DSI_CMD_SET_NATIVE_DISPLAY_SRGB_COLOR_ON, + DSI_CMD_SET_NATIVE_DISPLAY_SRGB_COLOR_OFF, + DSI_CMD_SET_113MHZ_OSC_ON, + DSI_CMD_POST_ON_BACKLIGHT, + DSI_CMD_LOADING_EFFECT_ON, + DSI_CMD_LOADING_EFFECT_OFF, + DSI_CMD_LOADING_CUSTOMER_RGB_ON, + DSI_CMD_LOADING_CUSTOMER_RGB_OFF, + DSI_CMD_LOADING_CUSTOMER_P3_ON, + DSI_CMD_LOADING_CUSTOMER_P3_OFF, + DSI_CMD_SET_PANEL_COMMAND, + DSI_CMD_SET_SEED_COMMAND, DSI_CMD_SET_MAX }; @@ -392,7 +458,6 @@ struct dsi_panel_cmd_set { * @clk_rate_hz: DSI bit clock rate per lane in Hz. * @mdp_transfer_time_us: Specifies the mdp transfer time for command mode * panels in microseconds. - * @overlap_pixels: overlap pixels for certain panels. * @dsc_enabled: DSC compression enabled. * @dsc: DSC compression configuration. * @roi_caps: Panel ROI capabilities. @@ -414,7 +479,6 @@ struct dsi_mode_info { u32 refresh_rate; u64 clk_rate_hz; u32 mdp_transfer_time_us; - u32 overlap_pixels; bool dsc_enabled; struct msm_display_dsc_info *dsc; struct msm_roi_caps roi_caps; @@ -568,7 +632,6 @@ struct dsi_host_config { * @mdp_transfer_time_us: Specifies the mdp transfer time for command mode * panels in microseconds. * @clk_rate_hz: DSI bit clock per lane in hz. - * @overlap_pixels: overlap pixels for certain panels. * @topology: Topology selected for the panel * @dsc: DSC compression info * @dsc_enabled: DSC compression enabled @@ -585,7 +648,6 @@ struct dsi_display_mode_priv_info { u32 panel_prefill_lines; u32 mdp_transfer_time_us; u64 clk_rate_hz; - u32 overlap_pixels; struct msm_display_topology topology; struct msm_display_dsc_info dsc; diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c index a4c4e957f10b847e6c8dee035949fea38b523c9b..7fb11b8b024fd6e0ecbc74a31ab792b77407f5cd 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c @@ -31,6 +31,16 @@ #include "dsi_pwr.h" #include "sde_dbg.h" #include "dsi_parser.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include "../sde/sde_trace.h" +#include "dsi_parser.h" #define to_dsi_display(x) container_of(x, struct dsi_display, host) #define INT_BASE_10 10 @@ -44,10 +54,14 @@ #define DSI_CLOCK_BITRATE_RADIX 10 #define MAX_TE_SOURCE_ID 2 +#define WU_SEED_REGISTER 0x67 +#define UG_SEED_REGISTER 0xB1 + DEFINE_MUTEX(dsi_display_clk_mutex); static char dsi_display_primary[MAX_CMDLINE_PARAM_LEN]; static char dsi_display_secondary[MAX_CMDLINE_PARAM_LEN]; +static char SERIAL_NUMBER_flag = 0; static struct dsi_display_boot_param boot_displays[MAX_DSI_ACTIVE_DISPLAY] = { {.boot_param = dsi_display_primary}, {.boot_param = dsi_display_secondary}, @@ -58,6 +72,16 @@ static const struct of_device_id dsi_display_dt_match[] = { {} }; +static int esd_black_count; +static int esd_greenish_count; +static struct dsi_display *primary_display; +static struct input_dev* fresh_rate_input_dev = NULL; +static struct proc_dir_entry *proc_entry_display = NULL; +static int fresh_rate_report_enable = 0; +static bool fresh_rate_input_dev_init = false; + +#define to_dsi_bridge(x) container_of((x), struct dsi_bridge, base) + static void dsi_display_mask_ctrl_error_interrupts(struct dsi_display *display, u32 mask, bool enable) { @@ -183,6 +207,7 @@ void dsi_rect_intersect(const struct dsi_rect *r1, } } +extern int aod_layer_hide; int dsi_display_set_backlight(struct drm_connector *connector, void *display, u32 bl_lvl) { @@ -191,7 +216,7 @@ int dsi_display_set_backlight(struct drm_connector *connector, u32 bl_scale, bl_scale_ad; u64 bl_temp; int rc = 0; - + static int gamma_read_flag; if (dsi_display == NULL || dsi_display->panel == NULL) return -EINVAL; @@ -199,10 +224,130 @@ int dsi_display_set_backlight(struct drm_connector *connector, mutex_lock(&panel->panel_lock); if (!dsi_panel_initialized(panel)) { + panel->hbm_backlight = bl_lvl; + panel->bl_config.bl_level = bl_lvl; + pr_err("HBM_backight =%d\n",panel->hbm_backlight); rc = -EINVAL; goto error; } + + if (strcmp(dsi_display->panel->name, "samsung s6e3fc2x01 cmd mode dsi panel") == 0) { + if (bl_lvl != 0 && panel->bl_config.bl_level == 0) { + if (panel->naive_display_p3_mode) { + mdelay(20); + pr_err("Send DSI_CMD_SET_NATIVE_DISPLAY_P3_ON cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_NATIVE_DISPLAY_P3_ON); + } + if (panel->naive_display_wide_color_mode) { + mdelay(20); + pr_err("Send DSI_CMD_SET_NATIVE_DISPLAY_WIDE_COLOR_ON cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_NATIVE_DISPLAY_WIDE_COLOR_ON); + } + if (panel->naive_display_srgb_color_mode) { + mdelay(20); + pr_err("Send DSI_CMD_SET_NATIVE_DISPLAY_SRGB_COLOR_ON cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_NATIVE_DISPLAY_SRGB_COLOR_ON); + } + if (panel->naive_display_customer_srgb_mode) { + pr_err("Send DSI_CMD_LOADING_CUSTOMER_RGB_ON cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_LOADING_CUSTOMER_RGB_ON); + } else { + pr_err("Send DSI_CMD_LOADING_CUSTOMER_RGB_OFF cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_LOADING_CUSTOMER_RGB_OFF); + } + if (panel->naive_display_customer_p3_mode) { + pr_err("Send DSI_CMD_LOADING_CUSTOMER_P3_ON cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_LOADING_CUSTOMER_P3_ON); + } else { + pr_err("Send DSI_CMD_LOADING_CUSTOMER_P3_OFF cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_LOADING_CUSTOMER_P3_OFF); + } + } + } + + if (strcmp(dsi_display->panel->name, "samsung dsc cmd mode oneplus dsi panel") == 0) { + if (bl_lvl != 0 && panel->bl_config.bl_level == 0) { + if (panel->naive_display_p3_mode) { + mdelay(20); + pr_err("Send DSI_CMD_SET_NATIVE_DISPLAY_P3_ON cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_NATIVE_DISPLAY_P3_ON); + } + if (panel->naive_display_wide_color_mode) { + mdelay(20); + pr_err("Send DSI_CMD_SET_NATIVE_DISPLAY_WIDE_COLOR_ON cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_NATIVE_DISPLAY_WIDE_COLOR_ON); + } + if (panel->naive_display_srgb_color_mode) { + mdelay(20); + pr_err("Send DSI_CMD_SET_NATIVE_DISPLAY_SRGB_COLOR_ON cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_NATIVE_DISPLAY_SRGB_COLOR_ON); + } + if (panel->naive_display_loading_effect_mode) { + pr_err("Send DSI_CMD_LOADING_EFFECT_ON cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_LOADING_EFFECT_ON); + } else { + pr_err("Send DSI_CMD_LOADING_EFFECT_OFF cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_LOADING_EFFECT_OFF); + } + if (panel->naive_display_customer_srgb_mode) { + pr_err("Send DSI_CMD_LOADING_CUSTOMER_RGB_ON cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_LOADING_CUSTOMER_RGB_ON); + } else { + pr_err("Send DSI_CMD_LOADING_CUSTOMER_RGB_OFF cmds\n"); + //rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_LOADING_CUSTOMER_RGB_OFF); + } + if (panel->naive_display_customer_p3_mode) { + pr_err("Send DSI_CMD_LOADING_CUSTOMER_P3_ON cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_LOADING_CUSTOMER_P3_ON); + } else { + pr_err("Send DSI_CMD_LOADING_CUSTOMER_P3_OFF cmds\n"); + //rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_LOADING_CUSTOMER_P3_OFF); + } + } + } + + if (strcmp(dsi_display->panel->name, "samsung sofef03f_m fhd cmd mode dsc dsi panel") == 0) { + if (bl_lvl != 0 && panel->bl_config.bl_level == 0) { + if (panel->naive_display_p3_mode) { + msleep(20); + pr_err("Send DSI_CMD_SET_NATIVE_DISPLAY_P3_ON cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_NATIVE_DISPLAY_P3_ON); + } + if (panel->naive_display_wide_color_mode) { + msleep(20); + pr_err("Send DSI_CMD_SET_NATIVE_DISPLAY_WIDE_COLOR_ON cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_NATIVE_DISPLAY_WIDE_COLOR_ON); + } + if (panel->naive_display_srgb_color_mode) { + msleep(20); + pr_err("Send DSI_CMD_SET_NATIVE_DISPLAY_SRGB_COLOR_ON cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_NATIVE_DISPLAY_SRGB_COLOR_ON); + } + if (panel->naive_display_loading_effect_mode) { + pr_err("Send DSI_CMD_LOADING_EFFECT_ON cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_LOADING_EFFECT_ON); + } else { + pr_err("Send DSI_CMD_LOADING_EFFECT_OFF cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_LOADING_EFFECT_OFF); + } + if (panel->naive_display_customer_srgb_mode) { + pr_err("Send DSI_CMD_LOADING_CUSTOMER_RGB_ON cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_LOADING_CUSTOMER_RGB_ON); + } else { + pr_err("Send DSI_CMD_LOADING_CUSTOMER_RGB_OFF cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_LOADING_CUSTOMER_RGB_OFF); + } + if (panel->naive_display_customer_p3_mode) { + pr_err("Send DSI_CMD_LOADING_CUSTOMER_P3_ON cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_LOADING_CUSTOMER_P3_ON); + } else { + pr_err("Send DSI_CMD_LOADING_CUSTOMER_P3_OFF cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_LOADING_CUSTOMER_P3_OFF); + } + } + } + panel->bl_config.bl_level = bl_lvl; /* scale backlight */ @@ -237,6 +382,23 @@ int dsi_display_set_backlight(struct drm_connector *connector, error: mutex_unlock(&panel->panel_lock); + + if((strcmp(dsi_display->panel->name, "samsung dsc cmd mode oneplus dsi panel") == 0 + || strcmp(panel->name, "samsung s6e3fc2x01 cmd mode dsi panel") == 0 || + strcmp(panel->name, "samsung sofef03f_m fhd cmd mode dsc dsi panel") == 0) && (0 == SERIAL_NUMBER_flag)) { + dsi_display_get_serial_number_AT(connector); + } + + if ((gamma_read_flag < 2) && (strcmp(dsi_display->panel->name, "samsung dsc cmd mode oneplus dsi panel") == 0)) { + if (gamma_read_flag < 1) { + gamma_read_flag++; + } + else { + schedule_delayed_work(&dsi_display->panel->gamma_read_work, 0); + gamma_read_flag++; + } + } + return rc; } @@ -383,6 +545,96 @@ static void dsi_display_aspace_cb_locked(void *cb_data, bool is_detach) dsi_panel_release_panel_lock(display->panel); } +static irqreturn_t dsi_display_panel_err_flag_irq_handler(int irq, void *data) +{ + struct dsi_display *display = (struct dsi_display *)data; + /* + * This irq handler is used for sole purpose of identifying + * ESD attacks on panel and we can safely assume IRQ_HANDLED + * in case of display not being initialized yet + */ + if ((!display) || (!display->panel->is_err_flag_irq_enabled) || (!display->panel->panel_initialized)) + return IRQ_HANDLED; + + pr_err("%s\n", __func__); + + if (!display->panel->err_flag_status) { + display->panel->err_flag_status = true; + cancel_delayed_work_sync(sde_esk_check_delayed_work); + schedule_delayed_work(sde_esk_check_delayed_work, 0); + pr_err("schedule sde_esd_check_delayed_work\n"); + } + + return IRQ_HANDLED; +} + +void dsi_display_change_err_flag_irq_status(struct dsi_display *display, + bool enable) +{ + if (!display) { + pr_err("Invalid params\n"); + return; + } + + if (!gpio_is_valid(display->panel->err_flag_gpio)) + return; + + /* Handle unbalanced irq enable/disbale calls */ + if (enable && !display->panel->is_err_flag_irq_enabled) { + enable_irq(gpio_to_irq(display->panel->err_flag_gpio)); + display->panel->is_err_flag_irq_enabled = true; + pr_err("enable err flag irq\n"); + } else if (!enable && display->panel->is_err_flag_irq_enabled) { + disable_irq(gpio_to_irq(display->panel->err_flag_gpio)); + display->panel->is_err_flag_irq_enabled = false; + pr_err("disable err flag irq\n"); + } +} +EXPORT_SYMBOL(dsi_display_change_err_flag_irq_status); + +static void dsi_display_register_err_flag_irq(struct dsi_display *display) +{ + int rc = 0; + struct platform_device *pdev; + struct device *dev; + unsigned int err_flag_irq; + + pdev = display->pdev; + if (!pdev) { + pr_err("invalid platform device\n"); + return; + } + + dev = &pdev->dev; + if (!dev) { + pr_err("invalid device\n"); + return; + } + + if (!gpio_is_valid(display->panel->err_flag_gpio)) { + pr_err("Failed to get err-flag-gpio\n"); + rc = -EINVAL; + return; + } + + err_flag_irq = gpio_to_irq(display->panel->err_flag_gpio); + + /* Avoid deferred spurious irqs with disable_irq() */ + irq_set_status_flags(err_flag_irq, IRQ_DISABLE_UNLAZY); + + rc = devm_request_irq(dev, err_flag_irq, dsi_display_panel_err_flag_irq_handler, + IRQF_TRIGGER_FALLING | IRQF_ONESHOT, + "ERR_FLAG_GPIO", display); + if (rc) { + pr_err("Err flag request_irq failed for ESD rc:%d\n", rc); + irq_clear_status_flags(err_flag_irq, IRQ_DISABLE_UNLAZY); + return; + } + + disable_irq(err_flag_irq); + display->panel->is_err_flag_irq_enabled = false; +} + static irqreturn_t dsi_display_panel_te_irq_handler(int irq, void *data) { struct dsi_display *display = (struct dsi_display *)data; @@ -708,12 +960,79 @@ static int dsi_display_validate_status(struct dsi_display_ctrl *ctrl, return rc; } +static int dsi_panel_tx_cmd_set_op(struct dsi_panel *panel, + enum dsi_cmd_set_type type) +{ + int rc = 0, i = 0; + ssize_t len; + struct dsi_cmd_desc *cmds; + u32 count; + enum dsi_cmd_set_state state; + struct dsi_display_mode *mode; + const struct mipi_dsi_host_ops *ops = panel->host->ops; + if (!panel || !panel->cur_mode) + return -EINVAL; + + + mode = panel->cur_mode; + + cmds = mode->priv_info->cmd_sets[type].cmds; + count = mode->priv_info->cmd_sets[type].count; + state = mode->priv_info->cmd_sets[type].state; + + if (count == 0) { + pr_debug("[%s] No commands to be sent for state(%d)\n", + panel->name, type); + goto error; + } + for (i = 0; i < count; i++) { + if (state == DSI_CMD_SET_STATE_LP) + cmds->msg.flags |= MIPI_DSI_MSG_USE_LPM; + + if (cmds->last_command) + cmds->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + + len = ops->transfer(panel->host, &cmds->msg); + if (len < 0) { + rc = len; + pr_err("failed to set cmds(%d), rc=%d\n", type, rc); + goto error; + } + if (cmds->post_wait_ms) + usleep_range(cmds->post_wait_ms*1000, + ((cmds->post_wait_ms*1000)+10)); + cmds++; + } +error: + return rc; +} + static int dsi_display_status_reg_read(struct dsi_display *display) { int rc = 0, i; struct dsi_display_ctrl *m_ctrl, *ctrl; - - pr_debug(" ++\n"); + struct dsi_display_mode *mode; + u32 flags = 0; + u32 count = 0; + struct dsi_panel *panel = NULL; + struct dsi_cmd_desc *cmds1; + struct dsi_cmd_desc *cmds2; + struct dsi_cmd_desc *cmds3; + struct dsi_cmd_desc *cmds4; + struct dsi_cmd_desc *cmds5; + struct dsi_cmd_desc *cmds6; + struct dsi_cmd_desc *cmds7; + u8 temp_buffer_1[1] = {0}; + u8 temp_buffer_2[1] = {0}; + u8 temp_buffer_3[1] = {0}; + u8 temp_buffer_4[1] = {0}; + u8 temp_buffer_5[2] = {0,}; + u8 temp_buffer_6[16] = {0,}; + u8 temp_buffer_7[34] = {0,}; + u8 register_0a[1] = {0}; + u8 register_b6[1] = {0}; + u8 buf[48]; + memset(buf, 0, sizeof(buf)); m_ctrl = &display->ctrl[display->cmd_master_idx]; @@ -730,8 +1049,245 @@ static int dsi_display_status_reg_read(struct dsi_display *display) pr_err("cmd engine enable failed\n"); return -EPERM; } + mode = display->panel->cur_mode; + panel = display->panel; + + if (strcmp(panel->name, "samsung dsc cmd mode oneplus dsi panel") == 0) { + count = mode->priv_info->cmd_sets[DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_ON].count; + if (!count) { + pr_err("This panel does not read register\n"); + } else { + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_ON); + } + cmds1 = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_ID1].cmds; + if (cmds1->last_command) { + cmds1->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + cmds1->msg.rx_buf = buf; + cmds1->msg.rx_len = 1; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds1->msg, flags); + if (rc <= 0) + pr_err("rx cmd transfer failed rc=%d\n", rc); + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_OFF); + + memcpy(temp_buffer_1, cmds1->msg.rx_buf, 1); + memset(buf, 0, sizeof(buf)); + + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_ON); + cmds2 = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_ID2].cmds; + if (cmds2->last_command) { + cmds2->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + cmds2->msg.rx_buf = buf; + cmds2->msg.rx_len = 1; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds2->msg, flags); + if (rc <= 0) + pr_err("rx cmd transfer failed rc=%d\n", rc); + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_OFF); + + memcpy(temp_buffer_2, cmds2->msg.rx_buf, 1); + memset(buf, 0, sizeof(buf)); + + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_ON); + cmds3 = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_ID3].cmds; + if (cmds3->last_command) { + cmds3->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + cmds3->msg.rx_buf = buf; + cmds3->msg.rx_len = 1; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds3->msg, flags); + if (rc <= 0) + pr_err("rx cmd transfer failed rc=%d\n", rc); + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_OFF); + + memcpy(temp_buffer_3, cmds3->msg.rx_buf, 1); + + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_ON); + cmds4 = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_ID4].cmds; + if (cmds4->last_command) { + cmds4->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + cmds4->msg.rx_buf = buf; + cmds4->msg.rx_len = 1; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds4->msg, flags); + if (rc <= 0) + pr_err("rx cmd transfer failed rc=%d\n", rc); + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_OFF); + + memcpy(temp_buffer_4, cmds4->msg.rx_buf, 1); + memset(buf, 0, sizeof(buf)); + + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_ON); + cmds5 = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_ID5].cmds; + if (cmds5->last_command) { + cmds5->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + cmds5->msg.rx_buf = buf; + cmds5->msg.rx_len = 2; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds5->msg, flags); + if (rc <= 0) + pr_err("rx cmd transfer failed rc=%d\n", rc); + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_OFF); + + memcpy(temp_buffer_5, cmds5->msg.rx_buf, 2); + memset(buf, 0, sizeof(buf)); + + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_ON); + cmds6 = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_ID6].cmds; + if (cmds6->last_command) { + cmds6->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + cmds6->msg.rx_buf = buf; + cmds6->msg.rx_len = 16; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds6->msg, flags); + if (rc <= 0) + pr_err("rx cmd transfer failed rc=%d\n", rc); + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_OFF); + + memcpy(temp_buffer_6, cmds6->msg.rx_buf, 16); + memset(buf, 0, sizeof(buf)); + + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_ON); + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_SET_ESD_LOGREAD_PREREAD); + + cmds7 = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_ID7].cmds; + if (cmds7->last_command) { + cmds7->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + cmds7->msg.rx_buf = buf; + cmds7->msg.rx_len = 34; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds7->msg, flags); + if (rc <= 0) + pr_err("rx cmd transfer failed rc=%d\n", rc); + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_OFF); + + memcpy(temp_buffer_7, cmds7->msg.rx_buf, 34); + + if((temp_buffer_6[0] !=0x80) && (temp_buffer_2[0] != 0x80)) { + rc = -1; + } + else { + rc = 1; + } + } else if (strcmp(panel->name, "samsung s6e3fc2x01 cmd mode dsi panel") == 0) { + count = mode->priv_info->cmd_sets[DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_ON].count; + if (!count) { + pr_err("This panel does not read register\n"); + } else { + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_ON); + } + cmds1 = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_ID1].cmds; + if (cmds1->last_command) { + cmds1->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + cmds1->msg.rx_buf = buf; + cmds1->msg.rx_len = 1; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds1->msg, flags); + if (rc <= 0) + pr_err("rx cmd transfer failed rc=%d\n", rc); + memcpy(temp_buffer_1, cmds1->msg.rx_buf, 1); + count = mode->priv_info->cmd_sets[DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_ON].count; + if (!count) { + pr_err("This panel does not read register\n"); + } else { + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_ON); + } + cmds2 = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_ID6].cmds; + if (cmds2->last_command) { + cmds2->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + cmds2->msg.rx_buf = buf; + cmds2->msg.rx_len = 2; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds2->msg, flags); + if (rc <= 0) + pr_err("rx cmd transfer failed rc=%d\n", rc); + memcpy(temp_buffer_6, cmds2->msg.rx_buf, 2); + count = mode->priv_info->cmd_sets[DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_OFF].count; + if (!count) { + pr_err("This panel does not read register\n"); + } else { + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_OFF); + } + if(((temp_buffer_6[0] == 132) && (temp_buffer_6[1] == 0))||(temp_buffer_1[0] != 159)) + rc = -1; + else + rc = 1; + } else if (strcmp(panel->name, "samsung sofef03f_m fhd cmd mode dsc dsi panel") == 0) { + count = mode->priv_info->cmd_sets[DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_ON].count; + if (!count) { + pr_err("This panel does not support esd register reading\n"); + } else { + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_ON); + } + + flags = 0; + cmds1 = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_ID1].cmds; + if (cmds1->last_command) { + cmds1->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + cmds1->msg.rx_buf = register_0a; + cmds1->msg.rx_len = 1; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds1->msg, flags); + if (rc <= 0) + pr_err("rx cmd transfer failed rc=%d\n", rc); + + flags = 0; + cmds2 = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_ID2].cmds; + if (cmds2->last_command) { + cmds2->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + cmds2->msg.rx_buf = register_b6; + cmds2->msg.rx_len = 1; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds2->msg, flags); + if (rc <= 0) + pr_err("rx cmd transfer failed rc=%d\n", rc); + + count = mode->priv_info->cmd_sets[DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_OFF].count; + if (!count) { + pr_err("This panel does not support esd register reading\n"); + } else { + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_OFF); + } + + if ((register_0a[0] != 0x9c) || (register_b6[0] != 0x0a)) { + if (register_0a[0] != 0x9c) + esd_black_count++; + if (register_b6[0] != 0x0a) + esd_greenish_count++; + pr_err("%s:black_count=%d, greenish_count=%d, total=%d\n", + __func__, esd_black_count, esd_greenish_count, + esd_black_count + esd_greenish_count); + rc = -1; + } + else { + rc = 1; + } + } else { + rc = dsi_display_validate_status(m_ctrl, display->panel); + } - rc = dsi_display_validate_status(m_ctrl, display->panel); if (rc <= 0) { pr_err("[%s] read status failed on master,rc=%d\n", display->name, rc); @@ -755,6 +1311,7 @@ static int dsi_display_status_reg_read(struct dsi_display *display) } exit: dsi_display_cmd_engine_disable(display); + done: return rc; } @@ -803,6 +1360,10 @@ int dsi_display_check_status(struct drm_connector *connector, void *display, panel = dsi_display->panel; dsi_panel_acquire_panel_lock(panel); + + if (strcmp(dsi_display->panel->name, "samsung findx dsc cmd mode dsi panel") == 0){ + goto release_panel_lock; + } if (!panel->panel_initialized) { pr_debug("Panel not initialized\n"); @@ -832,6 +1393,15 @@ int dsi_display_check_status(struct drm_connector *connector, void *display, goto exit; } + if (dsi_display->panel->err_flag_status == true) { + esd_black_count++; + pr_err("%s:black_count=%d, greenish_count=%d, total=%d\n", + __func__, esd_black_count, esd_greenish_count, + esd_black_count + esd_greenish_count); + rc = -1; + goto exit; + } + dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, DSI_ALL_CLKS, DSI_CLK_ON); @@ -1069,12 +1639,15 @@ static bool dsi_display_get_cont_splash_status(struct dsi_display *display) } return true; } +extern int dsi_panel_set_aod_mode(struct dsi_panel *panel, int level); int dsi_display_set_power(struct drm_connector *connector, int power_mode, void *disp) { struct dsi_display *display = disp; int rc = 0; + struct msm_drm_notifier notifier_data; + int blank; if (!display || !display->panel) { pr_err("invalid display/panel\n"); @@ -1092,12 +1665,26 @@ int dsi_display_set_power(struct drm_connector *connector, if (display->panel->power_mode == SDE_MODE_DPMS_LP1 || display->panel->power_mode == SDE_MODE_DPMS_LP2) rc = dsi_panel_set_nolp(display->panel); + /*sned screen on cmd for TP start*/ + blank = MSM_DRM_BLANK_UNBLANK_CUST; + notifier_data.data = ␣ + notifier_data.id = connector_state_crtc_index; + msm_drm_notifier_call_chain(MSM_DRM_EARLY_EVENT_BLANK, + ¬ifier_data); + /*sned screen on cmd for TP end*/ break; case SDE_MODE_DPMS_OFF: + /*sned screen off cmd for TP start*/ + blank = MSM_DRM_BLANK_POWERDOWN_CUST; + notifier_data.data = ␣ + notifier_data.id = connector_state_crtc_index; + msm_drm_notifier_call_chain(MSM_DRM_EARLY_EVENT_BLANK, + ¬ifier_data); + /*sned screen off cmd for TP end*/ + break; default: return rc; } - pr_debug("Power mode transition from %d to %d %s", display->panel->power_mode, power_mode, rc ? "failed" : "successful"); @@ -3676,6 +4263,11 @@ static int dsi_display_res_init(struct dsi_display *display) goto error_ctrl_put; } + if (strcmp(display->panel->name, "samsung dsc cmd mode oneplus dsi panel") == 0) { + INIT_DELAYED_WORK(&display->panel->gamma_read_work, dsi_display_gamma_read_work); + pr_err("INIT_DELAYED_WORK: dsi_display_gamma_read_work\n"); + } + return 0; error_ctrl_put: for (i = i - 1; i >= 0; i--) { @@ -4300,7 +4892,6 @@ static int dsi_display_get_dfps_timing(struct dsi_display *display, struct dsi_display_mode per_ctrl_mode; struct dsi_mode_info *timing; struct dsi_ctrl *m_ctrl; - u32 overlap_pixels = 0; int rc = 0; @@ -4310,6 +4901,7 @@ static int dsi_display_get_dfps_timing(struct dsi_display *display, } m_ctrl = display->ctrl[display->clk_master_idx].ctrl; + dsi_panel_get_dfps_caps(display->panel, &dfps_caps); if (!dfps_caps.dfps_support) { pr_err("dfps not supported by panel\n"); @@ -4335,7 +4927,6 @@ static int dsi_display_get_dfps_timing(struct dsi_display *display, } /* TODO: Remove this direct reference to the dsi_ctrl */ timing = &per_ctrl_mode.timing; - overlap_pixels = per_ctrl_mode.priv_info->overlap_pixels; switch (dfps_caps.type) { case DSI_DFPS_IMMEDIATE_VFP: @@ -4353,7 +4944,7 @@ static int dsi_display_get_dfps_timing(struct dsi_display *display, curr_refresh_rate, timing->refresh_rate, DSI_V_TOTAL(timing), - DSI_H_TOTAL_DSC(timing) + overlap_pixels, + DSI_H_TOTAL_DSC(timing), timing->h_front_porch, &adj_mode->timing.h_front_porch); if (!rc) @@ -5095,6 +5686,8 @@ static int dsi_display_bind(struct device *dev, /* register te irq handler */ dsi_display_register_te_irq(display); + /* register err flag irq handler */ + dsi_display_register_err_flag_irq(display); goto error; @@ -5232,6 +5825,90 @@ static void dsi_display_firmware_display(const struct firmware *fw, pr_debug("success\n"); } +static ssize_t fresh_rate_read(struct file *file, char __user *user_buf, size_t count, loff_t *ppos) +{ + int ret = 0; + char fresh_rate[4] = {0}; + + if (mode_fps == 90) + strcpy(fresh_rate, "90"); + else if (mode_fps == 60) + strcpy(fresh_rate, "60"); + else + strcpy(fresh_rate, "-1"); + + pr_info("fresh_rate : %s\n", fresh_rate); + ret = simple_read_from_buffer(user_buf, count, ppos, fresh_rate, strlen(fresh_rate)); + return ret; +} + +static const struct file_operations fresh_rate_fops = { + .read = fresh_rate_read, + .open = simple_open, + .owner = THIS_MODULE, +}; + +static ssize_t fresh_rate_event_num_read(struct file *file, char __user *user_buf, size_t count, loff_t *ppos) +{ + int ret = 0; + const char *devname = NULL; + struct input_handle *handle; + if (!fresh_rate_input_dev) + return count; + list_for_each_entry(handle, &(fresh_rate_input_dev->h_list), d_node) { + if (strncmp(handle->name, "event", 5) == 0) { + devname = handle->name; + break; + } + } + ret = simple_read_from_buffer(user_buf, count, ppos, devname, strlen(devname)); + return ret; +} + +static const struct file_operations fresh_rate_event_num_fops = { + .read = fresh_rate_event_num_read, + .open = simple_open, + .owner = THIS_MODULE, +}; + +static ssize_t fresh_rate_enable_read(struct file *file, char __user *user_buf, size_t count, loff_t *ppos) +{ + ssize_t ret =0; + char page[4]; + + pr_info("the fresh_rate_report_enable is: %d\n", fresh_rate_report_enable); + ret = sprintf(page, "%d\n", fresh_rate_report_enable); + ret = simple_read_from_buffer(user_buf, count, ppos, page, strlen(page)); + return ret; + +} + +static ssize_t fresh_rate_enable_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos) +{ + char buf[8]={0}; + + if( count > 2) + count = 2; + if(copy_from_user(buf, buffer, count)){ + pr_err("%s: read proc input error.\n", __func__); + return count; + } + if('0' == buf[0]) { + fresh_rate_report_enable = 0; + } else if('1' == buf[0]){ + fresh_rate_report_enable = 1; + } + + return count; +} + +static const struct file_operations fresh_rate_enable_fops = { + .read = fresh_rate_enable_read, + .write = fresh_rate_enable_write, + .open = simple_open, + .owner = THIS_MODULE, +}; + int dsi_display_dev_probe(struct platform_device *pdev) { struct dsi_display *display = NULL; @@ -5242,6 +5919,15 @@ int dsi_display_dev_probe(struct platform_device *pdev) int i, count, rc = 0, index; bool firm_req = false; struct dsi_display_boot_param *boot_disp; + struct proc_dir_entry* proc_entry_tmp = NULL; + + if (fresh_rate_input_dev_init == false) { + proc_entry_display = proc_mkdir("fresh_rate_for_sensor", NULL); + if( proc_entry_display == NULL ){ + pr_err("Couldn't create fresh_rate_for_sensor directory\n"); + } + } + if (!pdev || !pdev->dev.of_node) { pr_err("pdev not found\n"); @@ -5331,12 +6017,61 @@ int dsi_display_dev_probe(struct platform_device *pdev) goto end; } + + if (fresh_rate_input_dev_init == false) { + //create fresh_rate + proc_entry_tmp = proc_create("fresh_rate", 0664, + proc_entry_display, &fresh_rate_fops); + if (proc_entry_tmp == NULL) { + pr_err("Couldn't create fresh_rate_fops\n"); + goto fresh_rate_report_failed; + } + + //create fresh_rate_event_num + proc_entry_tmp = proc_create("fresh_rate_event_num", 0664, + proc_entry_display, &fresh_rate_event_num_fops); + if (proc_entry_tmp == NULL) { + pr_err("Couldn't create fresh_rate_event_num_fops\n"); + goto fresh_rate_report_failed; + } + + //create fresh_rate_enable + proc_entry_tmp = proc_create("fresh_rate_enable", 0666, + proc_entry_display, &fresh_rate_enable_fops); + if (proc_entry_tmp == NULL) { + pr_err("Couldn't create fresh_rate_enable_fops\n"); + goto fresh_rate_report_failed; + } + + //create input event + fresh_rate_input_dev = input_allocate_device(); + if (fresh_rate_input_dev == NULL) { + pr_err("Failed to allocate fresh rate input device\n"); + goto fresh_rate_report_failed; + } + fresh_rate_input_dev->name = "oneplus,fresh_rate"; + + set_bit(EV_MSC, fresh_rate_input_dev->evbit); + set_bit(MSC_RAW, fresh_rate_input_dev->mscbit); + + if (input_register_device(fresh_rate_input_dev)) { + pr_err("%s: Failed to register fresh rate input device\n", __func__); + input_free_device(fresh_rate_input_dev); + goto fresh_rate_report_failed; + } + } + + fresh_rate_input_dev_init = true; + return 0; end: if (display) devm_kfree(&pdev->dev, display); - return rc; + +fresh_rate_report_failed: + pr_err("%s: fresh rate_report_failed\n", __func__); + return 0; } int dsi_display_dev_remove(struct platform_device *pdev) @@ -5358,6 +6093,12 @@ int dsi_display_dev_remove(struct platform_device *pdev) platform_set_drvdata(pdev, NULL); devm_kfree(&pdev->dev, display); + + //unregister_device + pr_err("unregister_device fresh_rate_input_dev...\n"); + input_unregister_device(fresh_rate_input_dev); + input_free_device(fresh_rate_input_dev); + return rc; } @@ -5567,6 +6308,7 @@ static int dsi_display_ext_get_mode_info(struct drm_connector *connector, if (!drm_mode || !mode_info) return -EINVAL; + SDE_EVT32(mode_info, ((unsigned long long)mode_info) >> 32, 0x9999); memset(mode_info, 0, sizeof(*mode_info)); mode_info->frame_rate = drm_mode->vrefresh; mode_info->vtotal = drm_mode->vtotal; @@ -6150,10 +6892,6 @@ int dsi_display_get_modes(struct dsi_display *display, panel_mode.pixel_clk_khz *= display->ctrl_count; } - /* pixel overlap is not supported for single dsi panels */ - if (display->ctrl_count == 1) - panel_mode.priv_info->overlap_pixels = 0; - start = array_idx; for (i = 0; i < num_dfps_rates; i++) { @@ -6189,6 +6927,7 @@ int dsi_display_get_modes(struct dsi_display *display, exit: *out_modes = display->modes; + primary_display = display; rc = 0; error: @@ -6302,16 +7041,16 @@ int dsi_display_find_mode(struct dsi_display *display, } /** - * dsi_display_validate_mode_change() - Validate mode change case. + * dsi_display_validate_mode_change() - Validate if varaible refresh case. * @display: DSI display handle. - * @cur_mode: Current mode. - * @adj_mode: Mode to be set. + * @cur_dsi_mode: Current DSI mode. + * @mode: Mode value structure to be validated. * MSM_MODE_FLAG_SEAMLESS_VRR flag is set if there * is change in fps but vactive and hactive are same. - * DSI_MODE_FLAG_DYN_CLK flag is set if there - * is change in clk but vactive and hactive are same. * Return: error code. */ + u32 mode_fps = 90; +EXPORT_SYMBOL(mode_fps); int dsi_display_validate_mode_change(struct dsi_display *display, struct dsi_display_mode *cur_mode, struct dsi_display_mode *adj_mode) @@ -6320,6 +7059,9 @@ int dsi_display_validate_mode_change(struct dsi_display *display, struct dsi_dfps_capabilities dfps_caps; struct dsi_dyn_clk_caps *dyn_clk_caps; + struct msm_drm_notifier notifier_data; + int dynamic_fps; + if (!display || !adj_mode) { pr_err("Invalid params\n"); return -EINVAL; @@ -6333,38 +7075,57 @@ int dsi_display_validate_mode_change(struct dsi_display *display, mutex_lock(&display->display_lock); if ((cur_mode->timing.v_active == adj_mode->timing.v_active) && - (cur_mode->timing.h_active == adj_mode->timing.h_active)) { + (cur_mode->timing.h_active == adj_mode->timing.h_active)) { /* dfps change use case */ if (cur_mode->timing.refresh_rate != adj_mode->timing.refresh_rate) { dsi_panel_get_dfps_caps(display->panel, &dfps_caps); - if (dfps_caps.dfps_support) { - pr_debug("Mode switch is seamless variable refresh\n"); - adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_VRR; - SDE_EVT32(cur_mode->timing.refresh_rate, - adj_mode->timing.refresh_rate, - cur_mode->timing.h_front_porch, - adj_mode->timing.h_front_porch); - } - } - /* dynamic clk change use case */ - if (cur_mode->pixel_clk_khz != adj_mode->pixel_clk_khz) { - dyn_clk_caps = &(display->panel->dyn_clk_caps); - if (dyn_clk_caps->dyn_clk_support) { - pr_debug("dynamic clk change detected\n"); - if (adj_mode->dsi_mode_flags - & DSI_MODE_FLAG_VRR) { - pr_err("dfps and dyn clk not supported in same commit\n"); - rc = -ENOTSUPP; - goto error; + if (mode_fps != adj_mode->timing.refresh_rate) { + mode_fps = adj_mode->timing.refresh_rate; + dynamic_fps = mode_fps; + notifier_data.data = &dynamic_fps; + notifier_data.id = MSM_DRM_PRIMARY_DISPLAY; + pr_err("set fps: %d, fresh_rate_report_enable : %d\n", dynamic_fps, fresh_rate_report_enable); + msm_drm_notifier_call_chain(MSM_DRM_EARLY_EVENT_BLANK, ¬ifier_data); + + if (fresh_rate_report_enable) { + input_event(fresh_rate_input_dev, EV_MSC, MSC_RAW, mode_fps); + input_sync(fresh_rate_input_dev); } - adj_mode->dsi_mode_flags |= - DSI_MODE_FLAG_DYN_CLK; - SDE_EVT32(cur_mode->pixel_clk_khz, - adj_mode->pixel_clk_khz); } + + if (!dfps_caps.dfps_support) { + pr_err("invalid mode dfps not supported\n"); + rc = -ENOTSUPP; + goto error; + } + pr_debug("Mode switch is seamless variable refresh\n"); + adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_VRR; + SDE_EVT32(cur_mode->timing.refresh_rate, + adj_mode->timing.refresh_rate, + cur_mode->timing.h_front_porch, + adj_mode->timing.h_front_porch); + } + + /* dynamic clk change use case */ + if (cur_mode->pixel_clk_khz != adj_mode->pixel_clk_khz) { + dyn_clk_caps = &(display->panel->dyn_clk_caps); + if (!dyn_clk_caps->dyn_clk_support) { + pr_err("dyn clk change not supported\n"); + rc = -ENOTSUPP; + goto error; + } + if (adj_mode->dsi_mode_flags & DSI_MODE_FLAG_VRR) { + pr_err("dfps and dyn clk not supported in same commit\n"); + rc = -ENOTSUPP; + goto error; + } + pr_debug("dynamic clk change detected\n"); + adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_DYN_CLK; + SDE_EVT32(cur_mode->pixel_clk_khz, + adj_mode->pixel_clk_khz); } } @@ -6474,6 +7235,8 @@ int dsi_display_set_mode(struct dsi_display *display, } memcpy(display->panel->cur_mode, &adj_mode, sizeof(adj_mode)); + + mode_fps = display->panel->cur_mode->timing.refresh_rate; error: mutex_unlock(&display->display_lock); return rc; @@ -7146,6 +7909,7 @@ int dsi_display_pre_kickoff(struct drm_connector *connector, int i; bool enable; + SDE_ATRACE_BEGIN("dsi_display_pre_kickoff"); /* check and setup MISR */ if (display->misr_enable) _dsi_display_setup_misr(display); @@ -7196,6 +7960,7 @@ int dsi_display_pre_kickoff(struct drm_connector *connector, mutex_unlock(&display->display_lock); } + SDE_ATRACE_END("dsi_display_pre_kickoff"); return rc; } @@ -7258,6 +8023,8 @@ int dsi_display_enable(struct dsi_display *display) /* Engine states and panel states are populated during splash * resource init and hence we return early */ + SDE_ATRACE_BEGIN("dsi_display_enable"); + if (display->is_cont_splash_enabled) { dsi_display_config_ctrl_for_cont_splash(display); @@ -7340,6 +8107,8 @@ int dsi_display_enable(struct dsi_display *display) error: mutex_unlock(&display->display_lock); SDE_EVT32(SDE_EVTLOG_FUNC_EXIT); + + SDE_ATRACE_END("dsi_display_enable"); return rc; } @@ -7451,75 +8220,2360 @@ int dsi_display_update_pps(char *pps_cmd, void *disp) return 0; } +int dsi_display_set_acl_mode(struct drm_connector *connector, int level) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; -int dsi_display_unprepare(struct dsi_display *display) + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + + mutex_lock(&dsi_display->display_lock); + + panel->acl_mode = level; + if (!dsi_panel_initialized(panel)) { + goto error; + } + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + rc = dsi_panel_set_acl_mode(panel, level); + if (rc) + pr_err("unable to set acl mode\n"); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } +error: + mutex_unlock(&dsi_display->display_lock); + return rc; +} + +int dsi_display_get_acl_mode(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->acl_mode; +} + +int dsi_display_get_gamma_para(struct dsi_display *dsi_display, struct dsi_panel *panel) +{ + int i = 0; + int j = 0; + int rc = 0; + int flags = 0; + char fb[13] = {0}; + //char c8[135] = {0}; + //char c9[180] = {0}; + char b3[47] = {0}; + char fb_temp[13] = {0}; + char c8_temp[135] = {0}; + char c9_temp[180] = {0}; + char b3_temp[47] = {0}; + char gamma_para_60hz[452] = {0}; + char gamma_para_backup[413] = {0}; + int check_sum_60hz = 0; + + struct dsi_cmd_desc *cmds; + struct dsi_display_mode *mode; + struct dsi_display_ctrl *m_ctrl; + + pr_err("%s start\n", __func__); + + m_ctrl = &dsi_display->ctrl[dsi_display->cmd_master_idx]; + if (!panel || !m_ctrl) + return -EINVAL; + + rc = dsi_display_cmd_engine_enable(dsi_display); + if (rc) { + pr_err("cmd engine enable failed\n"); + return -EINVAL; + } + + dsi_panel_acquire_panel_lock(panel); + mode = panel->cur_mode; + +/* Read 60hz gamma para */ + memcpy(gamma_para_backup, gamma_para[0], 413); + do { + check_sum_60hz = 0; + if (j > 0) { + pr_err("Failed to read the 60hz gamma parameters %d!", j); + for (i = 0; i < 52; i++) { + if (i != 51) { + pr_err("[60hz][%d]0x%02X,[%d]0x%02X,[%d]0x%02X,[%d]0x%02X,[%d]0x%02X,[%d]0x%02X,[%d]0x%02X,[%d]0x%02X", + i*8, gamma_para[0][i*8], i*8+1, gamma_para[0][i*8+1], i*8+2, gamma_para[0][i*8+2], i*8+3, gamma_para[0][i*8+3], i*8+4, gamma_para[0][i*8+4], + i*8+5, gamma_para[0][i*8+5], i*8+6, gamma_para[0][i*8+6], i*8+7, gamma_para[0][i*8+7]); + } + else { + pr_err("[60hz][%d]0x%02X,[%d]0x%02X,[%d]0x%02X,[%d]0x%02X,[%d]0x%02X", + i*8, gamma_para[0][i*8], i*8+1, gamma_para[0][i*8+1], i*8+2, gamma_para[0][i*8+2], i*8+3, gamma_para[0][i*8+3], i*8+4, gamma_para[0][i*8+4]); + } + } + mdelay(1000); + } + for(i = 0; i < 452; i++) + { + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_GAMMA_FLASH_PRE_READ_1); + if (rc) { + pr_err("Failed to send DSI_CMD_SET_GAMMA_FLASH_PRE_READ_1 command\n"); + goto error; + } + + rc = dsi_panel_gamma_read_address_setting(panel, i); + if (rc) { + pr_err("Failed to set gamma read address\n"); + goto error; + } + + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_GAMMA_FLASH_PRE_READ_2); + if (rc) { + pr_err("Failed to send DSI_CMD_SET_GAMMA_FLASH_PRE_READ_2 command\n"); + goto error; + } + + flags = 0; + cmds = mode->priv_info->cmd_sets[DSI_CMD_SET_GAMMA_FLASH_READ_FB].cmds; + if (cmds->last_command) { + cmds->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + if (!m_ctrl->ctrl->vaddr) + goto error; + cmds->msg.rx_buf = fb_temp; + cmds->msg.rx_len = 13; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds->msg, flags); + if (rc <= 0) { + pr_err("Failed to read DSI_CMD_SET_GAMMA_FLASH_READ_FB\n"); + goto error; + } + memcpy(fb, cmds->msg.rx_buf, 13); + + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_LEVEL2_KEY_DISABLE); + if (rc) { + pr_err("Failed to send DSI_CMD_SET_LEVEL2_KEY_DISABLE command\n"); + goto error; + } + + if (i < 135) { + gamma_para[0][i+18] = fb[12]; + } + else if (i < 315) { + gamma_para[0][i+26] = fb[12]; + } + else if (i < 360) { + gamma_para[0][i+43] = fb[12]; + } + + gamma_para_60hz[i] = fb[12]; + if (i < 449) { + check_sum_60hz = gamma_para_60hz[i] + check_sum_60hz; + } + j++; + } + } + while ((check_sum_60hz != (gamma_para_60hz[450] << 8) + gamma_para_60hz[451]) && (j < 10)); + + if (check_sum_60hz == (gamma_para_60hz[450] << 8) + gamma_para_60hz[451]) { + pr_err("Read 60hz gamma done\n"); + } + else { + pr_err("Failed to read 60hz gamma, use default 60hz gamma.\n"); + memcpy(gamma_para[0], gamma_para_backup, 413); + gamma_read_flag = GAMMA_READ_ERROR; + } + +/* Read 90hz gamma para */ + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_LEVEL2_KEY_ENABLE); + if (rc) { + pr_err("Failed to send DSI_CMD_SET_LEVEL2_KEY_ENABLE command\n"); + goto error; + } + + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_GAMMA_OTP_READ_C8_SMRPS); + if (rc) { + pr_err("Failed to send DSI_CMD_SET_GAMMA_OTP_READ_C8_SMRPS command\n"); + goto error; + } + + flags = 0; + cmds = mode->priv_info->cmd_sets[DSI_CMD_SET_GAMMA_OTP_READ_C8].cmds; + if (cmds->last_command) { + cmds->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + cmds->msg.rx_buf = c8_temp; + cmds->msg.rx_len = 135; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds->msg, flags); + if (rc <= 0) { + pr_err("Failed to read DSI_CMD_SET_GAMMA_OTP_READ_C8\n"); + goto error; + } + memcpy(&gamma_para[1][18], cmds->msg.rx_buf, 135); + + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_GAMMA_OTP_READ_C9_SMRPS); + if (rc) { + pr_err("Failed to send DSI_CMD_SET_GAMMA_OTP_READ_C9_SMRPS command\n"); + goto error; + } + + flags = 0; + cmds = mode->priv_info->cmd_sets[DSI_CMD_SET_GAMMA_OTP_READ_C9].cmds; + if (cmds->last_command) { + cmds->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + cmds->msg.rx_buf = c9_temp; + cmds->msg.rx_len = 180; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds->msg, flags); + if (rc <= 0) { + pr_err("Failed to read DSI_CMD_SET_GAMMA_OTP_READ_C9\n"); + goto error; + } + memcpy(&gamma_para[1][161], cmds->msg.rx_buf, 180); + + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_GAMMA_OTP_READ_B3_SMRPS); + if (rc) { + pr_err("Failed to send DSI_CMD_SET_GAMMA_OTP_READ_C9_SMRPS command\n"); + goto error; + } + + flags = 0; + cmds = mode->priv_info->cmd_sets[DSI_CMD_SET_GAMMA_OTP_READ_B3].cmds; + if (cmds->last_command) { + cmds->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + cmds->msg.rx_buf = b3_temp; + cmds->msg.rx_len = 47; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds->msg, flags); + if (rc <= 0) { + pr_err("Failed to read DSI_CMD_SET_GAMMA_OTP_READ_B3\n"); + goto error; + } + memcpy(b3, cmds->msg.rx_buf, 47); + memcpy(&gamma_para[1][358], &b3[2], 45); + + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_LEVEL2_KEY_DISABLE); + if (rc) { + pr_err("Failed to send DSI_CMD_SET_GAMMA_OTP_READ_C9_SMRPS command\n"); + goto error; + } + pr_err("Read 90hz gamma done\n"); + +error: + dsi_panel_release_panel_lock(panel); + dsi_display_cmd_engine_disable(dsi_display); + pr_err("%s end\n", __func__); + return rc; +} + +int dsi_display_gamma_read(struct dsi_display *dsi_display) { int rc = 0; + struct dsi_panel *panel = NULL; - if (!display) { - pr_err("Invalid params\n"); + pr_err("%s start\n", __func__); + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) return -EINVAL; + + panel = dsi_display->panel; + mutex_lock(&dsi_display->display_lock); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, DSI_ALL_CLKS, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI clocks, rc=%d\n", dsi_display->name, rc); + goto error; } - SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY); - mutex_lock(&display->display_lock); + dsi_display_get_gamma_para(dsi_display, panel); - rc = dsi_display_wake_up(display); - if (rc) - pr_err("[%s] display wake up failed, rc=%d\n", - display->name, rc); + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, DSI_ALL_CLKS, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI clocks, rc=%d\n", dsi_display->name, rc); + goto error; + } - rc = dsi_panel_unprepare(display->panel); - if (rc) - pr_err("[%s] panel unprepare failed, rc=%d\n", - display->name, rc); +error: + mutex_unlock(&dsi_display->display_lock); + pr_err("%s end\n", __func__); + return rc; +} - rc = dsi_display_ctrl_host_disable(display); - if (rc) - pr_err("[%s] failed to disable DSI host, rc=%d\n", - display->name, rc); +void dsi_display_gamma_read_work(struct work_struct *work) +{ + struct dsi_display *dsi_display; - rc = dsi_display_clk_ctrl(display->dsi_clk_handle, - DSI_LINK_CLK, DSI_CLK_OFF); - if (rc) - pr_err("[%s] failed to disable Link clocks, rc=%d\n", - display->name, rc); + dsi_display = get_main_display(); - rc = dsi_display_ctrl_deinit(display); - if (rc) - pr_err("[%s] failed to deinit controller, rc=%d\n", - display->name, rc); + if (((dsi_display->panel->panel_production_info & 0x0F) == 0x0C) + || ((dsi_display->panel->panel_production_info & 0x0F) == 0x0E) + || ((dsi_display->panel->panel_production_info & 0x0F) == 0x0D)) + dsi_display_gamma_read(dsi_display); - if (!display->panel->ulps_suspend_enabled) { - rc = dsi_display_phy_disable(display); - if (rc) - pr_err("[%s] failed to disable DSI PHY, rc=%d\n", - display->name, rc); + dsi_panel_parse_gamma_cmd_sets(); +} + +int dsi_display_read_serial_number(struct dsi_display *dsi_display, + struct dsi_panel *panel, char *buf, int len) +{ + int rc = 0; + int flags = 0; + int code_info = 0; + int stage_info = 0; + int prodution_info = 0; + struct dsi_cmd_desc *cmds; + struct dsi_display_mode *mode; + struct dsi_display_ctrl *m_ctrl; + + pr_err("%s start\n", __func__); + + m_ctrl = &dsi_display->ctrl[dsi_display->cmd_master_idx]; + + if (!panel || !m_ctrl) + return -EINVAL; + + rc = dsi_display_cmd_engine_enable(dsi_display); + if (rc) { + pr_err("cmd engine enable failed\n"); + return -EINVAL; } - rc = dsi_display_clk_ctrl(display->dsi_clk_handle, - DSI_CORE_CLK, DSI_CLK_OFF); - if (rc) - pr_err("[%s] failed to disable DSI clocks, rc=%d\n", - display->name, rc); + dsi_panel_acquire_panel_lock(panel); + mode = panel->cur_mode; - /* destrory dsi isr set up */ - dsi_display_ctrl_isr_configure(display, false); + if ((strcmp(dsi_display->panel->name, "samsung dsc cmd mode oneplus dsi panel") == 0) || + (strcmp(dsi_display->panel->name, "samsung sofef03f_m fhd cmd mode dsc dsi panel") == 0)) { + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_LCDINFO_PRE); + if (rc) { + pr_err("Failed to send DSI_CMD_SET_LCDINFO_PRE commands\n"); + goto error; + } + } - rc = dsi_panel_post_unprepare(display->panel); - if (rc) - pr_err("[%s] panel post-unprepare failed, rc=%d\n", - display->name, rc); + cmds = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_SERIAL_NUMBER].cmds; + if (cmds->last_command) { + cmds->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + if (!m_ctrl->ctrl->vaddr) + goto error; + cmds->msg.rx_buf = buf; + cmds->msg.rx_len = len; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds->msg, flags); + if (rc <= 0) + pr_err("Failed to get panel serial number, rc=%d\n", rc); - mutex_unlock(&display->display_lock); + if ((strcmp(dsi_display->panel->name, "samsung dsc cmd mode oneplus dsi panel") == 0) || + (strcmp(dsi_display->panel->name, "samsung sofef03f_m fhd cmd mode dsc dsi panel") == 0)) { - /* Free up DSI ERROR event callback */ - dsi_display_unregister_error_handler(display); + flags = 0; + cmds = mode->priv_info->cmd_sets[DSI_CMD_SET_CODE_INFO].cmds; + if (cmds->last_command) { + cmds->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + if (!m_ctrl->ctrl->vaddr) + goto error; + cmds->msg.rx_buf = &code_info; + cmds->msg.rx_len = 1; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds->msg, flags); + if (rc <= 0) + pr_err("Failed to get code info, rc=%d\n", rc); + + panel->panel_code_info = code_info & 0xff; + pr_err("Code info is 0x%X\n", panel->panel_code_info); + + flags = 0; + cmds = mode->priv_info->cmd_sets[DSI_CMD_SET_STAGE_INFO].cmds; + if (cmds->last_command) { + cmds->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + if (!m_ctrl->ctrl->vaddr) + goto error; + cmds->msg.rx_buf = &stage_info; + cmds->msg.rx_len = 1; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds->msg, flags); + if (rc <= 0) + pr_err("Failed to get stage info, rc=%d\n", rc); + + panel->panel_stage_info = stage_info & 0xff; + pr_err("Stage info is 0x%X\n", panel->panel_stage_info); + + flags = 0; + cmds = mode->priv_info->cmd_sets[DSI_CMD_SET_PRODUCTION_INFO].cmds; + if (cmds->last_command) { + cmds->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + if (!m_ctrl->ctrl->vaddr) + goto error; + cmds->msg.rx_buf = &prodution_info; + cmds->msg.rx_len = 1; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds->msg, flags); + if (rc <= 0) + pr_err("Failed to get production info, rc=%d\n", rc); + + panel->panel_production_info = prodution_info & 0xff; + pr_err("Production info is 0x%X\n", panel->panel_production_info); + + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_LCDINFO_POST); + if (rc) { + pr_err("Failed to send DSI_CMD_SET_LCDINFO_POST commands\n"); + goto error; + } + } + + error: + dsi_panel_release_panel_lock(panel); + dsi_display_cmd_engine_disable(dsi_display); + pr_err("%s end\n", __func__); - SDE_EVT32(SDE_EVTLOG_FUNC_EXIT); return rc; } +int dsi_display_get_serial_number(struct drm_connector *connector) +{ + struct dsi_display_mode *mode; + struct dsi_panel *panel = NULL; + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + char buf[32]; + int panel_year = 0; + int panel_mon = 0; + int panel_day = 0; + int panel_hour = 0; + int panel_min = 0; + int panel_sec = 0; + int len = 0; + int count; + int rc = 0; + + pr_err("%s start\n", __func__); + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + mutex_lock(&dsi_display->display_lock); + + if (!dsi_panel_initialized(panel) || !panel->cur_mode) + goto error; + + mode = panel->cur_mode; + count = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_SERIAL_NUMBER].count; + if (count) { + len = panel->panel_min_index; + if (len > sizeof(buf)) { + pr_err("len is large than buf size!!!\n"); + goto error; + } + + if ((panel->panel_year_index > len) || (panel->panel_mon_index > len) + || (panel->panel_day_index > len) || (panel->panel_hour_index > len) + || (panel->panel_min_index > len)) { + pr_err("Panel serial number index not corrected.\n"); + goto error; + } + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_ALL_CLKS, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + memset(buf, 0, sizeof(buf)); + dsi_display_read_serial_number(dsi_display, panel, buf, len); + memcpy(panel->buf_id, buf, 32); + panel_year = 2011 + ((buf[panel->panel_year_index - 1] >> 4) & 0x0f); + if (panel_year == 2011) + panel_year = 0; + panel_mon = buf[panel->panel_mon_index - 1] & 0x0f; + if ((panel_mon > 12) || (panel_mon < 1)) { + pr_err("Panel Mon not corrected.\n"); + panel_mon = 0; + } + panel_day = buf[panel->panel_day_index - 1] & 0x3f; + if ((panel_day > 31) || (panel_day < 1)) { + pr_err("Panel Day not corrected.\n"); + panel_day = 0; + } + panel_hour = buf[panel->panel_hour_index - 1] & 0x3f; + if ((panel_hour > 23) || (panel_hour < 0)) { + pr_err("Panel Hour not corrected.\n"); + panel_hour = 0; + } + panel_min = buf[panel->panel_min_index - 1] & 0x3f; + if ((panel_min > 59) || (panel_min < 0)) { + pr_err("Panel Min not corrected.\n"); + panel_min = 0; + } + panel_sec = buf[panel->panel_sec_index - 1] & 0x3f; + if ((panel_sec > 59) || (panel_sec < 0)) { + pr_err("Panel sec not corrected.\n"); + panel_sec = 0; + } + panel->panel_year = panel_year; + panel->panel_mon = panel_mon; + panel->panel_day = panel_day; + panel->panel_hour = panel_hour; + panel->panel_min = panel_min; + panel->panel_sec = panel_sec; + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_ALL_CLKS, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to enable DSI clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + } else { + pr_err("This panel not support serial number.\n"); + } + +error: + mutex_unlock(&dsi_display->display_lock); + pr_err("%s end\n", __func__); + return 0; +} + +int dsi_display_get_serial_number_year(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + pr_err("%s start\n", __func__); + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + pr_err("%s end\n", __func__); + + return dsi_display->panel->panel_year; +} + +int dsi_display_get_serial_number_mon(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + pr_err("%s start\n", __func__); + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + pr_err("%s end\n", __func__); + + return dsi_display->panel->panel_mon; +} + +int dsi_display_get_serial_number_day(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + pr_err("%s start\n", __func__); + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + pr_err("%s end\n", __func__); + + return dsi_display->panel->panel_day; +} + +int dsi_display_get_serial_number_hour(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + pr_err("%s start\n", __func__); + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + pr_err("%s end\n", __func__); + + return dsi_display->panel->panel_hour; +} + +int dsi_display_get_serial_number_min(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + pr_err("%s start\n", __func__); + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + pr_err("%s end\n", __func__); + + return dsi_display->panel->panel_min; +} + +int dsi_display_get_serial_number_sec(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + pr_err("%s start\n", __func__); + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + pr_err("%s end\n", __func__); + + return dsi_display->panel->panel_sec; +} + +int dsi_display_get_code_info(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + pr_err("%s start\n", __func__); + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + pr_err("%s end\n", __func__); + + return dsi_display->panel->panel_code_info; +} + +int dsi_display_get_stage_info(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + pr_err("%s start\n", __func__); + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + pr_err("%s end\n", __func__); + + return dsi_display->panel->panel_stage_info; +} + +int dsi_display_get_production_info(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + pr_err("%s start\n", __func__); + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + pr_err("%s end\n", __func__); + + return dsi_display->panel->panel_production_info; +} + +int dsi_display_get_serial_number_AT(struct drm_connector *connector) +{ + struct dsi_display_mode *mode; + struct dsi_panel *panel = NULL; + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + char buf[32]; + int panel_year = 0; + int panel_mon = 0; + int panel_day = 0; + int panel_hour = 0; + int panel_min = 0; + int panel_sec = 0; + int len = 0; + u32 count; + int rc = 0; + uint64_t serial_number; + pr_err("%s start\n", __func__); + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + mutex_lock(&dsi_display->display_lock); + + if (!dsi_panel_initialized(panel) || !panel->cur_mode) { + goto error; + } + mode = panel->cur_mode; + count = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_SERIAL_NUMBER].count; + + if (count) { + + len = panel->panel_min_index; + if (len > sizeof(buf)) { + pr_err("len is large than buf size!!!\n" ); + goto error; + } + + if ((panel->panel_year_index > len) || (panel->panel_mon_index > len) + || (panel->panel_day_index > len) || (panel->panel_hour_index > len) + || (panel->panel_min_index > len)) { + pr_err("Panel serial number index not corrected.\n"); + goto error; + } + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_ALL_CLKS, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + memset(buf, 0, sizeof(buf)); + dsi_display_read_serial_number(dsi_display, panel, buf, len); + memcpy(panel->buf_id, buf, 32); + + panel_year = 2011 + ((buf[panel->panel_year_index-1] >> 4) & 0x0f); + if (panel_year == 2011){ + panel_year = 0; + } + panel_mon = buf[panel->panel_mon_index-1] & 0x0f; + if ((panel_mon > 12) || (panel_mon < 1)){ + pr_err("Panel Mon not corrected.\n"); + panel_mon = 0; + } + panel_day = buf[panel->panel_day_index-1] & 0x3f; + if ((panel_day > 31) || (panel_day < 1)){ + pr_err("Panel Day not corrected.\n"); + panel_day = 0; + } + panel_hour = buf[panel->panel_hour_index-1] & 0x3f; + if ((panel_hour > 23) || (panel_hour < 0)){ + pr_err("Panel Hour not corrected.\n"); + panel_hour = 0; + } + panel_min = buf[panel->panel_min_index-1] & 0x3f; + if ((panel_min > 59) || (panel_min < 0)){ + pr_err("Panel Min not corrected.\n"); + panel_min = 0; + } + panel_sec = buf[panel->panel_sec_index-1] & 0x3f; + if ((panel_sec > 59) || (panel_sec < 0)){ + pr_err("Panel sec not corrected.\n"); + panel_sec = 0; + } +/* + serial_number = ((uint64_t)panel_year << 56) + + ((uint64_t)panel_mon << 48) + + ((uint64_t)panel_day << 40) + + ((uint64_t)panel_hour << 32) + + ((uint64_t)panel_min << 24) + + ((uint64_t)panel_sec << 16) + + ((uint64_t)0 << 8) + + ((uint64_t)0); +*/ + serial_number = (uint64_t)panel_year * 10000000000 + (uint64_t)panel_mon * 100000000 + (uint64_t)panel_day * 1000000 + + (uint64_t)panel_hour * 10000 + (uint64_t)panel_min * 100 + (uint64_t)panel_sec; + + dsi_display_get_serial_number_id(serial_number); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_ALL_CLKS, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to enable DSI clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + } else{ + pr_err("This panel not support serial number.\n"); + } +error: + mutex_unlock(&dsi_display->display_lock); + pr_err("%s END\n", __func__); + return 0; +} + +uint64_t dsi_display_get_serial_number_id(uint64_t serial_number) +{ + + static uint64_t serial_number_at; + + pr_err("%s start\n",__func__); + if(0 == SERIAL_NUMBER_flag) + { + serial_number_at = serial_number; + if(0 == serial_number_at) + SERIAL_NUMBER_flag = 0; + else + SERIAL_NUMBER_flag = 1; + } + + return serial_number_at; +} + + +int dsi_display_set_hbm_mode(struct drm_connector *connector, int level) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + + mutex_lock(&dsi_display->display_lock); + + panel->hbm_mode = level; + if (!dsi_panel_initialized(panel)) { + goto error; + } + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + rc = dsi_panel_set_hbm_mode(panel, level); + if (rc) + pr_err("unable to set hbm mode\n"); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } +error: + mutex_unlock(&dsi_display->display_lock); + return rc; +} + +int dsi_display_get_hbm_mode(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->hbm_mode; +} + +int dsi_display_set_hbm_brightness(struct drm_connector *connector, int level) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return -EINVAL; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + + if ((strcmp(dsi_display->panel->name, "samsung dsc cmd mode oneplus dsi panel") != 0) && (strcmp(dsi_display->panel->name, "samsung s6e3fc2x01 cmd mode dsi panel") != 0) + && (strcmp(dsi_display->panel->name, "samsung sofef03f_m fhd cmd mode dsc dsi panel") != 0)) { + dsi_display->panel->hbm_brightness = 0; + return 0; + } + + mutex_lock(&dsi_display->display_lock); + + panel->hbm_brightness = level; + + if (!dsi_panel_initialized(panel)) + goto error; + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + rc = dsi_panel_set_hbm_brightness(panel, level); + if (rc) + pr_err("Failed to set hbm brightness mode\n"); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + +error: + mutex_unlock(&dsi_display->display_lock); + return rc; +} + +int dsi_display_get_hbm_brightness(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->hbm_brightness; +} + +extern int oneplus_force_screenfp; + +int dsi_display_set_fp_hbm_mode(struct drm_connector *connector, int level) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + + mutex_lock(&dsi_display->display_lock); + + panel->op_force_screenfp = level; + oneplus_force_screenfp=panel->op_force_screenfp; + if (!dsi_panel_initialized(panel)) { + goto error; + } + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + rc = dsi_panel_op_set_hbm_mode(panel, level); + if (rc) + pr_err("unable to set hbm mode\n"); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } +error: + mutex_unlock(&dsi_display->display_lock); + return rc; +} + + +int dsi_display_get_fp_hbm_mode(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->op_force_screenfp; +} + +int dsi_display_set_dci_p3_mode(struct drm_connector *connector, int level) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + + mutex_lock(&dsi_display->display_lock); + + panel->dci_p3_mode = level; + if (!dsi_panel_initialized(panel)) { + goto error; + } + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + rc = dsi_panel_set_dci_p3_mode(panel, level); + if (rc) + pr_err("unable to set dci_p3 mode\n"); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } +error: + mutex_unlock(&dsi_display->display_lock); + return rc; +} + +int dsi_display_get_dci_p3_mode(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->dci_p3_mode; +} + +int dsi_display_set_night_mode(struct drm_connector *connector, int level) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + + mutex_lock(&dsi_display->display_lock); + + panel->night_mode = level; + if (!dsi_panel_initialized(panel)) { + goto error; + } + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + rc = dsi_panel_set_night_mode(panel, level); + if (rc) + pr_err("unable to set night mode\n"); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } +error: + mutex_unlock(&dsi_display->display_lock); + return rc; +} + +int dsi_display_get_night_mode(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->night_mode; +} +int dsi_display_set_native_display_p3_mode(struct drm_connector *connector, int level) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + + mutex_lock(&dsi_display->display_lock); + + panel->naive_display_p3_mode = level; + if (!dsi_panel_initialized(panel)) { + goto error; + } + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + rc = dsi_panel_set_native_display_p3_mode(panel, level); + if (rc) + pr_err("unable to set native display p3 mode\n"); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } +error: + mutex_unlock(&dsi_display->display_lock); + return rc; +} + +int dsi_display_get_native_display_p3_mode(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->naive_display_p3_mode; +} + +int dsi_display_set_native_display_wide_color_mode(struct drm_connector *connector, int level) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + + mutex_lock(&dsi_display->display_lock); + + panel->naive_display_wide_color_mode = level; + if (!dsi_panel_initialized(panel)) { + goto error; + } + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + rc = dsi_panel_set_native_display_wide_color_mode(panel, level); + if (rc) + pr_err("unable to set native display p3 mode\n"); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } +error: + mutex_unlock(&dsi_display->display_lock); + return rc; +} + +int dsi_display_set_native_loading_effect_mode(struct drm_connector *connector, int level) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + + mutex_lock(&dsi_display->display_lock); + + panel->naive_display_loading_effect_mode = level; + if (!dsi_panel_initialized(panel)) { + goto error; + } + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + rc = dsi_panel_set_native_loading_effect_mode(panel, level); + if (rc) + pr_err("unable to set loading effect mode\n"); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } +error: + mutex_unlock(&dsi_display->display_lock); + return rc; +} + +int dsi_display_set_customer_srgb_mode(struct drm_connector *connector, int level) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + + mutex_lock(&dsi_display->display_lock); + + panel->naive_display_customer_srgb_mode = level; + if (!dsi_panel_initialized(panel)) { + goto error; + } + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + rc = dsi_panel_set_customer_srgb_mode(panel, level); + if (rc) + pr_err("unable to set customer srgb mode\n"); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } +error: + mutex_unlock(&dsi_display->display_lock); + return rc; +} + +int dsi_display_set_customer_p3_mode(struct drm_connector *connector, int level) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + + mutex_lock(&dsi_display->display_lock); + + panel->naive_display_customer_p3_mode = level; + if (!dsi_panel_initialized(panel)) { + goto error; + } + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + rc = dsi_panel_set_customer_p3_mode(panel, level); + if (rc) + pr_err("unable to set customer srgb mode\n"); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } +error: + mutex_unlock(&dsi_display->display_lock); + return rc; +} +int dsi_display_set_native_display_srgb_color_mode(struct drm_connector *connector, int level) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + + mutex_lock(&dsi_display->display_lock); + + panel->naive_display_srgb_color_mode = level; + if (!dsi_panel_initialized(panel)) { + goto error; + } + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + rc = dsi_panel_set_native_display_srgb_color_mode(panel, level); + if (rc) + pr_err("unable to set native display p3 mode\n"); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } +error: + mutex_unlock(&dsi_display->display_lock); + return rc; +} + +int dsi_display_get_native_display_srgb_color_mode(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->naive_display_srgb_color_mode; +} + +int dsi_display_get_native_display_wide_color_mode(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->naive_display_wide_color_mode; +} + +int dsi_display_get_native_display_loading_effect_mode(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->naive_display_loading_effect_mode; +} +int dsi_display_get_customer_srgb_mode(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->naive_display_customer_srgb_mode; +} +int dsi_display_get_customer_p3_mode(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->naive_display_customer_p3_mode; +} + +int dsi_display_set_aod_mode(struct drm_connector *connector, int level) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + panel->aod_mode = level; + if (strcmp(dsi_display->panel->name, "samsung s6e3fc2x01 cmd mode dsi panel") == 0){ + printk(KERN_ERR"dsi_display_set_aod_mode\n"); + }else if(strcmp(dsi_display->panel->name, "samsung dsc cmd mode oneplus dsi panel") == 0){ + printk(KERN_ERR"oneplus SDC 2K OLED dsi_display_set_aod_mode\n"); + }else if(strcmp(dsi_display->panel->name, "samsung sofef03f_m fhd cmd mode dsc dsi panel") == 0) { + printk(KERN_ERR"samsung sofef03f_m fhd cmd mode dsc dsi panel\n"); + }else{ + dsi_display->panel->aod_mode=0; + return 0; + } + mutex_lock(&dsi_display->display_lock); + if (!dsi_panel_initialized(panel)) { + goto error; + } + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + rc = dsi_panel_set_aod_mode(panel, level); + if (rc) + pr_err("unable to set aod mode\n"); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } +error: + mutex_unlock(&dsi_display->display_lock); + + return rc; +} + +int dsi_display_get_aod_mode(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->aod_mode; +} + +int dsi_display_set_aod_disable(struct drm_connector *connector, int disable) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + mutex_lock(&dsi_display->display_lock); + panel->aod_disable = disable; + mutex_unlock(&dsi_display->display_lock); + + return rc; +} + +int dsi_display_get_aod_disable(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->aod_disable; +} +int dsi_display_read_panel_id(struct dsi_display *dsi_display, + struct dsi_panel *panel, char* buf, int len) +{ + int rc = 0; + u32 flags = 0; + struct dsi_cmd_desc *cmds; + struct dsi_display_mode *mode; + struct dsi_display_ctrl *m_ctrl; + int retry_times; + + m_ctrl = &dsi_display->ctrl[dsi_display->cmd_master_idx]; + + if (!panel || !m_ctrl) + return -EINVAL; + + rc = dsi_display_cmd_engine_enable(dsi_display); + if (rc) { + pr_err("cmd engine enable failed\n"); + return -EINVAL; + } + + dsi_panel_acquire_panel_lock(panel); + + mode = panel->cur_mode; + cmds = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_ID].cmds;; + if (cmds->last_command) { + cmds->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + if (!m_ctrl->ctrl->vaddr) + goto error; + + cmds->msg.rx_buf = buf; + cmds->msg.rx_len = len; + retry_times = 0; + do { + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds->msg, flags); + retry_times++; + } while ((rc <= 0) && (retry_times < 3)); + + if (rc <= 0) + pr_err("rx cmd transfer failed rc=%d\n", rc); + + error: + dsi_panel_release_panel_lock(panel); + + dsi_display_cmd_engine_disable(dsi_display); + + return rc; +} + +char dsi_display_ascii_to_int(char ascii, int *ascii_err) +{ + char int_value; + + if ((ascii >= 48) && (ascii <= 57)){ + int_value = ascii - 48; + } + else if ((ascii >= 65) && (ascii <= 70)) { + int_value = ascii - 65 + 10; + } + else if ((ascii >= 97) && (ascii <= 102)) { + int_value = ascii - 97 + 10; + } + else { + int_value = 0; + *ascii_err = 1; + pr_err("Bad para: %d , please enter the right value!", ascii); + } + + return int_value; +} + +int dsi_display_update_dsi_on_command(struct drm_connector *connector, const char *buf, size_t count) +{ + int i = 0; + int j = 0; + int ascii_err = 0; + unsigned int length; + char *data; + struct dsi_panel_cmd_set *set; + + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return -EINVAL; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + + mutex_lock(&dsi_display->display_lock); + + length = count / 3; + data = kzalloc(length + 1, GFP_KERNEL); + + for (i = 0; (buf[i+2] != 10) && (j < length); i = i+3) { + data[j] = dsi_display_ascii_to_int(buf[i], &ascii_err) << 4; + data[j] += dsi_display_ascii_to_int(buf[i+1], &ascii_err); + j++; + } + data[j] = dsi_display_ascii_to_int(buf[i], &ascii_err) << 4; + data[j] += dsi_display_ascii_to_int(buf[i+1], &ascii_err); + if (ascii_err == 1) { + pr_err("Bad Para, ignore this command\n"); + goto error; + } + + set = &panel->cur_mode->priv_info->cmd_sets[DSI_CMD_SET_ON]; + + rc = dsi_panel_update_cmd_sets_sub(set, DSI_CMD_SET_ON, data, length); + if (rc) + pr_err("Failed to update_cmd_sets_sub, rc=%d\n", rc); + +error: + kfree(data); + mutex_unlock(&dsi_display->display_lock); + return rc; +} + +static int dsi_display_get_mipi_dsi_msg(const struct mipi_dsi_msg *msg, char* buf) +{ + int len = 0; + size_t i; + char *tx_buf = (char*)msg->tx_buf; + /* Packet Info */ + len += snprintf(buf + len, PAGE_SIZE - len, "%02X ", msg->type); + /* Last bit */ + len += snprintf(buf + len, PAGE_SIZE - len, "%02X ", (msg->flags & MIPI_DSI_MSG_LASTCOMMAND) ? 1 : 0); + len += snprintf(buf + len, PAGE_SIZE - len, "%02X ", msg->channel); + len += snprintf(buf + len, PAGE_SIZE - len, "%02X ", (unsigned int)msg->flags); + /* Delay */ + len += snprintf(buf + len, PAGE_SIZE - len, "%02X ", msg->wait_ms); + len += snprintf(buf + len, PAGE_SIZE - len, "%02X %02X ", msg->tx_len >> 8, msg->tx_len & 0x00FF); + + /* Packet Payload */ + for (i = 0 ; i < msg->tx_len ; i++) { + len += snprintf(buf + len, PAGE_SIZE - len, "%02X ", tx_buf[i]); + } + len += snprintf(buf + len, PAGE_SIZE - len, "\n"); + + return len; +} + +int dsi_display_get_dsi_on_command(struct drm_connector *connector, char *buf) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + struct dsi_panel_cmd_set *cmd; + int i = 0; + int count = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + cmd = &dsi_display->panel->cur_mode->priv_info->cmd_sets[DSI_CMD_SET_ON]; + + for (i = 0; i < cmd->count; i++) { + count += dsi_display_get_mipi_dsi_msg(&cmd->cmds[i].msg, &buf[count]); + } + + return count; +} + +int dsi_display_update_dsi_panel_command(struct drm_connector *connector, const char *buf, size_t count) +{ + int i = 0; + int j = 0; + int ascii_err = 0; + unsigned int length; + char *data; + struct dsi_panel_cmd_set *set; + + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return -EINVAL; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + + if ((strcmp(panel->name, "samsung dsc cmd mode oneplus dsi panel") != 0) && + (strcmp(panel->name, "samsung sofef03f_m fhd cmd mode dsc dsi panel") != 0)) { + return 0; + } + + mutex_lock(&dsi_display->display_lock); + + if (!dsi_panel_initialized(panel)) + goto error; + + length = count / 3; + data = kzalloc(length + 1, GFP_KERNEL); + + for (i = 0; (buf[i+2] != 10) && (j < length); i = i+3) { + data[j] = dsi_display_ascii_to_int(buf[i], &ascii_err) << 4; + data[j] += dsi_display_ascii_to_int(buf[i+1], &ascii_err); + j++; + } + data[j] = dsi_display_ascii_to_int(buf[i], &ascii_err) << 4; + data[j] += dsi_display_ascii_to_int(buf[i+1], &ascii_err); + if (ascii_err == 1) { + pr_err("Bad Para, ignore this command\n"); + kfree(data); + goto error; + } + + set = &panel->cur_mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_COMMAND]; + + rc = dsi_panel_update_cmd_sets_sub(set, DSI_CMD_SET_PANEL_COMMAND, data, length); + if (rc) + pr_err("Failed to update_cmd_sets_sub, rc=%d\n", rc); + kfree(data); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + rc = dsi_panel_send_dsi_panel_command(panel); + if (rc) + pr_err("Failed to send dsi panel command\n"); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + +error: + mutex_unlock(&dsi_display->display_lock); + return rc; +} + +int dsi_display_get_dsi_panel_command(struct drm_connector *connector, char *buf) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + struct dsi_panel_cmd_set *cmd; + int i = 0; + int count = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + cmd = &dsi_display->panel->cur_mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_COMMAND]; + + for (i = 0; i < cmd->count; i++) + count += dsi_display_get_mipi_dsi_msg(&cmd->cmds[i].msg, &buf[count]); + + return count; +} + +int dsi_display_update_dsi_seed_command(struct drm_connector *connector, const char *buf, size_t count) +{ + int i = 0; + int j = 0; + int ascii_err = 0; + unsigned int length; + char *data; + struct dsi_panel_cmd_set *set; + + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return -EINVAL; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + + if ((strcmp(panel->name, "samsung dsc cmd mode oneplus dsi panel") != 0) && + (strcmp(panel->name, "samsung sofef03f_m fhd cmd mode dsc dsi panel") != 0)) { + return 0; + } + + mutex_lock(&panel->panel_lock); + + if (!dsi_panel_initialized(panel)) + goto error; + + length = count / 3; + if (length != 0x16) { + pr_err("Insufficient parameters!\n"); + goto error; + } + data = kzalloc(length + 1, GFP_KERNEL); + + for (i = 0; (buf[i+2] != 10) && (j < length); i = i+3) { + data[j] = dsi_display_ascii_to_int(buf[i], &ascii_err) << 4; + data[j] += dsi_display_ascii_to_int(buf[i+1], &ascii_err); + j++; + } + data[j] = dsi_display_ascii_to_int(buf[i], &ascii_err) << 4; + data[j] += dsi_display_ascii_to_int(buf[i+1], &ascii_err); + if (ascii_err == 1) { + pr_err("Bad Para, ignore this command\n"); + kfree(data); + goto error; + } + + set = &panel->cur_mode->priv_info->cmd_sets[DSI_CMD_SET_SEED_COMMAND]; + + if (strcmp(panel->name, "samsung dsc cmd mode oneplus dsi panel") == 0) + data[0] = WU_SEED_REGISTER; + if (strcmp(panel->name, "samsung sofef03f_m fhd cmd mode dsc dsi panel") == 0) + data[0] = UG_SEED_REGISTER; + + rc = dsi_panel_update_dsi_seed_command(set->cmds, DSI_CMD_SET_SEED_COMMAND, data); + if (rc) + pr_err("Failed to dsi_panel_update_dsi_seed_command, rc=%d\n", rc); + kfree(data); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + rc = dsi_panel_send_dsi_seed_command(panel); + if (rc) + pr_err("Failed to send dsi seed command\n"); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + +error: + mutex_unlock(&panel->panel_lock); + return rc; +} + +int dsi_display_get_dsi_seed_command(struct drm_connector *connector, char *buf) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + struct dsi_panel_cmd_set *cmd; + int i = 0; + int count = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + if ((strcmp(dsi_display->panel->name, "samsung dsc cmd mode oneplus dsi panel") != 0) && + (strcmp(dsi_display->panel->name, "samsung sofef03f_m fhd cmd mode dsc dsi panel") != 0)) { + return 0; + } + + cmd = &dsi_display->panel->cur_mode->priv_info->cmd_sets[DSI_CMD_SET_SEED_COMMAND]; + + for (i = 0; i < cmd->count; i++) { + count += dsi_display_get_mipi_dsi_msg(&cmd->cmds[i].msg, &buf[count]); + } + + return count; +} + +int dsi_display_panel_mismatch_check(struct drm_connector *connector) +{ + struct dsi_display_mode *mode; + struct dsi_panel *panel = NULL; + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + char buf[32]; + int panel_id; + u32 count; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + mutex_lock(&dsi_display->display_lock); + + if (!dsi_panel_initialized(panel) || !panel->cur_mode) { + panel->panel_mismatch = 0; + goto error; + } + + if (!panel->panel_mismatch_check) { + panel->panel_mismatch = 0; + pr_err("This hw not support panel mismatch check(dvt-mp)\n"); + goto error; + } + + mode = panel->cur_mode; + count = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_ID].count; + if (count) { + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_ALL_CLKS, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + memset(buf, 0, sizeof(buf)); + dsi_display_read_panel_id(dsi_display, panel, buf, 1); + + panel_id = buf[0]; + panel->panel_mismatch = (panel_id == 0x03)? 1 : 0; + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_ALL_CLKS, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to enable DSI clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + } else{ + panel->panel_mismatch = 0; + pr_err("This panel not support panel mismatch check.\n"); + } +error: + mutex_unlock(&dsi_display->display_lock); + return 0; +} + +int dsi_display_panel_mismatch(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->panel_mismatch; +} + +int dsi_display_unprepare(struct dsi_display *display) +{ + int rc = 0; + + if (!display) { + pr_err("Invalid params\n"); + return -EINVAL; + } + + SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY); + mutex_lock(&display->display_lock); + + rc = dsi_display_wake_up(display); + if (rc) + pr_err("[%s] display wake up failed, rc=%d\n", + display->name, rc); + + rc = dsi_panel_unprepare(display->panel); + if (rc) + pr_err("[%s] panel unprepare failed, rc=%d\n", + display->name, rc); + + rc = dsi_display_ctrl_host_disable(display); + if (rc) + pr_err("[%s] failed to disable DSI host, rc=%d\n", + display->name, rc); + + rc = dsi_display_clk_ctrl(display->dsi_clk_handle, + DSI_LINK_CLK, DSI_CLK_OFF); + if (rc) + pr_err("[%s] failed to disable Link clocks, rc=%d\n", + display->name, rc); + + rc = dsi_display_ctrl_deinit(display); + if (rc) + pr_err("[%s] failed to deinit controller, rc=%d\n", + display->name, rc); + + if (!display->panel->ulps_suspend_enabled) { + rc = dsi_display_phy_disable(display); + if (rc) + pr_err("[%s] failed to disable DSI PHY, rc=%d\n", + display->name, rc); + } + + rc = dsi_display_clk_ctrl(display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) + pr_err("[%s] failed to disable DSI clocks, rc=%d\n", + display->name, rc); + + /* destrory dsi isr set up */ + dsi_display_ctrl_isr_configure(display, false); + + rc = dsi_panel_post_unprepare(display->panel); + if (rc) + pr_err("[%s] panel post-unprepare failed, rc=%d\n", + display->name, rc); + + mutex_unlock(&display->display_lock); + + /* Free up DSI ERROR event callback */ + dsi_display_unregister_error_handler(display); + + SDE_EVT32(SDE_EVTLOG_FUNC_EXIT); + return rc; +} +//*mark.yao@PSW.MM.Display.LCD.Stability,2018/4/28,add for support aod,hbm,seed*/ +struct dsi_display *get_main_display(void) { + return primary_display; +} +EXPORT_SYMBOL(get_main_display); + static int __init dsi_display_register(void) { dsi_phy_drv_register(); diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display.h b/drivers/gpu/drm/msm/dsi-staging/dsi_display.h index 4cf3cebb7d02e404cd6b8e433b663c1501f93e8c..1d761511d17313e5511dae31c2a654fccad9cf00 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_display.h +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display.h @@ -417,6 +417,7 @@ int dsi_display_validate_mode_change(struct dsi_display *display, struct dsi_display_mode *cur_dsi_mode, struct dsi_display_mode *mode); +extern int msm_drm_notifier_call_chain(unsigned long val, void *v); /** * dsi_display_set_mode() - Set mode on the display. * @display: Handle to display. @@ -580,6 +581,10 @@ int dsi_display_set_tpg_state(struct dsi_display *display, bool enable); int dsi_display_clock_gate(struct dsi_display *display, bool enable); int dsi_dispaly_static_frame(struct dsi_display *display, bool enable); +uint64_t dsi_display_get_serial_number_id(uint64_t serial_number); + +int dsi_display_get_serial_number_AT(struct drm_connector *connector); + /** * dsi_display_enable_event() - enable interrupt based connector event @@ -694,4 +699,12 @@ int dsi_display_cont_splash_config(void *display); int dsi_display_get_panel_vfp(void *display, int h_active, int v_active); +extern int connector_state_crtc_index; +extern int msm_drm_notifier_call_chain(unsigned long val, void *v); + +struct dsi_display *get_main_display(void); +extern char gamma_para[2][413]; +int dsi_display_gamma_read(struct dsi_display *dsi_display); +void dsi_display_gamma_read_work(struct work_struct *work); +extern struct delayed_work *sde_esk_check_delayed_work; #endif /* _DSI_DISPLAY_H_ */ diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c b/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c index 0e58dd8ed4d976350293f27f0c16425af6ba4fb9..4915f68707c669a2233286366da1e300b3272e9d 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c @@ -21,6 +21,8 @@ #include "sde_connector.h" #include "dsi_drm.h" #include "sde_trace.h" +#include "sde_dbg.h" + #define to_dsi_bridge(x) container_of((x), struct dsi_bridge, base) #define to_dsi_state(x) container_of((x), struct dsi_connector_state, base) @@ -186,15 +188,14 @@ static void dsi_bridge_pre_enable(struct drm_bridge *bridge) return; } - SDE_ATRACE_BEGIN("dsi_display_prepare"); + SDE_ATRACE_BEGIN("dsi_bridge_pre_enable"); rc = dsi_display_prepare(c_bridge->display); if (rc) { pr_err("[%d] DSI display prepare failed, rc=%d\n", c_bridge->id, rc); - SDE_ATRACE_END("dsi_display_prepare"); + SDE_ATRACE_END("dsi_bridge_pre_enable"); return; } - SDE_ATRACE_END("dsi_display_prepare"); SDE_ATRACE_BEGIN("dsi_display_enable"); rc = dsi_display_enable(c_bridge->display); @@ -204,6 +205,7 @@ static void dsi_bridge_pre_enable(struct drm_bridge *bridge) (void)dsi_display_unprepare(c_bridge->display); } SDE_ATRACE_END("dsi_display_enable"); + SDE_ATRACE_END("dsi_bridge_pre_enable"); rc = dsi_display_splash_res_cleanup(c_bridge->display); if (rc) @@ -384,7 +386,7 @@ static bool dsi_bridge_mode_fixup(struct drm_bridge *bridge, if (rc) { pr_err("[%s] seamless mode mismatch failure rc=%d\n", c_bridge->display->name, rc); - return false; +// return false; } cur_mode = crtc_state->crtc->mode; @@ -446,7 +448,7 @@ int dsi_conn_get_mode_info(struct drm_connector *connector, if (!dsi_mode.priv_info) return -EINVAL; - + SDE_EVT32(mode_info, ((unsigned long long)mode_info) >> 32, connector, ((unsigned long long)connector) >> 32, 0x9999); memset(mode_info, 0, sizeof(*mode_info)); timing = &dsi_mode.timing; @@ -458,7 +460,6 @@ int dsi_conn_get_mode_info(struct drm_connector *connector, mode_info->clk_rate = dsi_drm_find_bit_clk_rate(display, drm_mode); mode_info->mdp_transfer_time_us = dsi_mode.priv_info->mdp_transfer_time_us; - mode_info->overlap_pixels = dsi_mode.priv_info->overlap_pixels; memcpy(&mode_info->topology, &dsi_mode.priv_info->topology, sizeof(struct msm_display_topology)); @@ -476,7 +477,7 @@ int dsi_conn_get_mode_info(struct drm_connector *connector, memcpy(&mode_info->roi_caps, &dsi_mode.priv_info->roi_caps, sizeof(dsi_mode.priv_info->roi_caps)); } - + SDE_EVT32(dsi_mode.priv_info->dsc_enabled, mode_info->clk_rate, mode_info->frame_rate, 0x9999); return 0; } diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c index de28a2e8964dc1700c987e1e9a14d1d2e23a3970..a39cb90d5cb80e24a9e86bb4fc7582b21a8a6e72 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c @@ -19,11 +19,24 @@ #include #include #include