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Commit 71a4d4f0 authored by Tatenda Chipeperekwa's avatar Tatenda Chipeperekwa
Browse files

drm/msm/dp: update the DP PHY and controller programming for sm8150 



Update the AUX setup sequence for DP PHY on sm8150 in order to
enable AUX transactions once the cable is plugged in. Update the
values for the voltage swing and pre-emphasis levels used when
programming the DP PHY during the link power on sequence.
Furthermore, update the controller programming to ensure all
controller state transitions happens correctly.

Change-Id: I0b16ac79e9679a7aac119548a226531698400935
Signed-off-by: default avatarTatenda Chipeperekwa <tatendac@codeaurora.org>
parent da79c568

drivers/gpu/drm/msm/dp/dp_catalog_v420.c

+8 −8
Original line number Diff line number Diff line
@@ -27,17 +27,17 @@ 
#define MAX_PRE_EMP_LEVELS 4



static u8 const vm_pre_emphasis[MAX_VOLTAGE_LEVELS][MAX_PRE_EMP_LEVELS] = {

	{0x00, 0x0B, 0x12, 0xFF},       /* pe0, 0 db */

	{0x00, 0x0A, 0x12, 0xFF},       /* pe1, 3.5 db */

	{0x00, 0x0C, 0xFF, 0xFF},       /* pe2, 6.0 db */

	{0x00, 0x0B, 0x14, 0xFF},       /* pe0, 0 db */

	{0x00, 0x0B, 0x12, 0xFF},       /* pe1, 3.5 db */

	{0x00, 0x0B, 0xFF, 0xFF},       /* pe2, 6.0 db */

	{0xFF, 0xFF, 0xFF, 0xFF}        /* pe3, 9.5 db */

};



/* voltage swing, 0.2v and 1.0v are not support */

static u8 const vm_voltage_swing[MAX_VOLTAGE_LEVELS][MAX_PRE_EMP_LEVELS] = {

	{0x07, 0x0F, 0x14, 0xFF}, /* sw0, 0.4v  */

	{0x11, 0x1D, 0x1F, 0xFF}, /* sw1, 0.6 v */

	{0x18, 0x1F, 0xFF, 0xFF}, /* sw1, 0.8 v */

	{0x07, 0x0F, 0x16, 0xFF}, /* sw0, 0.4v  */

	{0x11, 0x1E, 0x1F, 0xFF}, /* sw1, 0.6 v */

	{0x19, 0x1F, 0xFF, 0xFF}, /* sw1, 0.8 v */

	{0xFF, 0xFF, 0xFF, 0xFF}  /* sw1, 1.2 v, optional */

};
@@ -108,13 +108,13 @@ static void dp_catalog_aux_setup_v420(struct dp_catalog_aux *aux, 
	catalog = dp_catalog_get_priv_v420(aux);



	io_data = catalog->io->dp_phy;

	dp_write(catalog, io_data, DP_PHY_PD_CTL, 0x65);

	dp_write(catalog, io_data, DP_PHY_PD_CTL, 0x67);

	wmb(); /* make sure PD programming happened */



	/* Turn on BIAS current for PHY/PLL */

	io_data = catalog->io->dp_pll;

	dp_write(catalog, io_data, QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x17);

	wmb(); /* make sure PD programming happened */

	wmb(); /* make sure BIAS programming happened */



	io_data = catalog->io->dp_phy;

	/* DP AUX CFG register programming */

drivers/gpu/drm/msm/dp/dp_ctrl.c

+2 −2
Original line number Diff line number Diff line
@@ -115,7 +115,7 @@ static void dp_ctrl_push_idle(struct dp_ctrl *dp_ctrl, enum dp_stream_id strm) 
{

	int const idle_pattern_completion_timeout_ms = 3 * HZ / 100;

	struct dp_ctrl_private *ctrl;

	u32 state;

	u32 state = 0x0;



	if (!dp_ctrl) {

		pr_err("Invalid input data\n");
@@ -139,7 +139,7 @@ static void dp_ctrl_push_idle(struct dp_ctrl *dp_ctrl, enum dp_stream_id strm) 
		return;

	}



	state = (strm == DP_STREAM_0) ? MST_DP0_PUSH_VCPF : MST_DP1_PUSH_VCPF;

	state |= (strm == DP_STREAM_0) ? MST_DP0_PUSH_VCPF : MST_DP1_PUSH_VCPF;



trigger_idle:

	reinit_completion(&ctrl->idle_comp);