Loading arch/arm64/boot/dts/qcom/sm8150-sde-display.dtsi +1 −1 Original line number Diff line number Diff line Loading @@ -395,7 +395,7 @@ }; &mdss_mdp { connectors = <&sde_rscc &sde_wb &sde_dp &sde_dsi>; connectors = <&sde_wb &sde_dp &sde_dsi>; }; /* PHY TIMINGS REVISION P */ Loading arch/arm64/boot/dts/qcom/sm8150-sde-pll.dtsi +17 −0 Original line number Diff line number Diff line Loading @@ -79,6 +79,8 @@ reg-names = "pll_base", "phy_base", "ln_tx0_base", "ln_tx1_base", "gdsc_base"; gdsc-supply = <&mdss_core_gdsc>; clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, <&clock_rpmh RPMH_CXO_CLK>, <&clock_gcc GCC_DISP_AHB_CLK>, Loading @@ -87,6 +89,21 @@ clock-names = "iface_clk", "ref_clk_src", "gcc_iface", "ref_clk", "pipe_clk"; clock-rate = <0>; qcom,platform-supply-entries { #address-cells = <1>; #size-cells = <0>; qcom,platform-supply-entry@0 { reg = <0>; qcom,supply-name = "gdsc"; qcom,supply-min-voltage = <0>; qcom,supply-max-voltage = <0>; qcom,supply-enable-load = <0>; qcom,supply-disable-load = <0>; }; }; }; }; arch/arm64/boot/dts/qcom/sm8150-sde.dtsi +45 −14 Original line number Diff line number Diff line Loading @@ -24,19 +24,15 @@ clocks = <&clock_gcc GCC_DISP_AHB_CLK>, <&clock_gcc GCC_DISP_HF_AXI_CLK>, <&clock_gcc GCC_DISP_SF_AXI_CLK>, <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, <&clock_dispcc DISP_CC_MDSS_MDP_CLK>, <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>, <&clock_dispcc DISP_CC_MDSS_ROT_CLK>; clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", "iface_clk", "core_clk", "vsync_clk", "rot_clk"; clock-rate = <0 0 0 0 300000000 19200000 0>; clock-max-rate = <0 0 0 0 460000000 19200000 0>; <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>; clock-names = "gcc_iface", "gcc_bus", "iface_clk", "core_clk", "vsync_clk"; clock-rate = <0 0 0 300000000 19200000>; clock-max-rate = <0 0 0 460000000 19200000>; sde-vdd-supply = <&mdss_core_gdsc>; mmcx-supply = <&VDD_MMCX_LEVEL>; /* interrupt config */ interrupts = <0 83 0>; Loading Loading @@ -248,7 +244,7 @@ qcom,platform-supply-entry@0 { reg = <0>; qcom,supply-name = "mmcx"; qcom,supply-name = "sde-vdd"; qcom,supply-min-voltage = <0>; qcom,supply-max-voltage = <0>; qcom,supply-enable-load = <0>; Loading @@ -263,13 +259,33 @@ /* data and reg bus scale settings */ qcom,sde-data-bus { qcom,msm-bus,name = "mdss_sde"; qcom,msm-bus,name = "mdss_sde_mnoc"; qcom,msm-bus,num-cases = <3>; qcom,msm-bus,num-paths = <2>; qcom,msm-bus,vectors-KBps = <22 512 0 0>, <23 512 0 0>, <22 512 0 6400000>, <23 512 0 6400000>, <22 512 0 6400000>, <23 512 0 6400000>; <22 773 0 0>, <23 773 0 0>, <22 773 0 6400000>, <23 773 0 6400000>, <22 773 0 6400000>, <23 773 0 6400000>; }; qcom,sde-llcc-bus { qcom,msm-bus,name = "mdss_sde_llcc"; qcom,msm-bus,num-cases = <3>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <132 770 0 0>, <132 770 0 6400000>, <132 770 0 6400000>; }; qcom,sde-ebi-bus { qcom,msm-bus,name = "mdss_sde_ebi"; qcom,msm-bus,num-cases = <3>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <129 512 0 0>, <129 512 0 6400000>, <129 512 0 6400000>; }; qcom,sde-reg-bus { Loading @@ -291,6 +307,7 @@ <0xaf30000 0x3fd4>; reg-names = "drv", "wrapper"; qcom,sde-rsc-version = <2>; status = "disabled"; vdd-supply = <&mdss_core_gdsc>; clocks = <&clock_dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>, Loading Loading @@ -337,6 +354,20 @@ <20000 20512 0 6400000>, <20000 20512 0 6400000>; }; qcom,platform-supply-entries { #address-cells = <1>; #size-cells = <0>; qcom,platform-supply-entry@0 { reg = <0>; qcom,supply-name = "mmcx"; qcom,supply-min-voltage = <0>; qcom,supply-max-voltage = <0>; qcom,supply-enable-load = <0>; qcom,supply-disable-load = <0>; }; }; }; mdss_rotator: qcom,mdss_rotator@ae00000 { Loading Loading
arch/arm64/boot/dts/qcom/sm8150-sde-display.dtsi +1 −1 Original line number Diff line number Diff line Loading @@ -395,7 +395,7 @@ }; &mdss_mdp { connectors = <&sde_rscc &sde_wb &sde_dp &sde_dsi>; connectors = <&sde_wb &sde_dp &sde_dsi>; }; /* PHY TIMINGS REVISION P */ Loading
arch/arm64/boot/dts/qcom/sm8150-sde-pll.dtsi +17 −0 Original line number Diff line number Diff line Loading @@ -79,6 +79,8 @@ reg-names = "pll_base", "phy_base", "ln_tx0_base", "ln_tx1_base", "gdsc_base"; gdsc-supply = <&mdss_core_gdsc>; clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, <&clock_rpmh RPMH_CXO_CLK>, <&clock_gcc GCC_DISP_AHB_CLK>, Loading @@ -87,6 +89,21 @@ clock-names = "iface_clk", "ref_clk_src", "gcc_iface", "ref_clk", "pipe_clk"; clock-rate = <0>; qcom,platform-supply-entries { #address-cells = <1>; #size-cells = <0>; qcom,platform-supply-entry@0 { reg = <0>; qcom,supply-name = "gdsc"; qcom,supply-min-voltage = <0>; qcom,supply-max-voltage = <0>; qcom,supply-enable-load = <0>; qcom,supply-disable-load = <0>; }; }; }; };
arch/arm64/boot/dts/qcom/sm8150-sde.dtsi +45 −14 Original line number Diff line number Diff line Loading @@ -24,19 +24,15 @@ clocks = <&clock_gcc GCC_DISP_AHB_CLK>, <&clock_gcc GCC_DISP_HF_AXI_CLK>, <&clock_gcc GCC_DISP_SF_AXI_CLK>, <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, <&clock_dispcc DISP_CC_MDSS_MDP_CLK>, <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>, <&clock_dispcc DISP_CC_MDSS_ROT_CLK>; clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", "iface_clk", "core_clk", "vsync_clk", "rot_clk"; clock-rate = <0 0 0 0 300000000 19200000 0>; clock-max-rate = <0 0 0 0 460000000 19200000 0>; <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>; clock-names = "gcc_iface", "gcc_bus", "iface_clk", "core_clk", "vsync_clk"; clock-rate = <0 0 0 300000000 19200000>; clock-max-rate = <0 0 0 460000000 19200000>; sde-vdd-supply = <&mdss_core_gdsc>; mmcx-supply = <&VDD_MMCX_LEVEL>; /* interrupt config */ interrupts = <0 83 0>; Loading Loading @@ -248,7 +244,7 @@ qcom,platform-supply-entry@0 { reg = <0>; qcom,supply-name = "mmcx"; qcom,supply-name = "sde-vdd"; qcom,supply-min-voltage = <0>; qcom,supply-max-voltage = <0>; qcom,supply-enable-load = <0>; Loading @@ -263,13 +259,33 @@ /* data and reg bus scale settings */ qcom,sde-data-bus { qcom,msm-bus,name = "mdss_sde"; qcom,msm-bus,name = "mdss_sde_mnoc"; qcom,msm-bus,num-cases = <3>; qcom,msm-bus,num-paths = <2>; qcom,msm-bus,vectors-KBps = <22 512 0 0>, <23 512 0 0>, <22 512 0 6400000>, <23 512 0 6400000>, <22 512 0 6400000>, <23 512 0 6400000>; <22 773 0 0>, <23 773 0 0>, <22 773 0 6400000>, <23 773 0 6400000>, <22 773 0 6400000>, <23 773 0 6400000>; }; qcom,sde-llcc-bus { qcom,msm-bus,name = "mdss_sde_llcc"; qcom,msm-bus,num-cases = <3>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <132 770 0 0>, <132 770 0 6400000>, <132 770 0 6400000>; }; qcom,sde-ebi-bus { qcom,msm-bus,name = "mdss_sde_ebi"; qcom,msm-bus,num-cases = <3>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <129 512 0 0>, <129 512 0 6400000>, <129 512 0 6400000>; }; qcom,sde-reg-bus { Loading @@ -291,6 +307,7 @@ <0xaf30000 0x3fd4>; reg-names = "drv", "wrapper"; qcom,sde-rsc-version = <2>; status = "disabled"; vdd-supply = <&mdss_core_gdsc>; clocks = <&clock_dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>, Loading Loading @@ -337,6 +354,20 @@ <20000 20512 0 6400000>, <20000 20512 0 6400000>; }; qcom,platform-supply-entries { #address-cells = <1>; #size-cells = <0>; qcom,platform-supply-entry@0 { reg = <0>; qcom,supply-name = "mmcx"; qcom,supply-min-voltage = <0>; qcom,supply-max-voltage = <0>; qcom,supply-enable-load = <0>; qcom,supply-disable-load = <0>; }; }; }; mdss_rotator: qcom,mdss_rotator@ae00000 { Loading