Commit 7149c1be authored Mar 24, 2017 by Chen-Yu Tsai Committed by Maxime Ripard Apr 13, 2017

clk: sunxi-ng: a80: Fix audio PLL comment not matching actual code



We ignore the d1 and d2 dividers in the audio PLL, and force them to
1 (register value 0) at probe time. However the comment preceding the
audio PLL definition says we enforce the default value, which is not
the same.

Fix the preceding comment to match what we do in code.

Fixes: b8eb71dc ("clk: sunxi-ng: Add A80 CCU")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

parent 95ad8ed9

drivers/clk/sunxi-ng/ccu-sun9i-a80.c

+1 −2

Original line number	Diff line number	Diff line
		@@ -70,8 +70,7 @@ static struct ccu_mult pll_c1cpux_clk = {
		/*
		* The Audio PLL has d1, d2 dividers in addition to the usual N, M
		* factors. Since we only need 2 frequencies from this PLL: 22.5792 MHz
		* and 24.576 MHz, ignore them for now. Enforce the default for them,
		* which is d1 = 0, d2 = 1.
		* and 24.576 MHz, ignore them for now. Enforce d1 = 0 and d2 = 0.
		*/
		#define SUN9I_A80_PLL_AUDIO_REG 0x008