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Commit 7140812c authored by Wei WANG's avatar Wei WANG Committed by Samuel Ortiz
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mfd: rtsx: Move some actions from rtsx_pci_init_hw to individual extra_init_hw 



These actions are individual for each reader model, so should be put in
extra_init_hw instead of rtsx_pci_init_hw.

Signed-off-by: default avatarWei WANG <wei_wang@realsil.com.cn>
Signed-off-by: default avatarSamuel Ortiz <sameo@linux.intel.com>
parent 5947c167

drivers/mfd/rts5209.c

+4 −0
Original line number Diff line number Diff line
@@ -70,6 +70,10 @@ static int rts5209_extra_init_hw(struct rtsx_pcr *pcr) 


	/* Turn off LED */

	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_GPIO, 0xFF, 0x03);

	/* Reset ASPM state to default value */

	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);

	/* Force CLKREQ# PIN to drive 0 to request clock */

	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x08, 0x08);

	/* Configure GPIO as output */

	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_GPIO_DIR, 0xFF, 0x03);

	/* Configure driving */

drivers/mfd/rts5227.c

+2 −0
Original line number Diff line number Diff line
@@ -101,6 +101,8 @@ static int rts5227_extra_init_hw(struct rtsx_pcr *pcr) 


	/* Configure GPIO as output */

	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);

	/* Reset ASPM state to default value */

	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);

	/* Switch LDO3318 source from DV33 to card_3v3 */

	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);

	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);

drivers/mfd/rts5229.c

+4 −0
Original line number Diff line number Diff line
@@ -67,6 +67,10 @@ static int rts5229_extra_init_hw(struct rtsx_pcr *pcr) 


	/* Configure GPIO as output */

	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);

	/* Reset ASPM state to default value */

	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);

	/* Force CLKREQ# PIN to drive 0 to request clock */

	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x08, 0x08);

	/* Switch LDO3318 source from DV33 to card_3v3 */

	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);

	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);

drivers/mfd/rts5249.c

+2 −0
Original line number Diff line number Diff line
@@ -104,6 +104,8 @@ static int rts5249_extra_init_hw(struct rtsx_pcr *pcr) 


	/* Configure GPIO as output */

	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);

	/* Reset ASPM state to default value */

	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);

	/* Switch LDO3318 source from DV33 to card_3v3 */

	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);

	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);

drivers/mfd/rtsx_pcr.c

+0 −4
Original line number Diff line number Diff line
@@ -972,8 +972,6 @@ static int rtsx_pci_init_hw(struct rtsx_pcr *pcr) 
	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00);

	/* Disable card clock */

	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0);

	/* Reset ASPM state to default value */

	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);

	/* Reset delink mode */

	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0);

	/* Card driving select */
@@ -1003,8 +1001,6 @@ static int rtsx_pci_init_hw(struct rtsx_pcr *pcr) 
	 *	0: ELBI interrupt flag[31:22] & [7:0] only can be write clear

	 */

	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0);

	/* Force CLKREQ# PIN to drive 0 to request clock */

	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x08, 0x08);



	err = rtsx_pci_send_cmd(pcr, 100);

	if (err < 0)