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Commit 7131b6bb authored by Amit Nischal's avatar Amit Nischal
Browse files

clk: qcom: Clear hardware clock control bit of RCG 



There could be few clock sources with only one scaling frequency
and after clock driver probe their rate is equal to supported
frequency level. Due to this rcg2_set_rate() would not get
called by the clock framework set_rate call and HW_CLK_CTRL bit
of RCG remains set only. In order to software control the RCG,
HW_CLK_CTRL bit needs to be cleared explicitly so add support
for the same by adding rcg2_prepare().

Change-Id: Ib19831758d54f14573f18e1916ced128d6db0cbb
Signed-off-by: default avatarAmit Nischal <anischal@codeaurora.org>
parent 20768179

drivers/clk/qcom/clk-rcg2.c

+23 −0
Original line number Diff line number Diff line
@@ -572,6 +572,28 @@ static int clk_rcg2_set_floor_rate_and_parent(struct clk_hw *hw, 
	return __clk_rcg2_set_rate(hw, rate, FLOOR);

}



static int clk_rcg2_prepare(struct clk_hw *hw)

{

	struct clk_rcg2 *rcg = to_clk_rcg2(hw);

	u32 cfg;

	int ret;



	ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);

	if (ret)

		return ret;



	if (cfg & CFG_HW_CLK_CTRL_MASK) {

		ret = regmap_update_bits(rcg->clkr.regmap,

			rcg->cmd_rcgr + CFG_REG, CFG_HW_CLK_CTRL_MASK, 0);

		if (ret)

			return ret;



		return update_config(rcg, cfg);

	}



	return 0;

}



static int clk_rcg2_enable(struct clk_hw *hw)

{

	struct clk_rcg2 *rcg = to_clk_rcg2(hw);
@@ -649,6 +671,7 @@ static void clk_rcg2_disable(struct clk_hw *hw) 


const struct clk_ops clk_rcg2_ops = {

	.is_enabled = clk_rcg2_is_enabled,

	.prepare = clk_rcg2_prepare,

	.enable = clk_rcg2_enable,

	.disable = clk_rcg2_disable,

	.get_parent = clk_rcg2_get_parent,