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Commit 712d7c86 authored by Daniel Stone's avatar Daniel Stone Committed by Russell King
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[ARM] OMAP2: Fix definition of SGX clock register bits 



The GFX/SGX functional and interface clocks have different masks, for
some unknown reason, so split EN_SGX_SHIFT into one each for fclk and
iclk.

Correct according to the TRM and the far more important 'does this
actually work at all?' metric.

linux-omap source commit is de1121fdb899f762b9e717f44eaf3fae7c00cd3e.

Signed-off-by: default avatarDaniel Stone <daniel.stone@nokia.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 9cfd985e

arch/arm/mach-omap2/clock34xx.h

+2 −2
Original line number Diff line number Diff line
@@ -1293,7 +1293,7 @@ static struct clk sgx_fck = { 
	.ops		= &clkops_omap2_dflt_wait,

	.init		= &omap2_init_clksel_parent,

	.enable_reg	= OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),

	.enable_bit	= OMAP3430ES2_EN_SGX_SHIFT,

	.enable_bit	= OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,

	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),

	.clksel_mask	= OMAP3430ES2_CLKSEL_SGX_MASK,

	.clksel		= sgx_clksel,
@@ -1307,7 +1307,7 @@ static struct clk sgx_ick = { 
	.parent		= &l3_ick,

	.init		= &omap2_init_clk_clkdm,

	.enable_reg	= OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),

	.enable_bit	= OMAP3430ES2_EN_SGX_SHIFT,

	.enable_bit	= OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,

	.clkdm_name	= "sgx_clkdm",

	.recalc		= &followparent_recalc,

};

arch/arm/mach-omap2/cm-regbits-34xx.h

+6 −2
Original line number Diff line number Diff line
@@ -332,8 +332,12 @@ 
#define OMAP3430ES1_CLKACTIVITY_GFX_MASK		(1 << 0)



/* CM_FCLKEN_SGX */

#define OMAP3430ES2_EN_SGX_SHIFT			1

#define OMAP3430ES2_EN_SGX_MASK				(1 << 1)

#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT		1

#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK		(1 << 1)



/* CM_ICLKEN_SGX */

#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT		0

#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK		(1 << 0)



/* CM_CLKSEL_SGX */

#define OMAP3430ES2_CLKSEL_SGX_SHIFT			0