Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 6fb93a92 authored by Mark Maule's avatar Mark Maule Committed by Tony Luck
Browse files

[IA64] altix: misc pci interrupt related fixes 



Fix a couple of altix interrupt related bugs.

Signed-off-by: default avatarMark Maule <maule@sgi.com>
Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
parent cbb92144

arch/ia64/sn/pci/pcibr/pcibr_provider.c

+2 −2
Original line number Diff line number Diff line
@@ -212,13 +212,13 @@ void pcibr_target_interrupt(struct sn_irq_info *sn_irq_info) 
		    pdi_pcibus_info;



		/* Disable the device's IRQ   */

		pcireg_intr_enable_bit_clr(pcibus_info, bit);

		pcireg_intr_enable_bit_clr(pcibus_info, (1 << bit));



		/* Change the device's IRQ    */

		pcireg_intr_addr_addr_set(pcibus_info, bit, xtalk_addr);



		/* Re-enable the device's IRQ */

		pcireg_intr_enable_bit_set(pcibus_info, bit);

		pcireg_intr_enable_bit_set(pcibus_info, (1 << bit));



		pcibr_force_interrupt(sn_irq_info);

	}

arch/ia64/sn/pci/pcibr/pcibr_reg.c

+1 −1
Original line number Diff line number Diff line
@@ -131,7 +131,7 @@ void pcireg_intr_enable_bit_clr(struct pcibus_info *pcibus_info, uint64_t bits) 
			__sn_clrq_relaxed(&ptr->tio.cp_int_enable, bits);

			break;

		case PCIBR_BRIDGETYPE_PIC:

			__sn_clrq_relaxed(&ptr->pic.p_int_enable, ~bits);

			__sn_clrq_relaxed(&ptr->pic.p_int_enable, bits);

			break;

		default:

			panic