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Commit 6f9fc3ce authored by Jiri Pirko's avatar Jiri Pirko Committed by David S. Miller
Browse files

mlxsw: reg: Add Router Algorithmic LPM Tree Allocation Register definition 



Register serves for allocation and deallocation of LPM search tree.

Signed-off-by: default avatarJiri Pirko <jiri@mellanox.com>
Reviewed-by: default avatarIdo Schimmel <idosch@mellanox.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 5e9c16cc

drivers/net/ethernet/mellanox/mlxsw/reg.h

+53 −1
Original line number Diff line number Diff line
@@ -3,7 +3,7 @@ 
 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.

 * Copyright (c) 2015-2016 Ido Schimmel <idosch@mellanox.com>

 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>

 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>

 * Copyright (c) 2015-2016 Jiri Pirko <jiri@mellanox.com>

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions are met:
@@ -3454,6 +3454,56 @@ static inline void mlxsw_reg_ritr_pack(char *payload, bool enable, 
	mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac);

}



/* RALTA - Router Algorithmic LPM Tree Allocation Register

 * -------------------------------------------------------

 * RALTA is used to allocate the LPM trees of the SHSPM method.

 */

#define MLXSW_REG_RALTA_ID 0x8010

#define MLXSW_REG_RALTA_LEN 0x04



static const struct mlxsw_reg_info mlxsw_reg_ralta = {

	.id = MLXSW_REG_RALTA_ID,

	.len = MLXSW_REG_RALTA_LEN,

};



/* reg_ralta_op

 * opcode (valid for Write, must be 0 on Read)

 * 0 - allocate a tree

 * 1 - deallocate a tree

 * Access: OP

 */

MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2);



enum mlxsw_reg_ralxx_protocol {

	MLXSW_REG_RALXX_PROTOCOL_IPV4,

	MLXSW_REG_RALXX_PROTOCOL_IPV6,

};



/* reg_ralta_protocol

 * Protocol.

 * Deallocation opcode: Reserved.

 * Access: RW

 */

MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4);



/* reg_ralta_tree_id

 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing

 * the tree identifier (managed by software).

 * Note that tree_id 0 is allocated for a default-route tree.

 * Access: Index

 */

MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8);



static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc,

					enum mlxsw_reg_ralxx_protocol protocol,

					u8 tree_id)

{

	MLXSW_REG_ZERO(ralta, payload);

	mlxsw_reg_ralta_op_set(payload, !alloc);

	mlxsw_reg_ralta_protocol_set(payload, protocol);

	mlxsw_reg_ralta_tree_id_set(payload, tree_id);

}



/* MFCR - Management Fan Control Register

 * --------------------------------------

 * This register controls the settings of the Fan Speed PWM mechanism.
@@ -4196,6 +4246,8 @@ static inline const char *mlxsw_reg_id_str(u16 reg_id) 
		return "RGCR";

	case MLXSW_REG_RITR_ID:

		return "RITR";

	case MLXSW_REG_RALTA_ID:

		return "RALTA";

	case MLXSW_REG_MFCR_ID:

		return "MFCR";

	case MLXSW_REG_MFSC_ID: