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Commit 6f3a5124 authored by Sujeev Dias's avatar Sujeev Dias Committed by Gerrit - the friendly Code Review server
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dmaengine: gpi: add GPI dmaengine driver snapshot 



This change ports GPI dmaengine driver and it's dependencies
from msm-4.9 to msm-4.14. All the files are as is from msm-4.9
Additional changes were made to gpi driver to support 4.14
kernel.

This gpi dmaengine driver snapshot is taken as of msm-4.9
commit: e491a3487768
("Merge "msm: vidc: Check for frame size for calculating CF").

CRs-Fixed: 2170554
Change-Id: If04ab521255501b941295ad1de59e5a4775bf849
Signed-off-by: default avatarSujeev Dias <sdias@codeaurora.org>
parent afa6ff3a

Documentation/devicetree/bindings/dma/qcom_gpi.txt

0 → 100644
+101 −0
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Qualcomm Technologies Inc GPI DMA controller



QCOM GPI DMA controller provides DMA capabilities for

peripheral buses such as I2C, UART, and SPI.



==============

Node Structure

==============



Main node properties:



- #dma-cells

  Usage: required

  Value type: <u32>

  Definition: Number of parameters client will provide.  Must be set to 5.

	1st parameter: channel index, 0 for TX, 1 for RX

	2nd parameter: serial engine index

	3rd parameter: bus protocol, 1 for SPI, 2 for UART, 3 for I2C

	4th parameter: channel ring length in transfer ring elements

	5th parameter: event processing priority, set to 0 for lowest latency



- compatible

  Usage: required

  Value type: <string>

  Definition: "qcom,gpi-dma"



- reg

  Usage: required

  Value type: Array of <u32>

  Definition: register address space location and size



- reg-name

  Usage: required

  Value type: <string>

  Definition: register space name, must be "gpi-top"



- interrupts

  Usage: required

  Value type: Array of <u32>

  Definition: Array of tuples which describe interrupt line for each GPII

	instance.



- qcom,max-num-gpii

  Usage: required

  Value type: <u32>

  Definition: Total number of GPII instances available for this controller.



- qcom,gpii-mask

  Usage: required

  Value type: <u32>

  Definition: Bitmap of supported GPII instances in hlos.



- qcom,ev-factor

  Usage: required

  Value type: <u32>

  Definition: Event ring transfer size compare to channel transfer ring. Event

	ring length = ev-factor * transfer ring size



- iommus

  Usage: required

  Value type: <phandle u32 u32>

  Definition: phandle for apps smmu controller and SID, and mask

	for the controller.  For more detail please check binding

	documentation arm,smmu.txt



- qcom,smmu-cfg

  Usage: required

  Value type: <u32>

  Definition: Determine whether GPI driver require to configure SMMU that

	sits behind GPI controller.

	Bit mask:

	BIT(0) : Attach address mapping to endpoint device

	BIT(1) : Set SMMU attribute S1_BYPASS

	BIT(2) : Set SMMU attribute FAST

	BIT(3) : Set SMMU attribute ATOMIC



- qcom,iova-range

  Usage: required if SMMU S1 translation is enabled

  Value type: Array of <u64>

  Definition: Pair of values describing iova base and size to allocate.



========

Example:

========

gpi_dma0: qcom,gpi-dma@0x800000 {

	#dma-cells = <5>;

	compatible = "qcom,gpi-dma";

	reg = <0x800000 0x60000>;

	reg-names = "gpi-top";

	interrupts = <0 244 0>, <0 245 0>, <0 246 0>, <0 247 0>,

                <0 248 0>, <0 249 0>, <0 250 0>, <0 251 0>,

                <0 252 0>, <0 253 0>, <0 254 0>, <0 255 0>,

                <0 256 0>;

	qcom,max-num-gpii = <13>;

	qcom,gpii-mask = <0xfa>;

	qcom,ev-factor = <2>;

	iommus = <&apps_smmu 0x0016 0x0>;

	qcom,smmu-cfg = <0x1>

	qcom,iova-range = <0x0 0x100000 0x0 0x100000>;

	status = "ok";

};

drivers/dma/qcom/Kconfig

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@@ -27,3 +27,22 @@ config QCOM_HIDMA 
	  (user to kernel, kernel to kernel, etc.).  It only supports

	  memcpy interface. The core is not intended for general

	  purpose slave DMA.



config QCOM_GPI_DMA

	tristate "Qualcomm Technologies Inc GPI DMA support"

	depends on ARCH_QCOM

	select DMA_ENGINE

	select DMA_VIRTUAL_CHANNELS

	help

	  Enable support for the QCOM GPI DMA controller. This controller

	  provides DMA capabilities for a variety of peripheral buses such

	  as I2C, UART, and SPI. By using GPI dmaengine driver, bus drivers

	  can use a standardize interface that is protocol independent to

	  transfer data between DDR and peripheral.



config QCOM_GPI_DMA_DEBUG

	bool "Qualcomm Technologies Inc GPI debug support"

	depends on QCOM_GPI_DMA

	help

	  Enable detailed logging for QCOM GPI driver. Extra logging will be

	  helpful when debugging critical issues.

drivers/dma/qcom/Makefile

+1 −0
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@@ -4,3 +4,4 @@ obj-$(CONFIG_QCOM_HIDMA_MGMT) += hdma_mgmt.o 
hdma_mgmt-objs	 := hidma_mgmt.o hidma_mgmt_sys.o

obj-$(CONFIG_QCOM_HIDMA) +=  hdma.o

hdma-objs        := hidma_ll.o hidma.o hidma_dbg.o

obj-$(CONFIG_QCOM_GPI_DMA) += gpi.o