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Commit 6ecf56ae authored by Arun Siluvery's avatar Arun Siluvery Committed by Daniel Vetter
Browse files

drm/i915/gen9: Add WaOCLCoherentLineFlush 



This is mainly required for future enabling of pre-emptive
command execution.

v2: explain purpose of change (Chris)

Reviewed-by: default avatarNick Hoath <nicholas.hoath@intel.com>
Cc: Dave Gordon <david.s.gordon@intel.com>
Signed-off-by: default avatarArun Siluvery <arun.siluvery@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1453412634-29238-9-git-send-email-arun.siluvery@linux.intel.com


Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent a78536e7

drivers/gpu/drm/i915/intel_ringbuffer.c

+4 −0
Original line number Original line Diff line number Diff line
@@ -981,6 +981,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) 
	/* WaDisableSTUnitPowerOptimization:skl,bxt */

	/* WaDisableSTUnitPowerOptimization:skl,bxt */

	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);

	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);





	/* WaOCLCoherentLineFlush:skl,bxt */

	I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |

				    GEN8_LQSC_FLUSH_COHERENT_LINES));



	/* WaEnablePreemptionGranularityControlByUMD:skl,bxt */

	/* WaEnablePreemptionGranularityControlByUMD:skl,bxt */

	ret= wa_ring_whitelist_reg(ring, GEN8_CS_CHICKEN1);

	ret= wa_ring_whitelist_reg(ring, GEN8_CS_CHICKEN1);

	if (ret)

	if (ret)