Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 6dc6826f authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'stmmac-multiqueue-mac-prep' 



Joao Pinto says:

====================
prepare mac operations for multiple queues

As agreed with David Miller, this patch-set is the first of 3 to enable
multiple queues in stmmac.

This first one concentrates on mac operations adding functionalities as:
a) Configuration through DT
b) RX and TX scheduling algorithms programming
b) TX queues weight programming (essential in weightes algorithms)
c) RX enable as DCB or AVB (preparing for future AVB support)
d) Mapping RX queue to DMA channel
e) IRQ treatment prepared for multiple queues
f) Debug dump prepared for multiple queues
g) CBS configuration

In v3 patch-set version I included a new patch to enable CBS configuration
(Patch 9).
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 429a372e 19d91873

Documentation/devicetree/bindings/net/stmmac.txt

+57 −1
Original line number Diff line number Diff line
@@ -72,7 +72,35 @@ Optional properties: 
	- snps,mb: mixed-burst

	- snps,rb: rebuild INCRx Burst

- mdio: with compatible = "snps,dwmac-mdio", create and register mdio bus.



- Multiple RX Queues parameters: below the list of all the parameters to

				 configure the multiple RX queues:

	- snps,rx-queues-to-use: number of RX queues to be used in the driver

	- Choose one of these RX scheduling algorithms:

		- snps,rx-sched-sp: Strict priority

		- snps,rx-sched-wsp: Weighted Strict priority

	- For each RX queue

		- Choose one of these modes:

			- snps,dcb-algorithm: Queue to be enabled as DCB

			- snps,avb-algorithm: Queue to be enabled as AVB

		- snps,map-to-dma-channel: Channel to map

- Multiple TX Queues parameters: below the list of all the parameters to

				 configure the multiple TX queues:

	- snps,tx-queues-to-use: number of TX queues to be used in the driver

	- Choose one of these TX scheduling algorithms:

		- snps,tx-sched-wrr: Weighted Round Robin

		- snps,tx-sched-wfq: Weighted Fair Queuing

		- snps,tx-sched-dwrr: Deficit Weighted Round Robin

		- snps,tx-sched-sp: Strict priority

	- For each TX queue

		- snps,weight: TX queue weight (if using a DCB weight algorithm)

		- Choose one of these modes:

			- snps,dcb-algorithm: TX queue will be working in DCB

			- snps,avb-algorithm: TX queue will be working in AVB

		- Configure Credit Base Shaper (if AVB Mode selected):

			- snps,send_slope: enable Low Power Interface

			- snps,idle_slope: unlock on WoL

			- snps,high_credit: max write outstanding req. limit

			- snps,low_credit: max read outstanding req. limit

Examples:



	stmmac_axi_setup: stmmac-axi-config {
@@ -81,6 +109,32 @@ Examples: 
		snps,blen = <256 128 64 32 0 0 0>;

	};



	mtl_rx_setup: rx-queues-config {

		snps,rx-queues-to-use = <1>;

		snps,rx-sched-sp;

		queue0 {

			snps,dcb-algorithm;

			snps,map-to-dma-channel = <0x0>;

		};

	};



	mtl_tx_setup: tx-queues-config {

		snps,tx-queues-to-use = <2>;

		snps,tx-sched-wrr;

		queue0 {

			snps,weight = <0x10>;

			snps,dcb-algorithm;

		};



		queue1 {

			snps,avb-algorithm;

			snps,send_slope = <0x1000>;

			snps,idle_slope = <0x1000>;

			snps,high_credit = <0x3E800>;

			snps,low_credit = <0xFFC18000>;

		};

	};



	gmac0: ethernet@e0800000 {

		compatible = "st,spear600-gmac";

		reg = <0xe0800000 0x8000>;
@@ -104,4 +158,6 @@ Examples: 
			phy1: ethernet-phy@0 {

			};

		};

		snps,mtl-rx-config = <&mtl_rx_setup>;

		snps,mtl-tx-config = <&mtl_tx_setup>;

	};

drivers/net/ethernet/stmicro/stmmac/common.h

+19 −3
Original line number Diff line number Diff line
@@ -457,17 +457,32 @@ struct stmmac_ops { 
	/* Enable and verify that the IPC module is supported */

	int (*rx_ipc)(struct mac_device_info *hw);

	/* Enable RX Queues */

	void (*rx_queue_enable)(struct mac_device_info *hw, u32 queue);

	void (*rx_queue_enable)(struct mac_device_info *hw, u8 mode, u32 queue);

	/* Program RX Algorithms */

	void (*prog_mtl_rx_algorithms)(struct mac_device_info *hw, u32 rx_alg);

	/* Program TX Algorithms */

	void (*prog_mtl_tx_algorithms)(struct mac_device_info *hw, u32 tx_alg);

	/* Set MTL TX queues weight */

	void (*set_mtl_tx_queue_weight)(struct mac_device_info *hw,

					u32 weight, u32 queue);

	/* RX MTL queue to RX dma mapping */

	void (*map_mtl_to_dma)(struct mac_device_info *hw, u32 queue, u32 chan);

	/* Configure AV Algorithm */

	void (*config_cbs)(struct mac_device_info *hw, u32 send_slope,

			   u32 idle_slope, u32 high_credit, u32 low_credit,

			   u32 queue);

	/* Dump MAC registers */

	void (*dump_regs)(struct mac_device_info *hw, u32 *reg_space);

	/* Handle extra events on specific interrupts hw dependent */

	int (*host_irq_status)(struct mac_device_info *hw,

			       struct stmmac_extra_stats *x);

	/* Handle MTL interrupts */

	int (*host_mtl_irq_status)(struct mac_device_info *hw, u32 chan);

	/* Multicast filter setting */

	void (*set_filter)(struct mac_device_info *hw, struct net_device *dev);

	/* Flow control setting */

	void (*flow_ctrl)(struct mac_device_info *hw, unsigned int duplex,

			  unsigned int fc, unsigned int pause_time);

			  unsigned int fc, unsigned int pause_time, u32 tx_cnt);

	/* Set power management mode (e.g. magic frame) */

	void (*pmt)(struct mac_device_info *hw, unsigned long mode);

	/* Set/Get Unicast MAC addresses */
@@ -480,7 +495,8 @@ struct stmmac_ops { 
	void (*reset_eee_mode)(struct mac_device_info *hw);

	void (*set_eee_timer)(struct mac_device_info *hw, int ls, int tw);

	void (*set_eee_pls)(struct mac_device_info *hw, int link);

	void (*debug)(void __iomem *ioaddr, struct stmmac_extra_stats *x);

	void (*debug)(void __iomem *ioaddr, struct stmmac_extra_stats *x,

		      u32 rx_queues, u32 tx_queues);

	/* PCS calls */

	void (*pcs_ctrl_ane)(void __iomem *ioaddr, bool ane, bool srgmi_ral,

			     bool loopback);

drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c

+4 −2
Original line number Diff line number Diff line
@@ -216,7 +216,8 @@ static void dwmac1000_set_filter(struct mac_device_info *hw, 




static void dwmac1000_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,

				unsigned int fc, unsigned int pause_time)

				unsigned int fc, unsigned int pause_time,

				u32 tx_cnt)

{

	void __iomem *ioaddr = hw->pcsr;

	/* Set flow such that DZPQ in Mac Register 6 is 0,
@@ -412,7 +413,8 @@ static void dwmac1000_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv) 
	dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);

}



static void dwmac1000_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x)

static void dwmac1000_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x,

			    u32 rx_queues, u32 tx_queues)

{

	u32 value = readl(ioaddr + GMAC_DEBUG);

drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c

+2 −1
Original line number Diff line number Diff line
@@ -131,7 +131,8 @@ static void dwmac100_set_filter(struct mac_device_info *hw, 
}



static void dwmac100_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,

			       unsigned int fc, unsigned int pause_time)

			       unsigned int fc, unsigned int pause_time,

			       u32 tx_cnt)

{

	void __iomem *ioaddr = hw->pcsr;

	unsigned int flow = MAC_FLOW_CTRL_ENABLE;

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

+58 −1
Original line number Diff line number Diff line
@@ -164,8 +164,25 @@ enum power_event { 
#define GMAC_HI_REG_AE			BIT(31)



/*  MTL registers */

#define MTL_OPERATION_MODE		0x00000c00

#define MTL_OPERATION_SCHALG_MASK	GENMASK(6, 5)

#define MTL_OPERATION_SCHALG_WRR	(0x0 << 5)

#define MTL_OPERATION_SCHALG_WFQ	(0x1 << 5)

#define MTL_OPERATION_SCHALG_DWRR	(0x2 << 5)

#define MTL_OPERATION_SCHALG_SP		(0x3 << 5)

#define MTL_OPERATION_RAA		BIT(2)

#define MTL_OPERATION_RAA_SP		(0x0 << 2)

#define MTL_OPERATION_RAA_WSP		(0x1 << 2)



#define MTL_INT_STATUS			0x00000c20

#define MTL_INT_Q0			BIT(0)

#define MTL_INT_QX(x)			BIT(x)



#define MTL_RXQ_DMA_MAP0		0x00000c30 /* queue 0 to 3 */

#define MTL_RXQ_DMA_MAP1		0x00000c34 /* queue 4 to 7 */

#define MTL_RXQ_DMA_Q04MDMACH_MASK	GENMASK(3, 0)

#define MTL_RXQ_DMA_Q04MDMACH(x)	((x) << 0)

#define MTL_RXQ_DMA_QXMDMACH_MASK(x)	GENMASK(11 + (8 * ((x) - 1)), 8 * (x))

#define MTL_RXQ_DMA_QXMDMACH(chan, q)	((chan) << (8 * (q)))



#define MTL_CHAN_BASE_ADDR		0x00000d00

#define MTL_CHAN_BASE_OFFSET		0x40
@@ -216,6 +233,46 @@ enum power_event { 
#define MTL_OP_MODE_RTC_96		(2 << MTL_OP_MODE_RTC_SHIFT)

#define MTL_OP_MODE_RTC_128		(3 << MTL_OP_MODE_RTC_SHIFT)



/* MTL ETS Control register */

#define MTL_ETS_CTRL_BASE_ADDR		0x00000d10

#define MTL_ETS_CTRL_BASE_OFFSET	0x40

#define MTL_ETSX_CTRL_BASE_ADDR(x)	(MTL_ETS_CTRL_BASE_ADDR + \

					((x) * MTL_ETS_CTRL_BASE_OFFSET))



#define MTL_ETS_CTRL_CC			BIT(3)

#define MTL_ETS_CTRL_AVALG		BIT(2)



/* MTL Queue Quantum Weight */

#define MTL_TXQ_WEIGHT_BASE_ADDR	0x00000d18

#define MTL_TXQ_WEIGHT_BASE_OFFSET	0x40

#define MTL_TXQX_WEIGHT_BASE_ADDR(x)	(MTL_TXQ_WEIGHT_BASE_ADDR + \

					((x) * MTL_TXQ_WEIGHT_BASE_OFFSET))

#define MTL_TXQ_WEIGHT_ISCQW_MASK	GENMASK(20, 0)



/* MTL sendSlopeCredit register */

#define MTL_SEND_SLP_CRED_BASE_ADDR	0x00000d1c

#define MTL_SEND_SLP_CRED_OFFSET	0x40

#define MTL_SEND_SLP_CREDX_BASE_ADDR(x)	(MTL_SEND_SLP_CRED_BASE_ADDR + \

					((x) * MTL_SEND_SLP_CRED_OFFSET))



#define MTL_SEND_SLP_CRED_SSC_MASK	GENMASK(13, 0)



/* MTL hiCredit register */

#define MTL_HIGH_CRED_BASE_ADDR		0x00000d20

#define MTL_HIGH_CRED_OFFSET		0x40

#define MTL_HIGH_CREDX_BASE_ADDR(x)	(MTL_HIGH_CRED_BASE_ADDR + \

					((x) * MTL_HIGH_CRED_OFFSET))



#define MTL_HIGH_CRED_HC_MASK		GENMASK(28, 0)



/* MTL loCredit register */

#define MTL_LOW_CRED_BASE_ADDR		0x00000d24

#define MTL_LOW_CRED_OFFSET		0x40

#define MTL_LOW_CREDX_BASE_ADDR(x)	(MTL_LOW_CRED_BASE_ADDR + \

					((x) * MTL_LOW_CRED_OFFSET))



#define MTL_HIGH_CRED_LC_MASK		GENMASK(28, 0)



/*  MTL debug */

#define MTL_DEBUG_TXSTSFSTS		BIT(5)

#define MTL_DEBUG_TXFSTS		BIT(4)