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Commit 6db957db authored by Sanchayan Maity's avatar Sanchayan Maity Committed by Shawn Guo
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ARM: dts: imx6qdl-apalis: split usdhc1 pinctrl to support 4- and 8-bit 



Split the pinctrl property for usdhc1 into a 4-bit SD interface
and an extension to 8-bit. This is required to support both 8-bit
and 4-bit interface on usdhc1 as per the carrier board.

Signed-off-by: default avatarSanchayan Maity <maitysanchayan@gmail.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent b5912b6f

arch/arm/boot/dts/imx6qdl-apalis.dtsi

+8 −3
Original line number Diff line number Diff line 
/*

 * Copyright 2014-2016 Toradex AG

 * Copyright 2014-2017 Toradex AG

 * Copyright 2012 Freescale Semiconductor, Inc.

 * Copyright 2011 Linaro Ltd.

 *
@@ -460,7 +460,7 @@ 
/* MMC1 */

&usdhc1 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_usdhc1>;

	pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit>;

	vqmmc-supply = <&reg_3p3v>;

	bus-width = <8>;

	voltage-ranges = <3300 3300>;
@@ -912,7 +912,7 @@ 
		>;

	};



	pinctrl_usdhc1: usdhc1grp {

	pinctrl_usdhc1_4bit: usdhc1grp_4bit {

		fsl,pins = <

			MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17071

			MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10071
@@ -920,6 +920,11 @@ 
			MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071

			MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071

			MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071

		>;

	};



	pinctrl_usdhc1_8bit: usdhc1grp_8bit {

		fsl,pins = <

			MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071

			MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071

			MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071