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Commit 6db0f7cc authored by Jonathan Cameron's avatar Jonathan Cameron
Browse files

Merge tag 'ib-mfd-iio-pwm-4.11' into test 

Immutable branch between MFD, IIO and PWM due for the v4.11 merge window

Pulled into IIO to allow follow up series of triggered capture for the
STM32 ADCs.
parents 1dc2af87 93fbe91b

Documentation/ABI/testing/sysfs-bus-iio-timer-stm32

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What:		/sys/bus/iio/devices/triggerX/master_mode_available

KernelVersion:	4.11

Contact:	benjamin.gaignard@st.com

Description:

		Reading returns the list possible master modes which are:

		- "reset"     :	The UG bit from the TIMx_EGR register is used as trigger output (TRGO).

		- "enable"    : The Counter Enable signal CNT_EN is used as trigger output.

		- "update"    : The update event is selected as trigger output.

				For instance a master timer can then be used as a prescaler for a slave timer.

		- "compare_pulse" : The trigger output send a positive pulse when the CC1IF flag is to be set.

		- "OC1REF"    : OC1REF signal is used as trigger output.

		- "OC2REF"    : OC2REF signal is used as trigger output.

		- "OC3REF"    : OC3REF signal is used as trigger output.

		- "OC4REF"    : OC4REF signal is used as trigger output.



What:		/sys/bus/iio/devices/triggerX/master_mode

KernelVersion:	4.11

Contact:	benjamin.gaignard@st.com

Description:

		Reading returns the current master modes.

		Writing set the master mode



What:		/sys/bus/iio/devices/triggerX/sampling_frequency

KernelVersion:	4.11

Contact:	benjamin.gaignard@st.com

Description:

		Reading returns the current sampling frequency.

		Writing an value different of 0 set and start sampling.

		Writing 0 stop sampling.

Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt

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STMicroelectronics STM32 Timers IIO timer bindings



Must be a sub-node of an STM32 Timers device tree node.

See ../mfd/stm32-timers.txt for details about the parent node.



Required parameters:

- compatible:	Must be "st,stm32-timer-trigger".

- reg:		Identify trigger hardware block.



Example:

	timers@40010000 {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "st,stm32-timers";

		reg = <0x40010000 0x400>;

		clocks = <&rcc 0 160>;

		clock-names = "clk_int";



		timer@0 {

			compatible = "st,stm32-timer-trigger";

			reg = <0>;

		};

	};

Documentation/devicetree/bindings/mfd/stm32-timers.txt

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STM32 Timers driver bindings



This IP provides 3 types of timer along with PWM functionality:

- advanced-control timers consist of a 16-bit auto-reload counter driven by a programmable

  prescaler, break input feature, PWM outputs and complementary PWM ouputs channels.

- general-purpose timers consist of a 16-bit or 32-bit auto-reload counter driven by a

  programmable prescaler and PWM outputs.

- basic timers consist of a 16-bit auto-reload counter driven by a programmable prescaler.



Required parameters:

- compatible: must be "st,stm32-timers"



- reg:			Physical base address and length of the controller's

			registers.

- clock-names:		Set to "int".

- clocks: 		Phandle to the clock used by the timer module.

			For Clk properties, please refer to ../clock/clock-bindings.txt



Optional parameters:

- resets:		Phandle to the parent reset controller.

			See ../reset/st,stm32-rcc.txt



Optional subnodes:

- pwm:			See ../pwm/pwm-stm32.txt

- timer:		See ../iio/timer/stm32-timer-trigger.txt



Example:

	timers@40010000 {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "st,stm32-timers";

		reg = <0x40010000 0x400>;

		clocks = <&rcc 0 160>;

		clock-names = "clk_int";



		pwm {

			compatible = "st,stm32-pwm";

			pinctrl-0	= <&pwm1_pins>;

			pinctrl-names	= "default";

		};



		timer@0 {

			compatible = "st,stm32-timer-trigger";

			reg = <0>;

		};

	};

Documentation/devicetree/bindings/pwm/pwm-stm32.txt

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STMicroelectronics STM32 Timers PWM bindings



Must be a sub-node of an STM32 Timers device tree node.

See ../mfd/stm32-timers.txt for details about the parent node.



Required parameters:

- compatible:		Must be "st,stm32-pwm".

- pinctrl-names: 	Set to "default".

- pinctrl-0: 		List of phandles pointing to pin configuration nodes for PWM module.

			For Pinctrl properties see ../pinctrl/pinctrl-bindings.txt



Optional parameters:

- st,breakinput:	One or two <index level filter> to describe break input configurations.

			"index" indicates on which break input (0 or 1) the configuration

			should be applied.

			"level" gives the active level (0=low or 1=high) of the input signal

			for this configuration.

			"filter" gives the filtering value to be applied.



Example:

	timers@40010000 {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "st,stm32-timers";

		reg = <0x40010000 0x400>;

		clocks = <&rcc 0 160>;

		clock-names = "clk_int";



		pwm {

			compatible = "st,stm32-pwm";

			pinctrl-0	= <&pwm1_pins>;

			pinctrl-names	= "default";

			st,breakinput = <0 1 5>;

		};

	};

drivers/iio/trigger/Kconfig

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@@ -24,6 +24,15 @@ config IIO_INTERRUPT_TRIGGER 
	  To compile this driver as a module, choose M here: the

	  module will be called iio-trig-interrupt.



config IIO_STM32_TIMER_TRIGGER

	tristate "STM32 Timer Trigger"

	depends on (ARCH_STM32 && OF && MFD_STM32_TIMERS) || COMPILE_TEST

	help

	  Select this option to enable STM32 Timer Trigger



	  To compile this driver as a module, choose M here: the

	  module will be called stm32-timer-trigger.



config IIO_TIGHTLOOP_TRIGGER

	tristate "A kthread based hammering loop trigger"

	depends on IIO_SW_TRIGGER