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Commit 6d7746c6 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Enable the OSM clock controller for sm6150"

parents 305b293c 9243d3c6

arch/arm64/boot/dts/qcom/sm6150.dtsi

+16 −4
Original line number Diff line number Diff line
@@ -17,7 +17,7 @@ 
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>

#include <dt-bindings/clock/qcom,gcc-sm6150.h>

#include <dt-bindings/clock/qcom,camcc-sm6150.h>

#include <dt-bindings/clock/qcom,cpucc-sm6150.h>

#include <dt-bindings/clock/qcom,cpucc-sm8150.h>

#include <dt-bindings/clock/qcom,dispcc-sm6150.h>

#include <dt-bindings/clock/qcom,gpucc-sm6150.h>

#include <dt-bindings/clock/qcom,videocc-sm6150.h>
@@ -1069,9 +1069,20 @@ 
		#reset-cells = <1>;

	};



	clock_cpucc: qcom,cpucc {

		compatible = "qcom,dummycc";

		clock-output-names = "cpucc_clocks";

	cpucc_debug: syscon@182a0018 {

		compatible = "syscon";

		reg = <0x182a0018 0x4>;

	};



	clock_cpucc: qcom,cpucc@18321000 {

		compatible = "qcom,clk-cpu-osm-sm6150";

		reg = <0x18321000 0x1400>,

			<0x18323000 0x1400>,

			<0x18325800 0x1400>;

		reg-names = "osm_l3_base", "osm_pwrcl_base",

			"osm_perfcl_base";

		l3-devs = <&cpu0_cpu_l3_lat &cpu6_cpu_l3_lat

			&cdsp_cdsp_l3_lat &msm_gpu>;

		#clock-cells = <1>;

	};
@@ -1082,6 +1093,7 @@ 
		qcom,camcc = <&clock_camcc>;

		qcom,dispcc = <&clock_dispcc>;

		qcom,gpucc = <&clock_gpucc>;

		qcom,cpucc = <&cpucc_debug>;

		clock-names = "cxo";

		clocks = <&clock_rpmh RPMH_CXO_CLK>;

		#clock-cells = <1>;

drivers/clk/qcom/debugcc-sm6150.c

+14 −1
Original line number Diff line number Diff line
@@ -255,6 +255,9 @@ static const char *const debug_mux_parent_names[] = { 
	"video_cc_venus_ctl_axi_clk",

	"video_cc_venus_ctl_core_clk",

	"video_cc_xo_clk",

	"l3_clk",

	"pwrcl_clk",

	"perfcl_clk",

};



static struct clk_debug_mux gcc_debug_mux = {
@@ -682,7 +685,7 @@ static struct clk_debug_mux gcc_debug_mux = { 
		{ "gpu_cc_sleep_clk", 0x144, 1, GPU_CC,

			0x16, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 },

		{ "measure_only_bimc_clk", 0xC2, 1, GCC,

			0xC2, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x62004, 0x62008 },

			0xBF, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x62004, 0x62008 },

		{ "measure_only_cnoc_clk", 0x15, 1, GCC,

			0x15, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x62004, 0x62008 },

		{ "measure_only_ipa_2x_clk", 0x128, 1, GCC,
@@ -711,6 +714,12 @@ static struct clk_debug_mux gcc_debug_mux = { 
			0x1, 0x3F, 0, 0x7, 0, 5, 0xA4C, 0xA30, 0xA38 },

		{ "video_cc_xo_clk", 0x48, 1, VIDEO_CC,

			0xC, 0x3F, 0, 0x7, 0, 5, 0xA4C, 0xA30, 0xA38 },

		{ "l3_clk", 0xD6, 4, CPU_CC,

			0x46, 0x7F, 4, 0xf, 11, 1, 0x0, 0x0, U32_MAX, 16 },

		{ "pwrcl_clk", 0xD6, 4, CPU_CC,

			0x44, 0x7F, 4, 0xf, 11, 1, 0x0, 0x0, U32_MAX, 16 },

		{ "perfcl_clk", 0xD6, 4, CPU_CC,

			0x45, 0x7F, 4, 0xf, 11, 1, 0x0, 0x0, U32_MAX, 16 },

	),

	.hw.init = &(struct clk_init_data){

		.name = "gcc_debug_mux",
@@ -784,6 +793,10 @@ static int clk_debug_sm6150_probe(struct platform_device *pdev) 
	if (ret)

		return ret;



	ret = map_debug_bases(pdev, "qcom,cpucc", CPU_CC);

	if (ret)

		return ret;



	clk = devm_clk_register(&pdev->dev, &gcc_debug_mux.hw);

	if (IS_ERR(clk)) {

		dev_err(&pdev->dev, "Unable to register GCC debug mux\n");

include/dt-bindings/clock/qcom,cpucc-sm6150.h

deleted100644 → 0
+0 −32
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef _DT_BINDINGS_CLK_QCOM_CPU_CC_SM6150_H

#define _DT_BINDINGS_CLK_QCOM_CPU_CC_SM6150_H



#define PWRCL_CLK						0

#define PERFCL_CLK						1

#define L3_CLK							2

#define L3_CLUSTER0_VOTE_CLK					3

#define L3_CLUSTER1_VOTE_CLK					4

#define CPU0_PWRCL_CLK						5

#define CPU1_PWRCL_CLK						6

#define CPU2_PWRCL_CLK						7

#define CPU3_PWRCL_CLK						8

#define CPU4_PWRCL_CLK						9

#define CPU5_PWRCL_CLK						10

#define CPU6_PERFCL_CLK						11

#define CPU7_PERFCL_CLK						12

#define L3_MISC_VOTE_CLK					13



#endif