Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 6d0ef2a8 authored by Sagar Dharia's avatar Sagar Dharia Committed by Girish Mahadevan
Browse files

ARM: dts: msm: Add HS-UART and fix 2 wire pin setting for SDM855 



QUPv3 SE13 is used as HS-UART by BT on SDM855. Add active and sleep
pinctrl settings for its GPIOs.

Change-Id: I939c1f93e94382d92e4d2b8995e2922fd4ee8c36
Signed-off-by: default avatarSagar Dharia <sdharia@codeaurora.org>
Signed-off-by: default avatarGirish Mahadevan <girishm@codeaurora.org>
parent b1d9a051

arch/arm64/boot/dts/qcom/sdm855-pinctrl.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -70,7 +70,7 @@ 
			qupv3_se12_2uart_active: qupv3_se12_2uart_active {

				mux {

					pins = "gpio85", "gpio86";

					function = "qup10";

					function = "qup12";

				};



				config {
@@ -94,8 +94,8 @@ 
			};

		};



		qupv3_se17_4uart_pins: qupv3_se17_4uart_pins {

			qupv3_se17_4uart_active: qupv3_se17_4uart_active {

		qupv3_se13_4uart_pins: qupv3_se13_4uart_pins {

			qupv3_se13_4uart_active: qupv3_se13_4uart_active {

				mux {

					pins = "gpio43", "gpio44", "gpio45",

								"gpio46";
@@ -110,7 +110,7 @@ 
				};

			};



			qupv3_se17_4uart_sleep: qupv3_se17_4uart_sleep {

			qupv3_se13_4uart_sleep: qupv3_se13_4uart_sleep {

				mux {

					pins = "gpio43", "gpio44", "gpio45",

								"gpio46";

arch/arm64/boot/dts/qcom/sdm855-qupv3.dtsi

+19 −19
Original line number Diff line number Diff line
@@ -398,6 +398,25 @@ 
		status = "disabled";

	};



	/* 4-wire UART */

	qupv3_se13_4uart: qcom,qup_uart@0xa94000 {

		compatible = "qcom,msm-geni-serial-hs", "qcom,msm-geni-uart";

		reg = <0xa94000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S5_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se13_4uart_active>;

		pinctrl-1 = <&qupv3_se13_4uart_sleep>;

		interrupts-extended = <GIC_SPI 358 0>,

				<&tlmm 46 0>;

		qcom,wrapper-core = <&qupv3_1>;

		qcom,wakeup-byte = <0xFD>;

		status = "disabled";

	};



	/* I2C */

	qupv3_se8_i2c: i2c@a80000 {

		compatible = "qcom,i2c-geni";
@@ -666,25 +685,6 @@ 
		};

	};



	/* 4-wire UART */

	qupv3_se17_4uart: qcom,qup_uart@0xc8c000 {

		compatible = "qcom,msm-geni-serial-hs", "qcom,msm-geni-uart";

		reg = <0xc8c000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S3_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se17_4uart_active>;

		pinctrl-1 = <&qupv3_se17_4uart_sleep>;

		interrupts-extended = <GIC_SPI 585 0>,

				<&tlmm 46 0>;

		qcom,wrapper-core = <&qupv3_2>;

		qcom,wakeup-byte = <0xFD>;

		status = "disabled";

	};



	/* I2C */

	qupv3_se14_i2c: i2c@0xc80000 {

		compatible = "qcom,i2c-geni";

arch/arm64/boot/dts/qcom/sdm855.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -41,7 +41,7 @@ 


	aliases {

		serial0 = &qupv3_se12_2uart;

		hsuart0 = &qupv3_se17_4uart;

		hsuart0 = &qupv3_se13_4uart;

	};



	cpus {