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Commit 6cb86873 authored by Deepak Katragadda's avatar Deepak Katragadda Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Add dummy GDSC support for SDM855 



Add dummy GDSC nodes for clients to use on SDM855.

Change-Id: Ica53831607605b1b5d529a70cb3c3a2eed3f18be
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent 21315046

arch/arm64/boot/dts/qcom/sdm855-gdsc.dtsi

0 → 100644
+247 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2017, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



&soc {

	/* GDSCs in Global CC */

	emac_gdsc: qcom,gdsc@0x106004 {

		compatible = "regulator-fixed";

		regulator-name = "emac_gdsc";

		reg = <0x106004 0x4>;

		status = "disabled";

	};



	pcie_0_gdsc: qcom,gdsc@0x16b004 {

		compatible = "regulator-fixed";

		regulator-name = "pcie_0_gdsc";

		reg = <0x16b004 0x4>;

		status = "disabled";

	};



	pcie_1_gdsc: qcom,gdsc@0x18d004 {

		compatible = "regulator-fixed";

		regulator-name = "pcie_1_gdsc";

		reg = <0x18d004 0x4>;

		status = "disabled";

	};



	ufs_card_gdsc: qcom,gdsc@0x175004 {

		compatible = "regulator-fixed";

		regulator-name = "ufs_card_gdsc";

		reg = <0x175004 0x4>;

		status = "disabled";

	};



	ufs_phy_gdsc: qcom,gdsc@0x177004 {

		compatible = "regulator-fixed";

		regulator-name = "ufs_phy_gdsc";

		reg = <0x177004 0x4>;

		status = "disabled";

	};



	usb30_prim_gdsc: qcom,gdsc@0x10f004 {

		compatible = "regulator-fixed";

		regulator-name = "usb30_prim_gdsc";

		reg = <0x10f004 0x4>;

		status = "disabled";

	};



	usb30_sec_gdsc: qcom,gdsc@0x110004 {

		compatible = "regulator-fixed";

		regulator-name = "usb30_sec_gdsc";

		reg = <0x110004 0x4>;

		status = "disabled";

	};



	hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc: qcom,gdsc@0x17d030 {

		compatible = "regulator-fixed";

		regulator-name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc";

		reg = <0x17d030 0x4>;

		qcom,no-status-check-on-disable;

		qcom,gds-timeout = <500>;

		status = "disabled";

	};



	hlos1_vote_aggre_noc_mmu_tbu1_gdsc: qcom,gdsc@0x17d034 {

		compatible = "regulator-fixed";

		regulator-name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc";

		reg = <0x17d034 0x4>;

		qcom,no-status-check-on-disable;

		qcom,gds-timeout = <500>;

		status = "disabled";

	};



	hlos1_vote_aggre_noc_mmu_tbu2_gdsc: qcom,gdsc@0x17d038 {

		compatible = "regulator-fixed";

		regulator-name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc";

		reg = <0x17d038 0x4>;

		qcom,no-status-check-on-disable;

		qcom,gds-timeout = <500>;

		status = "disabled";

	};



	hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc: qcom,gdsc@0x17d03c {

		compatible = "regulator-fixed";

		regulator-name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc";

		reg = <0x17d03c 0x4>;

		qcom,no-status-check-on-disable;

		qcom,gds-timeout = <500>;

		status = "disabled";

	};



	hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@0x17d040 {

		compatible = "regulator-fixed";

		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc";

		reg = <0x17d040 0x4>;

		qcom,no-status-check-on-disable;

		qcom,gds-timeout = <500>;

		status = "disabled";

	};



	hlos1_vote_mmnoc_mmu_tbu_sf_gdsc: qcom,gdsc@0x17d044 {

		compatible = "regulator-fixed";

		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc";

		reg = <0x17d044 0x4>;

		qcom,no-status-check-on-disable;

		qcom,gds-timeout = <500>;

		status = "disabled";

	};



	hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@0x17d048 {

		compatible = "regulator-fixed";

		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc";

		reg = <0x17d048 0x4>;

		qcom,no-status-check-on-disable;

		qcom,gds-timeout = <500>;

		status = "disabled";

	};



	hlos1_vote_turing_mmu_tbu_gdsc: qcom,gdsc@0x17d04c {

		compatible = "regulator-fixed";

		regulator-name = "hlos1_vote_turing_mmu_tbu_gdsc";

		reg = <0x17d04c 0x4>;

		qcom,no-status-check-on-disable;

		qcom,gds-timeout = <500>;

		status = "disabled";

	};



	/* GDSCs in Camera CC */

	bps_gdsc: qcom,gdsc@0xad07004 {

		compatible = "regulator-fixed";

		regulator-name = "bps_gdsc";

		reg = <0xad07004 0x4>;

		status = "disabled";

	};



	ipe_0_gdsc: qcom,gdsc@0xad08004 {

		compatible = "regulator-fixed";

		regulator-name = "ipe_0_gdsc";

		reg = <0xad08004 0x4>;

		status = "disabled";

	};



	ipe_1_gdsc: qcom,gdsc@0xad09004 {

		compatible = "regulator-fixed";

		regulator-name = "ipe_1_gdsc";

		reg = <0xad09004 0x4>;

		status = "disabled";

	};



	ife_0_gdsc: qcom,gdsc@0xad0a004 {

		compatible = "regulator-fixed";

		regulator-name = "ife_0_gdsc";

		reg = <0xad0a004 0x4>;

		status = "disabled";

	};



	ife_1_gdsc: qcom,gdsc@0xad0b004 {

		compatible = "regulator-fixed";

		regulator-name = "ife_1_gdsc";

		reg = <0xad0b004 0x4>;

		status = "disabled";

	};



	titan_top_gdsc: qcom,gdsc@0xad0c1bc {

		compatible = "regulator-fixed";

		regulator-name = "titan_top_gdsc";

		reg = <0xad0c1bc 0x4>;

		status = "disabled";

	};



	/* GDSCs in Display CC */

	mdss_core_gdsc: qcom,gdsc@0xaf03000 {

		compatible = "regulator-fixed";

		regulator-name = "mdss_core_gdsc";

		reg = <0xaf03000 0x4>;

		qcom,support-hw-trigger;

		status = "disabled";

	};



	/* GDSCs in Graphics CC */

	gpu_cx_hw_ctrl: syscon@0x2c91540 {

		compatible = "syscon";

		reg = <0x2c91540 0x4>;

	};



	gpu_cx_gdsc: qcom,gdsc@0x2c9106c {

		compatible = "regulator-fixed";

		regulator-name = "gpu_cx_gdsc";

		reg = <0x2c9106c 0x4>;

		hw-ctrl-addr = <&gpu_cx_hw_ctrl>;

		qcom,no-status-check-on-disable;

		qcom,gds-timeout = <500>;

		status = "disabled";

	};



	gpu_gx_domain_addr: syscon@0x2c91508 {

		compatible = "syscon";

		reg = <0x2c91508 0x4>;

	};



	gpu_gx_sw_reset: syscon@0x2c91008 {

		compatible = "syscon";

		reg = <0x2c91008 0x4>;

	};



	gpu_gx_gdsc: qcom,gdsc@0x2c9100c {

		compatible = "regulator-fixed";

		regulator-name = "gpu_gx_gdsc";

		reg = <0x2c9100c 0x4>;

		domain-addr = <&gpu_gx_domain_addr>;

		sw-reset = <&gpu_gx_sw_reset>;

		qcom,reset-aon-logic;

		qcom,toggle-sw-collapse-in-disable;

		status = "disabled";

	};



	/* GDSCs in Video CC */

	mvsc_gdsc: qcom,gdsc@0xab00814 {

		compatible = "regulator-fixed";

		regulator-name = "mvsc_gdsc";

		reg = <0xab00814 0x4>;

		status = "disabled";

	};



	mvs0_gdsc: qcom,gdsc@0xab00874 {

		compatible = "regulator-fixed";

		regulator-name = "mvs0_gdsc";

		reg = <0xab00874 0x4>;

		status = "disabled";

	};



	mvs1_gdsc: qcom,gdsc@0xab008b4 {

		compatible = "regulator-fixed";

		regulator-name = "mvs1_gdsc";

		reg = <0xab008b4 0x4>;

		status = "disabled";

	};

};

arch/arm64/boot/dts/qcom/sdm855.dtsi

+110 −0
Original line number Diff line number Diff line
@@ -206,6 +206,8 @@ 
	soc: soc { };

};



#include "sdm855-gdsc.dtsi"



&soc {

	#address-cells = <1>;

	#size-cells = <1>;
@@ -347,3 +349,111 @@ 
		#reset-cells = <1>;

	};

};



&emac_gdsc {

	status = "ok";

};



&pcie_0_gdsc {

	status = "ok";

};



&pcie_1_gdsc {

	status = "ok";

};



&ufs_card_gdsc {

	status = "ok";

};



&ufs_phy_gdsc {

	status = "ok";

};



&usb30_prim_gdsc {

	status = "ok";

};



&usb30_sec_gdsc {

	status = "ok";

};



&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc {

	status = "ok";

};



&hlos1_vote_aggre_noc_mmu_tbu1_gdsc {

	status = "ok";

};



&hlos1_vote_aggre_noc_mmu_tbu2_gdsc {

	status = "ok";

};



&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc {

	status = "ok";

};



&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {

	status = "ok";

};



&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc {

	status = "ok";

};



&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc {

	status = "ok";

};



&hlos1_vote_turing_mmu_tbu_gdsc {

	status = "ok";

};



&bps_gdsc {

	status = "ok";

};



&ipe_0_gdsc {

	status = "ok";

};



&ipe_1_gdsc {

	status = "ok";

};



&ife_0_gdsc {

	status = "ok";

};



&ife_1_gdsc {

	status = "ok";

};



&titan_top_gdsc {

	status = "ok";

};



&mdss_core_gdsc {

	status = "ok";

};



&gpu_cx_gdsc {

	status = "ok";

};



&gpu_gx_gdsc {

	status = "ok";

};



&mvsc_gdsc {

	status = "ok";

};



&mvs0_gdsc {

	status = "ok";

};



&mvs1_gdsc {

	status = "ok";

};