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Commit 6c9d370c authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus 

Pull MIPS fixes from Ralf Baechle:
 "One build fix for build breakage of all MIPS SMP kernels caused by
  Rusty's fix of obsolete use of cpu mask helpers, another to fix the FP
  ABI selection when loading an ELF binary"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
  MIPS: fix FP mode selection in lieu of .MIPS.abiflags data
  MIPS: SMP: Fix build error.
parents 03906ca3 620b1550

arch/mips/include/asm/smp.h

+1 −1
Original line number Diff line number Diff line
@@ -45,7 +45,7 @@ extern int __cpu_logical_map[NR_CPUS]; 
#define SMP_DUMP		0x8

#define SMP_ASK_C0COUNT		0x10



extern volatile cpumask_t cpu_callin_map;

extern cpumask_t cpu_callin_map;



/* Mask of CPUs which are currently definitely operating coherently */

extern cpumask_t cpu_coherent_mask;

arch/mips/kernel/elf.c

+17 −15
Original line number Diff line number Diff line
@@ -76,14 +76,6 @@ int arch_elf_pt_proc(void *_ehdr, void *_phdr, struct file *elf, 


	/* Lets see if this is an O32 ELF */

	if (ehdr32->e_ident[EI_CLASS] == ELFCLASS32) {

		/* FR = 1 for N32 */

		if (ehdr32->e_flags & EF_MIPS_ABI2)

			state->overall_fp_mode = FP_FR1;

		else

			/* Set a good default FPU mode for O32 */

			state->overall_fp_mode = cpu_has_mips_r6 ?

				FP_FRE : FP_FR0;



		if (ehdr32->e_flags & EF_MIPS_FP64) {

			/*

			 * Set MIPS_ABI_FP_OLD_64 for EF_MIPS_FP64. We will override it
@@ -104,9 +96,6 @@ int arch_elf_pt_proc(void *_ehdr, void *_phdr, struct file *elf, 
				  (char *)&abiflags,

				  sizeof(abiflags));

	} else {

		/* FR=1 is really the only option for 64-bit */

		state->overall_fp_mode = FP_FR1;



		if (phdr64->p_type != PT_MIPS_ABIFLAGS)

			return 0;

		if (phdr64->p_filesz < sizeof(abiflags))
@@ -137,6 +126,7 @@ int arch_check_elf(void *_ehdr, bool has_interpreter, 
	struct elf32_hdr *ehdr = _ehdr;

	struct mode_req prog_req, interp_req;

	int fp_abi, interp_fp_abi, abi0, abi1, max_abi;

	bool is_mips64;



	if (!config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT))

		return 0;
@@ -152,10 +142,22 @@ int arch_check_elf(void *_ehdr, bool has_interpreter, 
		abi0 = abi1 = fp_abi;

	}



	/* ABI limits. O32 = FP_64A, N32/N64 = FP_SOFT */

	max_abi = ((ehdr->e_ident[EI_CLASS] == ELFCLASS32) &&

		   (!(ehdr->e_flags & EF_MIPS_ABI2))) ?

		MIPS_ABI_FP_64A : MIPS_ABI_FP_SOFT;

	is_mips64 = (ehdr->e_ident[EI_CLASS] == ELFCLASS64) ||

		    (ehdr->e_flags & EF_MIPS_ABI2);



	if (is_mips64) {

		/* MIPS64 code always uses FR=1, thus the default is easy */

		state->overall_fp_mode = FP_FR1;



		/* Disallow access to the various FPXX & FP64 ABIs */

		max_abi = MIPS_ABI_FP_SOFT;

	} else {

		/* Default to a mode capable of running code expecting FR=0 */

		state->overall_fp_mode = cpu_has_mips_r6 ? FP_FRE : FP_FR0;



		/* Allow all ABIs we know about */

		max_abi = MIPS_ABI_FP_64A;

	}



	if ((abi0 > max_abi && abi0 != MIPS_ABI_FP_UNKNOWN) ||

	    (abi1 > max_abi && abi1 != MIPS_ABI_FP_UNKNOWN))

arch/mips/kernel/smp.c

+4 −2
Original line number Diff line number Diff line
@@ -43,7 +43,7 @@ 
#include <asm/time.h>

#include <asm/setup.h>



volatile cpumask_t cpu_callin_map;	/* Bitmask of started secondaries */

cpumask_t cpu_callin_map;		/* Bitmask of started secondaries */



int __cpu_number_map[NR_CPUS];		/* Map physical to logical */

EXPORT_SYMBOL(__cpu_number_map);
@@ -218,8 +218,10 @@ int __cpu_up(unsigned int cpu, struct task_struct *tidle) 
	/*

	 * Trust is futile.  We should really have timeouts ...

	 */

	while (!cpumask_test_cpu(cpu, &cpu_callin_map))

	while (!cpumask_test_cpu(cpu, &cpu_callin_map)) {

		udelay(100);

		schedule();

	}



	synchronise_count_master(cpu);

	return 0;