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Commit 6c826f34 authored by Mika Kuoppala's avatar Mika Kuoppala Committed by Daniel Vetter
Browse files

drm/i915: Add fault address to error state for gen8 and gen9 



The faulting virtual address is >32bits and has been moved
to different registers. Add to error state and output upper
register first, in the same line for easy reconstruction of
the fault address.

v2: correct gen masking (Michel)
v3: s/TBL/TLB (Ville)

Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: default avatarMichel Thierry <michel.thierry@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 1d00dad5

drivers/gpu/drm/i915/i915_drv.h

+2 −0
Original line number Diff line number Diff line
@@ -427,6 +427,8 @@ struct drm_i915_error_state { 
	u32 forcewake;

	u32 error; /* gen6+ */

	u32 err_int; /* gen7 */

	u32 fault_data0; /* gen8, gen9 */

	u32 fault_data1; /* gen8, gen9 */

	u32 done_reg;

	u32 gac_eco;

	u32 gam_ecochk;

drivers/gpu/drm/i915/i915_gpu_error.c

+10 −0
Original line number Diff line number Diff line
@@ -386,6 +386,11 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m, 


	if (INTEL_INFO(dev)->gen >= 6) {

		err_printf(m, "ERROR: 0x%08x\n", error->error);



		if (INTEL_INFO(dev)->gen >= 8)

			err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",

				   error->fault_data1, error->fault_data0);



		err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);

	}
@@ -1171,6 +1176,11 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv, 
	if (IS_GEN7(dev))

		error->err_int = I915_READ(GEN7_ERR_INT);



	if (INTEL_INFO(dev)->gen >= 8) {

		error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);

		error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);

	}



	if (IS_GEN6(dev)) {

		error->forcewake = I915_READ(FORCEWAKE);

		error->gab_ctl = I915_READ(GAB_CTL);

drivers/gpu/drm/i915/i915_reg.h

+3 −0
Original line number Diff line number Diff line
@@ -1306,6 +1306,9 @@ enum skl_disp_power_wells { 
#define   ERR_INT_FIFO_UNDERRUN_A	(1<<0)

#define   ERR_INT_FIFO_UNDERRUN(pipe)	(1<<(pipe*3))



#define GEN8_FAULT_TLB_DATA0		0x04b10

#define GEN8_FAULT_TLB_DATA1		0x04b14



#define FPGA_DBG		0x42300

#define   FPGA_DBG_RM_NOCLAIM	(1<<31)