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Commit 6c3af955 authored by Horia Geant?'s avatar Horia Geant? Committed by Herbert Xu
Browse files

crypto: caam - add support for LS1021A 



LS1021A is a QorIQ SoC having little endian CAAM.

There are a few differences b/w QorIQ and i.MX from CAAM perspective:

1. i.MX platforms are somewhat special wrt. 64-bit registers:
-big endian format at 64-bit level: MSW at address+0 and LSW at address+4
-little endian format at 32-bit level (within MSW and LSW)
and thus need special handling.

2. No CCM (clock controller module) for QorIQ.
No CAAM clocks to enable / disable.

A new Kconfig option - CRYPTO_DEV_FSL_CAAM_LE - is added to indicate
CAAM is little endian (*). It is hidden from the user (to avoid
misconfiguration); when adding support for a new platform with LE CAAM,
either the Kconfig needs to be updated or the corresponding defconfig
needs to indicate that CAAM is LE.
(*) Using a DT property to provide CAAM endianness would not allow
for the ifdeffery.

In order to keep changes to a minimum, the following changes
are postponed:
-endianness fix of the last word in the S/G (rsvd2, bpid, offset),
fields are always 0 anyway;
-S/G format fix for i.MX7 (yes, i.MX7 support was not added yet,
but still...)

Signed-off-by: default avatarHoria Geant? <horia.geanta@freescale.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent c1ae632a

drivers/crypto/caam/Kconfig

+8 −0
Original line number Diff line number Diff line
@@ -112,6 +112,14 @@ config CRYPTO_DEV_FSL_CAAM_RNG_API 
	  To compile this as a module, choose M here: the module

	  will be called caamrng.



config CRYPTO_DEV_FSL_CAAM_IMX

	def_bool SOC_IMX6 || SOC_IMX7D

	depends on CRYPTO_DEV_FSL_CAAM



config CRYPTO_DEV_FSL_CAAM_LE

	def_bool CRYPTO_DEV_FSL_CAAM_IMX || SOC_LS1021A

	depends on CRYPTO_DEV_FSL_CAAM



config CRYPTO_DEV_FSL_CAAM_DEBUG

	bool "Enable debug output in CAAM driver"

	depends on CRYPTO_DEV_FSL_CAAM

drivers/crypto/caam/ctrl.c

+2 −2
Original line number Diff line number Diff line
@@ -16,10 +16,10 @@ 
#include "error.h"



/*

 * ARM targets tend to have clock control subsystems that can

 * i.MX targets tend to have clock control subsystems that can

 * enable/disable clocking to our device.

 */

#ifdef CONFIG_ARM

#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_IMX

static inline struct clk *caam_drv_identify_clk(struct device *dev,

						char *clk_name)

{

drivers/crypto/caam/desc.h

+4 −4
Original line number Diff line number Diff line
@@ -23,12 +23,12 @@ 
#define SEC4_SG_OFFS_MASK	0x00001fff



struct sec4_sg_entry {

#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT

	dma_addr_t ptr;

#else

#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_IMX

	u32 rsvd1;

	dma_addr_t ptr;

#endif

#else

	u64 ptr;

#endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_IMX */

	u32 len;

	u8 rsvd2;

	u8 buf_pool_id;

drivers/crypto/caam/regs.h

+15 −4
Original line number Diff line number Diff line
@@ -108,20 +108,31 @@ 


/*

 * The only users of these wr/rd_reg64 functions is the Job Ring (JR).

 * The DMA address registers in the JR are a pair of 32-bit registers.

 * The layout is:

 * The DMA address registers in the JR are handled differently depending on

 * platform:

 *

 * 1. All BE CAAM platforms and i.MX platforms (LE CAAM):

 *

 *    base + 0x0000 : most-significant 32 bits

 *    base + 0x0004 : least-significant 32 bits

 *

 * The 32-bit version of this core therefore has to write to base + 0x0004

 * to set the 32-bit wide DMA address. This seems to be independent of the

 * endianness of the written/read data.

 * to set the 32-bit wide DMA address.

 *

 * 2. All other LE CAAM platforms (LS1021A etc.)

 *    base + 0x0000 : least-significant 32 bits

 *    base + 0x0004 : most-significant 32 bits

 */



#ifndef CONFIG_64BIT

#if !defined(CONFIG_CRYPTO_DEV_FSL_CAAM_LE) || \

	defined(CONFIG_CRYPTO_DEV_FSL_CAAM_IMX)

#define REG64_MS32(reg) ((u32 __iomem *)(reg))

#define REG64_LS32(reg) ((u32 __iomem *)(reg) + 1)

#else

#define REG64_MS32(reg) ((u32 __iomem *)(reg) + 1)

#define REG64_LS32(reg) ((u32 __iomem *)(reg))

#endif



static inline void wr_reg64(u64 __iomem *reg, u64 data)

{