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Commit 6b7b9e78 authored by Aravind Venkateswaran's avatar Aravind Venkateswaran
Browse files

drm/msm/dsi-staging: fix default value for DSI clockout control 



DSI clockout control setting for t-clk-pre and t-clk-post is an
optional parameter for certain chip versions. When these bindings
are not specified, current implementation has default values which
may result in incorrect settings. Fix this by setting the default
value to 0x00.

Change-Id: Iecbc4f2d6311263c7dac4af40f72cf746e48cb86
Signed-off-by: default avatarAravind Venkateswaran <aravindh@codeaurora.org>
parent a7354462

Documentation/devicetree/bindings/drm/msm/mdss-dsi-panel.txt

+2 −2
Original line number Diff line number Diff line
@@ -241,9 +241,9 @@ Optional properties: 
- qcom,mdss-dsi-lane-2-state:		Boolean that specifies whether data lane 2 is enabled.

- qcom,mdss-dsi-lane-3-state:		Boolean that specifies whether data lane 3 is enabled.

- qcom,mdss-dsi-t-clk-post:		Specifies the byte clock cycles after mode switch.

					0x03 = default value.

					0x00 = default value.

- qcom,mdss-dsi-t-clk-pre:		Specifies the byte clock cycles before mode switch.

					0x24 = default value.

					0x00 = default value.

- qcom,mdss-dsi-stream:			Specifies the packet stream to be used.

					0 = stream 0 (default)

					1 = stream 1

drivers/gpu/drm/msm/dsi-staging/dsi_panel.c

+2 −8
Original line number Diff line number Diff line
@@ -984,20 +984,14 @@ static int dsi_panel_parse_misc_host_config(struct dsi_host_common_cfg *host, 
	int rc = 0;



	rc = utils->read_u32(utils->data, "qcom,mdss-dsi-t-clk-post", &val);

	if (rc) {

		pr_debug("[%s] Fallback to default t_clk_post value\n", name);

		host->t_clk_post = 0x03;

	} else {

	if (!rc) {

		host->t_clk_post = val;

		pr_debug("[%s] t_clk_post = %d\n", name, val);

	}



	val = 0;

	rc = utils->read_u32(utils->data, "qcom,mdss-dsi-t-clk-pre", &val);

	if (rc) {

		pr_debug("[%s] Fallback to default t_clk_pre value\n", name);

		host->t_clk_pre = 0x24;

	} else {

	if (!rc) {

		host->t_clk_pre = val;

		pr_debug("[%s] t_clk_pre = %d\n", name, val);

	}