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Commit 6b47a825 authored by Will Deacon's avatar Will Deacon Committed by Greg Kroah-Hartman
Browse files

arm64: entry: Apply BP hardening for high-priority synchronous exceptions 




Commit 5dfc6ed27710 upstream.

Software-step and PC alignment fault exceptions have higher priority than
instruction abort exceptions, so apply the BP hardening hooks there too
if the user PC appears to reside in kernel space.

Reported-by: default avatarDan Hettena <dhettena@nvidia.com>
Reviewed-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarArd Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent aab33067

arch/arm64/kernel/entry.S

+4 −2
Original line number Diff line number Diff line
@@ -759,8 +759,10 @@ el0_sp_pc: 
	 * Stack or PC alignment exception handling

	 */

	mrs	x26, far_el1

	// enable interrupts before calling the main handler

	enable_dbg_and_irq

	enable_dbg

#ifdef CONFIG_TRACE_IRQFLAGS

	bl	trace_hardirqs_off

#endif

	ct_user_exit

	mov	x0, x26

	mov	x1, x25

arch/arm64/mm/fault.c

+9 −0
Original line number Diff line number Diff line
@@ -778,6 +778,12 @@ asmlinkage void __exception do_sp_pc_abort(unsigned long addr, 
	struct siginfo info;

	struct task_struct *tsk = current;



	if (user_mode(regs)) {

		if (instruction_pointer(regs) > TASK_SIZE)

			arm64_apply_bp_hardening();

		local_irq_enable();

	}



	if (show_unhandled_signals && unhandled_signal(tsk, SIGBUS))

		pr_info_ratelimited("%s[%d]: %s exception: pc=%p sp=%p\n",

				    tsk->comm, task_pid_nr(tsk),
@@ -837,6 +843,9 @@ asmlinkage int __exception do_debug_exception(unsigned long addr, 
	if (interrupts_enabled(regs))

		trace_hardirqs_off();



	if (user_mode(regs) && instruction_pointer(regs) > TASK_SIZE)

		arm64_apply_bp_hardening();



	if (!inf->fn(addr, esr, regs)) {

		rv = 1;

	} else {