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Commit 6b301a05 authored by Rhyland Klein's avatar Rhyland Klein Committed by Thierry Reding
Browse files

clk: tegra: Add support for Tegra210 clocks 



Implement clock support for Tegra210.

Signed-off-by: default avatarRhyland Klein <rklein@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 139fd309

drivers/clk/tegra/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -20,3 +20,4 @@ obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124.o 
obj-$(CONFIG_ARCH_TEGRA_124_SOC)	+= clk-tegra124-dfll-fcpu.o

obj-$(CONFIG_ARCH_TEGRA_132_SOC)	+= clk-tegra124.o

obj-y					+= cvb.o

obj-$(CONFIG_ARCH_TEGRA_210_SOC)	+= clk-tegra210.o

drivers/clk/tegra/clk-id.h

+7 −0
Original line number Diff line number Diff line
@@ -152,6 +152,10 @@ enum clk_id { 
	tegra_clk_pll_c2,

	tegra_clk_pll_c3,

	tegra_clk_pll_c4,

	tegra_clk_pll_c4_out0,

	tegra_clk_pll_c4_out1,

	tegra_clk_pll_c4_out2,

	tegra_clk_pll_c4_out3,

	tegra_clk_pll_c_out1,

	tegra_clk_pll_d,

	tegra_clk_pll_d2,
@@ -179,6 +183,9 @@ enum clk_id { 
	tegra_clk_pll_re_out,

	tegra_clk_pll_re_vco,

	tegra_clk_pll_u,

	tegra_clk_pll_u_out,

	tegra_clk_pll_u_out1,

	tegra_clk_pll_u_out2,

	tegra_clk_pll_u_12m,

	tegra_clk_pll_u_480m,

	tegra_clk_pll_u_48m,

drivers/clk/tegra/clk-pll.c

+5 −0
Original line number Diff line number Diff line
@@ -414,6 +414,11 @@ static int _p_div_to_hw(struct clk_hw *hw, u8 p_div) 
	return -EINVAL;

}



int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div)

{

	return _p_div_to_hw(&pll->hw, p_div);

}



static int _hw_to_p_div(struct clk_hw *hw, u8 p_div_hw)

{

	struct tegra_clk_pll *pll = to_clk_pll(hw);

drivers/clk/tegra/clk-tegra210.c

0 → 100644
+2852 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/clk/tegra/clk.h

+3 −0
Original line number Diff line number Diff line
@@ -242,6 +242,7 @@ struct tegra_clk_pll; 
 *     it may be more accurate (especially if SDM present)

 * TEGRA_PLLMB - PLLMB has should be treated similar to PLLM. This

 *     flag indicated that it is PLLMB.

 * TEGRA_PLL_VCO_OUT - Used to indicate that the PLL has a VCO output

 */

struct tegra_clk_pll_params {

	unsigned long	input_min;
@@ -307,6 +308,7 @@ struct tegra_clk_pll_params { 
#define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10)

#define TEGRA_MDIV_NEW BIT(11)

#define TEGRA_PLLMB BIT(12)

#define TEGRA_PLL_VCO_OUT BIT(13)



/**

 * struct tegra_clk_pll - Tegra PLL clock
@@ -766,5 +768,6 @@ typedef void (*tegra_clk_apply_init_table_func)(void); 
extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table;

int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll);

u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate);

int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div);



#endif /* TEGRA_CLK_H */