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Commit 6ae66982 authored by Nicolin Chen's avatar Nicolin Chen Committed by Mark Brown
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ASoC: fsl_spdif: Fix wrong OFFSET of STC_SYSCLK_DIV 



It should use STC_SYSCLK_DIV_OFFSET. Thus fix it.

Signed-off-by: default avatarNicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: default avatarMark Brown <broonie@linaro.org>
parent c9eaa447

sound/soc/fsl/fsl_spdif.h

+2 −2
Original line number Diff line number Diff line
@@ -144,8 +144,8 @@ enum spdif_gainsel { 


/* SPDIF Clock register */

#define STC_SYSCLK_DIV_OFFSET		11

#define STC_SYSCLK_DIV_MASK		(0x1ff << STC_TXCLK_SRC_OFFSET)

#define STC_SYSCLK_DIV(x)		((((x) - 1) << STC_TXCLK_DIV_OFFSET) & STC_SYSCLK_DIV_MASK)

#define STC_SYSCLK_DIV_MASK		(0x1ff << STC_SYSCLK_DIV_OFFSET)

#define STC_SYSCLK_DIV(x)		((((x) - 1) << STC_SYSCLK_DIV_OFFSET) & STC_SYSCLK_DIV_MASK)

#define STC_TXCLK_SRC_OFFSET		8

#define STC_TXCLK_SRC_MASK		(0x7 << STC_TXCLK_SRC_OFFSET)

#define STC_TXCLK_SRC_SET(x)		((x << STC_TXCLK_SRC_OFFSET) & STC_TXCLK_SRC_MASK)