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Commit 6aa4cf1c authored by Michal Kazior's avatar Michal Kazior Committed by Kalle Valo
Browse files

ath10k: add hw rate definitions 



Prepare defines for future use.

Signed-off-by: default avatarMichal Kazior <michal.kazior@tieto.com>
Signed-off-by: default avatarKalle Valo <kvalo@qca.qualcomm.com>
parent 5653b39d

drivers/net/wireless/ath/ath10k/htt.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -25,6 +25,7 @@ 
#include <net/mac80211.h>

#include <net/mac80211.h>





#include "htc.h"

#include "htc.h"

#include "hw.h"

#include "rx_desc.h"

#include "rx_desc.h"

#include "hw.h"

#include "hw.h"

drivers/net/wireless/ath/ath10k/hw.h

+21 −0
Original line number Original line Diff line number Diff line
@@ -202,6 +202,27 @@ struct ath10k_pktlog_hdr { 
	u8 payload[0];

	u8 payload[0];

} __packed;

} __packed;





enum ath10k_hw_rate_ofdm {

	ATH10K_HW_RATE_OFDM_48M = 0,

	ATH10K_HW_RATE_OFDM_24M,

	ATH10K_HW_RATE_OFDM_12M,

	ATH10K_HW_RATE_OFDM_6M,

	ATH10K_HW_RATE_OFDM_54M,

	ATH10K_HW_RATE_OFDM_36M,

	ATH10K_HW_RATE_OFDM_18M,

	ATH10K_HW_RATE_OFDM_9M,

};



enum ath10k_hw_rate_cck {

	ATH10K_HW_RATE_CCK_LP_11M = 0,

	ATH10K_HW_RATE_CCK_LP_5_5M,

	ATH10K_HW_RATE_CCK_LP_2M,

	ATH10K_HW_RATE_CCK_LP_1M,

	ATH10K_HW_RATE_CCK_SP_11M,

	ATH10K_HW_RATE_CCK_SP_5_5M,

	ATH10K_HW_RATE_CCK_SP_2M,

};



/* Target specific defines for MAIN firmware */

/* Target specific defines for MAIN firmware */

#define TARGET_NUM_VDEVS			8

#define TARGET_NUM_VDEVS			8

#define TARGET_NUM_PEER_AST			2

#define TARGET_NUM_PEER_AST			2

drivers/net/wireless/ath/ath10k/rx_desc.h

+22 −0
Original line number Original line Diff line number Diff line
@@ -661,6 +661,28 @@ struct rx_msdu_end { 
#define RX_PPDU_START_INFO5_SERVICE_MASK 0x0000ffff

#define RX_PPDU_START_INFO5_SERVICE_MASK 0x0000ffff

#define RX_PPDU_START_INFO5_SERVICE_LSB  0

#define RX_PPDU_START_INFO5_SERVICE_LSB  0





/* No idea what this flag means. It seems to be always set in rate. */

#define RX_PPDU_START_RATE_FLAG BIT(3)



enum rx_ppdu_start_rate {

	RX_PPDU_START_RATE_OFDM_48M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_OFDM_48M,

	RX_PPDU_START_RATE_OFDM_24M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_OFDM_24M,

	RX_PPDU_START_RATE_OFDM_12M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_OFDM_12M,

	RX_PPDU_START_RATE_OFDM_6M  = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_OFDM_6M,

	RX_PPDU_START_RATE_OFDM_54M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_OFDM_54M,

	RX_PPDU_START_RATE_OFDM_36M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_OFDM_36M,

	RX_PPDU_START_RATE_OFDM_18M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_OFDM_18M,

	RX_PPDU_START_RATE_OFDM_9M  = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_OFDM_9M,



	RX_PPDU_START_RATE_CCK_LP_11M  = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_CCK_LP_11M,

	RX_PPDU_START_RATE_CCK_LP_5_5M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_CCK_LP_5_5M,

	RX_PPDU_START_RATE_CCK_LP_2M   = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_CCK_LP_2M,

	RX_PPDU_START_RATE_CCK_LP_1M   = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_CCK_LP_1M,

	RX_PPDU_START_RATE_CCK_SP_11M  = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_CCK_SP_11M,

	RX_PPDU_START_RATE_CCK_SP_5_5M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_CCK_SP_5_5M,

	RX_PPDU_START_RATE_CCK_SP_2M   = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_CCK_SP_2M,

};



struct rx_ppdu_start {

struct rx_ppdu_start {

	struct {

	struct {

		u8 pri20_mhz;

		u8 pri20_mhz;