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Commit 6a8daaaf authored by Santosh Mardi's avatar Santosh Mardi
Browse files

ARM: dts: msm: update DDR IB value for qcs405 and qcs403 target 



update DDR IB value with proper width value for all the frequency
on qcs405 and qcs403 target.

Change-Id: Ibadced248850396bb95d7af2bbed980130812847
Signed-off-by: default avatarSantosh Mardi <gsantosh@codeaurora.org>
parent 5832f3db

arch/arm64/boot/dts/qcom/qcs403.dtsi

+3 −3
Original line number Diff line number Diff line
@@ -40,8 +40,8 @@ 
		qcom,cpulist = <&CPU0 &CPU1>;

		qcom,target-dev = <&cpu0_cpu_ddr_latfloor>;

		qcom,core-dev-table =

			< 1094400 MHZ_TO_MBPS( 297, 4) >,

			< 1248000 MHZ_TO_MBPS( 597, 4) >,

			< 1401600 MHZ_TO_MBPS( 710, 4) >;

			< 1094400 MHZ_TO_MBPS( 297, 8) >,

			< 1248000 MHZ_TO_MBPS( 597, 8) >,

			< 1401600 MHZ_TO_MBPS( 710, 8) >;

	};

};

arch/arm64/boot/dts/qcom/qcs405.dtsi

+5 −5
Original line number Diff line number Diff line
@@ -1265,9 +1265,9 @@ 


	ddr_bw_opp_table: ddr-bw-opp-table {

		compatible = "operating-points-v2";

		BW_OPP_ENTRY( 297, 4); /* 1132 MB/s */

		BW_OPP_ENTRY( 595, 4); /* 2269 MB/s */

		BW_OPP_ENTRY( 710, 4); /* 2708 MB/s */

		BW_OPP_ENTRY( 297, 8); /* 2265 MB/s */

		BW_OPP_ENTRY( 595, 8); /* 4539 MB/s */

		BW_OPP_ENTRY( 710, 8); /* 5416 MB/s */

	};



	cpubw: qcom,cpubw {
@@ -1300,8 +1300,8 @@ 
		qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;

		qcom,target-dev = <&cpu0_cpu_ddr_latfloor>;

		qcom,core-dev-table =

			< 1094400 MHZ_TO_MBPS( 297, 4) >,

			< 1248000 MHZ_TO_MBPS( 597, 4) >;

			< 1094400 MHZ_TO_MBPS( 297, 8) >,

			< 1248000 MHZ_TO_MBPS( 597, 8) >;

	};



	emac_hw: qcom,emac@07A80000 {