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Commit 6a6781de authored by Jilai Wang's avatar Jilai Wang
Browse files

ARM: dts: msm: Add NPU support for sdmmagpie 



This change is to add NPU configuration and PIL node for
sdmmagpie.

Change-Id: I6282f5fd8b54d848a27fc4364295e357bbbd8607
Signed-off-by: default avatarJilai Wang <jilaiw@codeaurora.org>
parent bead6b39

arch/arm64/boot/dts/qcom/sdmmagpie-npu.dtsi

0 → 100644
+182 −0
Original line number Diff line number Diff line 
/* Copyright (c) 2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

 * GNU General Public License for more details.

 */



&soc {

	msm_npu: qcom,msm_npu@9800000 {

		compatible = "qcom,msm-npu";

		reg = <0x9800000 0x800000>;

		reg-names = "npu_base";

		interrupts = <GIC_SPI 583 IRQ_TYPE_EDGE_RISING>,

				<GIC_SPI 585 IRQ_TYPE_EDGE_RISING>,

				<GIC_SPI 587 IRQ_TYPE_EDGE_RISING>;

		interrupt-names = "error_irq", "wdg_bite_irq", "ipc_irq";

		iommus = <&apps_smmu 0x1461 0x0>;

		cache-slice-names = "npu";

		cache-slices = <&llcc 23>;



		clocks = <&clock_npucc NPU_CC_CAL_DP_CLK>,

			<&clock_npucc NPU_CC_XO_CLK>,

			<&clock_npucc NPU_CC_ARMWIC_CORE_CLK>,

			<&clock_npucc NPU_CC_BTO_CORE_CLK>,

			<&clock_npucc NPU_CC_BWMON_CLK>,

			<&clock_npucc NPU_CC_CAL_DP_CDC_CLK>,

			<&clock_npucc NPU_CC_COMP_NOC_AXI_CLK>,

			<&clock_npucc NPU_CC_CONF_NOC_AHB_CLK>,

			<&clock_npucc NPU_CC_NPU_CORE_APB_CLK>,

			<&clock_npucc NPU_CC_NPU_CORE_ATB_CLK>,

			<&clock_npucc NPU_CC_NPU_CORE_CLK>,

			<&clock_npucc NPU_CC_NPU_CORE_CTI_CLK>,

			<&clock_npucc NPU_CC_NPU_CPC_CLK>,

			<&clock_npucc NPU_CC_NPU_CPC_TIMER_CLK>,

			<&clock_npucc NPU_CC_PERF_CNT_CLK>,

			<&clock_npucc NPU_CC_QTIMER_CORE_CLK>,

			<&clock_npucc NPU_CC_SLEEP_CLK>,

			<&clock_aop QDSS_CLK>;

		clock-names = "cal_dp_clk",

			"xo_clk",

			"armwic_core_clk",

			"bto_core_clk",

			"bwmon_clk",

			"cal_dp_cdc_clk",

			"comp_noc_axi_clk",

			"conf_noc_ahb_clk",

			"npu_core_apb_clk",

			"npu_core_atb_clk",

			"npu_core_clk",

			"npu_core_cti_clk",

			"npu_cpc_clk",

			"npu_cpc_timer_clk",

			"perf_cnt_clk",

			"qtimer_core_clk",

			"sleep_clk",

			"qdss_clk";

		vdd-supply = <&npu_core_gdsc>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		qcom,proxy-reg-names ="vdd", "vdd_cx";

		qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;

		mboxes = <&qmp_npu0 0>, <&qmp_npu1 0>;

		mbox-names = "npu_low", "npu_high";



		#cooling-cells = <2>;

		qcom,npu-pwrlevels {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "qcom,npu-pwrlevels";

			initial-pwrlevel = <4>;

			qcom,npu-pwrlevel@0 {

				reg = <0>;

				clk-freq = <300000000

					19200000

					100000000

					19200000

					19200000

					300000000

					150000000

					30000000

					19200000

					60000000

					100000000

					37500000

					100000000

					19200000

					300000000

					19200000

					0

					0>;

			};

			qcom,npu-pwrlevel@1 {

				reg = <1>;

				clk-freq = <400000000

					19200000

					150000000

					19200000

					19200000

					400000000

					200000000

					37500000

					19200000

					120000000

					150000000

					75000000

					150000000

					19200000

					400000000

					19200000

					0

					0>;

			};

			qcom,npu-pwrlevel@2 {

				reg = <2>;

				clk-freq = <466500000

					19200000

					200000000

					19200000

					19200000

					466500000

					300000000

					37500000

					19200000

					120000000

					200000000

					75000000

					200000000

					19200000

					466500000

					19200000

					0

					0>;

			};

			qcom,npu-pwrlevel@3 {

				reg = <3>;

				clk-freq = <600000000

					19200000

					300000000

					19200000

					19200000

					600000000

					403000000

					75000000

					19200000

					240000000

					300000000

					150000000

					300000000

					19200000

					600000000

					19200000

					0

					0>;

			};

			qcom,npu-pwrlevel@4 {

				reg = <4>;

				clk-freq = <700000000

					19200000

					400000000

					19200000

					19200000

					700000000

					533000000

					75000000

					19200000

					300000000

					400000000

					150000000

					400000000

					19200000

					700000000

					19200000

					0

					0>;

			};

		};

	};

};

arch/arm64/boot/dts/qcom/sdmmagpie.dtsi

+12 −0
Original line number Diff line number Diff line
@@ -2152,6 +2152,16 @@ 
		qcom,firmware-name = "venus";

		memory-region = <&pil_video_mem>;

	};



	qcom,npu@0x9800000 {

		compatible = "qcom,pil-tz-generic";

		reg = <0x9800000 0x800000>;



		status = "ok";

		qcom,pas-id = <23>;

		qcom,firmware-name = "npu";

		memory-region = <&npu_mem>;

	};

};



#include "sdmmagpie-pinctrl.dtsi"
@@ -2401,3 +2411,5 @@ 
		qcom,hw-settle-time = <200>;

	};

};



#include "sdmmagpie-npu.dtsi"