Commit 69e4e63e authored Feb 18, 2015 by Manuel Lauss Committed by Ralf Baechle Feb 20, 2015

MIPS: Alchemy: Fix cpu clock calculation



The current code uses bits 0-6 of the sys_cpupll register to calculate
core clock speed.  However this is only valid on Au1300, on all earlier
models the hardware only uses bits 0-5 to generate core clock.

This fixes clock calculation on the MTX1 (Au1500), where bit 6 of cpupll
is set as well, which ultimately lead the code to calculate a bogus cpu
core clock and also uart base clock down the line.

Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Reported-by: John Crispin <blogic@openwrt.org>
Tested-by: Bruno Randolf <br1@einfach.org>
Cc: stable@vger.kernel.org	[v3.17+]
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/9279/


Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

parent 200276e6

arch/mips/alchemy/common/clock.c

+2 −0

Original line number	Diff line number	Diff line
		@@ -127,6 +127,8 @@ static unsigned long alchemy_clk_cpu_recalc(struct clk_hw *hw,
		t = 396000000;
		else {
		t = alchemy_rdsys(AU1000_SYS_CPUPLL) & 0x7f;
		if (alchemy_get_cputype() < ALCHEMY_CPU_AU1300)
		t &= 0x3f;
		t *= parent_rate;
		}