Loading arch/arm64/boot/dts/qcom/sm8150-gpu.dtsi +0 −22 Original line number Diff line number Diff line Loading @@ -289,20 +289,6 @@ }; }; gmu_opp_table: gmu-opp-table { compatible = "operating-points-v2"; opp-200000000 { opp-hz = /bits/ 64 <200000000>; opp-microvolt = <RPMH_REGULATOR_LEVEL_LOW_SVS>; }; opp-500000000 { opp-hz = /bits/ 64 <500000000>; opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS>; }; }; gmu: qcom,gmu@0x2C6A000 { label = "kgsl-gmu"; compatible = "qcom,gpu-gmu"; Loading @@ -324,9 +310,6 @@ vddcx-supply = <&gpu_cx_gdsc>; vdd-supply = <&gpu_gx_gdsc>; /* GMU OPP data */ operating-points-v2 = <&gmu_opp_table>; clocks = <&clock_gpucc GPU_CC_CX_GMU_CLK>, <&clock_gpucc GPU_CC_CXO_CLK>, <&clock_gcc GCC_DDRSS_GPU_AXI_CLK>, Loading @@ -352,11 +335,6 @@ reg = <1>; qcom,gmu-freq = <200000000>; }; qcom,gmu-pwrlevel@2 { reg = <2>; qcom,gmu-freq = <500000000>; }; }; gmu_user: gmu_user { Loading Loading
arch/arm64/boot/dts/qcom/sm8150-gpu.dtsi +0 −22 Original line number Diff line number Diff line Loading @@ -289,20 +289,6 @@ }; }; gmu_opp_table: gmu-opp-table { compatible = "operating-points-v2"; opp-200000000 { opp-hz = /bits/ 64 <200000000>; opp-microvolt = <RPMH_REGULATOR_LEVEL_LOW_SVS>; }; opp-500000000 { opp-hz = /bits/ 64 <500000000>; opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS>; }; }; gmu: qcom,gmu@0x2C6A000 { label = "kgsl-gmu"; compatible = "qcom,gpu-gmu"; Loading @@ -324,9 +310,6 @@ vddcx-supply = <&gpu_cx_gdsc>; vdd-supply = <&gpu_gx_gdsc>; /* GMU OPP data */ operating-points-v2 = <&gmu_opp_table>; clocks = <&clock_gpucc GPU_CC_CX_GMU_CLK>, <&clock_gpucc GPU_CC_CXO_CLK>, <&clock_gcc GCC_DDRSS_GPU_AXI_CLK>, Loading @@ -352,11 +335,6 @@ reg = <1>; qcom,gmu-freq = <200000000>; }; qcom,gmu-pwrlevel@2 { reg = <2>; qcom,gmu-freq = <500000000>; }; }; gmu_user: gmu_user { Loading