Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 6958f22f authored by Chanwoo Choi's avatar Chanwoo Choi Committed by Sylwester Nawrocki
Browse files

clk: samsung: exynos5433: Add clocks for CMU_CAM0 domain 



This patch adds the mux/divider/gate clocks for CMU_CAM0 domain which
generates the clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs.

Signed-off-by: default avatarChanwoo Choi <cw00.choi@samsung.com>
Acked-by: default avatarInki Dae <inki.dae@samsung.com>
Signed-off-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
parent 8e46c4b8

Documentation/devicetree/bindings/clock/exynos5433-clock.txt

+24 −0
Original line number Original line Diff line number Diff line
@@ -45,6 +45,9 @@ Required Properties: 
    which generates clocks for HEVC(High Efficiency Video Codec) decoder IP.

    which generates clocks for HEVC(High Efficiency Video Codec) decoder IP.

  - "samsung,exynos5433-cmu-isp" - clock controller compatible for CMU_ISP

  - "samsung,exynos5433-cmu-isp" - clock controller compatible for CMU_ISP

    which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs.

    which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs.

  - "samsung,exynos5433-cmu-cam0" - clock controller compatible for CMU_CAM0

    which generates clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1}

    IPs.





- reg: physical base address of the controller and length of memory mapped

- reg: physical base address of the controller and length of memory mapped

  region.

  region.
@@ -144,6 +147,12 @@ Required Properties: 
		- aclk_isp_dis_400

		- aclk_isp_dis_400

		- aclk_isp_400

		- aclk_isp_400





	Input clocks for cam0 clock controller:

		- oscclk

		- aclk_cam0_333

		- aclk_cam0_400

		- aclk_cam0_552



Each clock is assigned an identifier and client nodes can use this identifier

Each clock is assigned an identifier and client nodes can use this identifier

to specify the clock which they consume.

to specify the clock which they consume.
@@ -390,6 +399,21 @@ Example 2: Examples of clock controller nodes are listed below. 
		       <&cmu_top CLK_ACLK_ISP_400>;

		       <&cmu_top CLK_ACLK_ISP_400>;

	};

	};





	cmu_cam0: clock-controller@120d0000 {

		compatible = "samsung,exynos5433-cmu-cam0";

		reg = <0x120d0000 0x0b0c>;

		#clock-cells = <1>;



		clock-names = "oscclk",

			"aclk_cam0_333",

			"aclk_cam0_400",

			"aclk_cam0_552";

		clocks = <&xxti>,

		       <&cmu_top CLK_ACLK_CAM0_333>,

		       <&cmu_top CLK_ACLK_CAM0_400>,

		       <&cmu_top CLK_ACLK_CAM0_552>;

	};



Example 3: UART controller node that consumes the clock generated by the clock

Example 3: UART controller node that consumes the clock generated by the clock

	   controller.

	   controller.

drivers/clk/samsung/clk-exynos5433.c

+501 −0

File changed.

Preview size limit exceeded, changes collapsed.

include/dt-bindings/clock/exynos5433.h

+145 −1

File changed.

Preview size limit exceeded, changes collapsed.