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Commit 6929715c authored by Rhyland Klein's avatar Rhyland Klein Committed by Thierry Reding
Browse files

clk: tegra: pll: Add support for PLLMB for Tegra210 



Tegra210 SoC's have 2 PLLs for memory usage. Add plumbing to register
and handle PLLMB.

PLLMB is used to allow switching between 2 PLLM's without having to use
and intermediate backup PLL, as we need to lock the PLL before we can
switch to it.

Reviewed-by: default avatarBenson Leung <bleung@chromium.org>
Signed-off-by: default avatarRhyland Klein <rklein@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent dd322f04

drivers/clk/tegra/clk-pll.c

+43 −5
Original line number Diff line number Diff line
@@ -571,7 +571,7 @@ static void _update_pll_mnp(struct tegra_clk_pll *pll, 
	struct tegra_clk_pll_params *params = pll->params;

	struct div_nmp *div_nmp = params->div_nmp;



	if ((params->flags & TEGRA_PLLM) &&

	if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&

		(pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &

			PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {

		val = pll_override_readl(params->pmc_divp_reg, pll);
@@ -608,7 +608,7 @@ static void _get_pll_mnp(struct tegra_clk_pll *pll, 
	struct tegra_clk_pll_params *params = pll->params;

	struct div_nmp *div_nmp = params->div_nmp;



	if ((params->flags & TEGRA_PLLM) &&

	if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&

		(pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &

			PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {

		val = pll_override_readl(params->pmc_divp_reg, pll);
@@ -729,8 +729,8 @@ static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, 
	struct tegra_clk_pll_freq_table cfg;



	if (pll->params->flags & TEGRA_PLL_FIXED) {

		/* PLLM are used for memory; we do not change rate */

		if (pll->params->flags & TEGRA_PLLM)

		/* PLLM/MB are used for memory; we do not change rate */

		if (pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB))

			return clk_hw_get_rate(hw);

		return pll->params->fixed_rate;

	}
@@ -757,7 +757,7 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, 
		return parent_rate;



	if ((pll->params->flags & TEGRA_PLL_FIXED) &&

	    !(pll->params->flags & TEGRA_PLLM) &&

	    !(pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&

			!(val & PLL_BASE_OVERRIDE)) {

		struct tegra_clk_pll_freq_table sel;

		if (_get_table_rate(hw, &sel, pll->params->fixed_rate,
@@ -2244,4 +2244,42 @@ struct clk *tegra_clk_register_pllss_tegra210(const char *name, 


	return clk;

}



struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name,

			  void __iomem *clk_base, void __iomem *pmc,

			  unsigned long flags,

			  struct tegra_clk_pll_params *pll_params,

			  spinlock_t *lock)

{

	struct tegra_clk_pll *pll;

	struct clk *clk, *parent;

	unsigned long parent_rate;



	if (!pll_params->pdiv_tohw)

		return ERR_PTR(-EINVAL);



	parent = __clk_lookup(parent_name);

	if (!parent) {

		WARN(1, "parent clk %s of %s must be registered first\n",

			parent_name, name);

		return ERR_PTR(-EINVAL);

	}



	parent_rate = clk_get_rate(parent);



	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);



	pll_params->flags |= TEGRA_PLL_BYPASS;

	pll_params->flags |= TEGRA_PLLMB;

	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);

	if (IS_ERR(pll))

		return ERR_CAST(pll);



	clk = _tegra_clk_register_pll(pll, name, parent_name, flags,

				      &tegra_clk_pll_ops);

	if (IS_ERR(clk))

		kfree(pll);



	return clk;

}

#endif

drivers/clk/tegra/clk.h

+9 −0
Original line number Diff line number Diff line
@@ -225,6 +225,8 @@ struct div_nmp { 
 * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring

 * TEGRA_MDIV_NEW - Switch to new method for calculating fixed mdiv

 *     it may be more accurate (especially if SDM present)

 * TEGRA_PLLMB - PLLMB has should be treated similar to PLLM. This

 *     flag indicated that it is PLLMB.

 */

struct tegra_clk_pll_params {

	unsigned long	input_min;
@@ -281,6 +283,7 @@ struct tegra_clk_pll_params { 
#define TEGRA_PLL_BYPASS BIT(9)

#define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10)

#define TEGRA_MDIV_NEW BIT(11)

#define TEGRA_PLLMB BIT(12)



/**

 * struct tegra_clk_pll - Tegra PLL clock
@@ -387,6 +390,12 @@ struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name, 
			   struct tegra_clk_pll_params *pll_params,

			   spinlock_t *lock);



struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name,

			   void __iomem *clk_base, void __iomem *pmc,

			   unsigned long flags,

			   struct tegra_clk_pll_params *pll_params,

			   spinlock_t *lock);



/**

 * struct tegra_clk_pll_out - PLL divider down clock

 *