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Commit 68ffeca4 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'linux_next' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-edac 

Pull EDAC updates from Mauro Carvalho Chehab.

* 'linux_next' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-edac:
  sb_edac: add support for Haswell based systems
  sb_edac: Fix mix tab/spaces alignments
  edac: add DDR4 and RDDR4
  sb_edac: remove bogus assumption on mc ordering
  sb_edac: make minimal use of channel_mask
  sb_edac: fix socket detection on Ivy Bridge controllers
  sb_edac: update Kconfig description
  sb_edac: search devices using product id
  sb_edac: make RIR limit retrieval per model
  sb_edac: make node id retrieval per model
  sb_edac: make memory type detection per memory controller
parents c9d26423 50d1bb93

drivers/edac/Kconfig

+2 −2
Original line number Original line Diff line number Diff line
@@ -253,12 +253,12 @@ config EDAC_I7300 
	  Clarksboro MCH (Intel 7300 chipset).

	  Clarksboro MCH (Intel 7300 chipset).





config EDAC_SBRIDGE

config EDAC_SBRIDGE

	tristate "Intel Sandy-Bridge Integrated MC"

	tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"

	depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL

	depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL

	depends on PCI_MMCONFIG

	depends on PCI_MMCONFIG

	help

	help

	  Support for error detection and correction the Intel

	  Support for error detection and correction the Intel

	  Sandy Bridge Integrated Memory Controller.

	  Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.





config EDAC_MPC85XX

config EDAC_MPC85XX

	tristate "Freescale MPC83xx / MPC85xx"

	tristate "Freescale MPC83xx / MPC85xx"

drivers/edac/edac_mc_sysfs.c

+3 −1
Original line number Original line Diff line number Diff line
@@ -108,7 +108,9 @@ static const char * const mem_types[] = { 
	[MEM_RDDR2] = "Registered-DDR2",

	[MEM_RDDR2] = "Registered-DDR2",

	[MEM_XDR] = "XDR",

	[MEM_XDR] = "XDR",

	[MEM_DDR3] = "Unbuffered-DDR3",

	[MEM_DDR3] = "Unbuffered-DDR3",

	[MEM_RDDR3] = "Registered-DDR3"

	[MEM_RDDR3] = "Registered-DDR3",

	[MEM_DDR4] = "Unbuffered-DDR4",

	[MEM_RDDR4] = "Registered-DDR4"

};

};





static const char * const dev_types[] = {

static const char * const dev_types[] = {