Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 68f37d86 authored by Chen-Yu Tsai's avatar Chen-Yu Tsai Committed by Maxime Ripard
Browse files

clk: sunxi-ng: a33: Add offset and minimum value for DDR1 PLL N factor 



The DDR1 PLL on the A33 is an oddball amongst the A33 CCU clocks.
It is a clock multiplier, with the effective multiplier in the
range of 12 ~ 255 and no offset between the multiplier value and
the value programmed into the register.

Implement the zero offset and minimum value of 12 for this clock.

Fixes: d05c748b ("clk: sunxi-ng: Add A33 CCU support")
Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent 25eb035c

drivers/clk/sunxi-ng/ccu-sun8i-a33.c

+11 −7
Original line number Diff line number Diff line
@@ -159,13 +159,17 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de", 
					BIT(28),	/* lock */

					CLK_SET_RATE_UNGATE);



/* TODO: Fix N */

static SUNXI_CCU_N_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",

				  "osc24M", 0x04c,

				  8, 6,			/* N */

				  BIT(31),		/* gate */

				  BIT(28),		/* lock */

				  CLK_SET_RATE_UNGATE);

static struct ccu_mult pll_ddr1_clk = {

	.enable	= BIT(31),

	.lock	= BIT(28),

	.mult	= _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 6, 0, 12, 0),

	.common	= {

		.reg		= 0x04c,

		.hw.init	= CLK_HW_INIT("pll-ddr1", "osc24M",

					      &ccu_mult_ops,

					      CLK_SET_RATE_UNGATE),

	},

};



static const char * const cpux_parents[] = { "osc32k", "osc24M",

					     "pll-cpux" , "pll-cpux" };