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Commit 67d1d415 authored by Deepak Katragadda's avatar Deepak Katragadda
Browse files

ARM: dts: msm: Update properties for the GPU GDSCs on SDM855 



Add the clock-disable-wait value for the gpu_cx GDSC based on
the HW recommendation. Also add the support to force-enable the
graphics GX RCG prior to enabling or disabling the GX GDSC.

Change-Id: I435983ed800cbf90feb44d9e8114eed1a5fce934
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent be60ad58

arch/arm64/boot/dts/qcom/sdm855-gdsc.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -208,6 +208,7 @@ 
		hw-ctrl-addr = <&gpu_cx_hw_ctrl>;

		qcom,no-status-check-on-disable;

		qcom,gds-timeout = <500>;

		qcom,clk-dis-wait-val = <8>;

		status = "disabled";

	};
@@ -228,7 +229,6 @@ 
		domain-addr = <&gpu_gx_domain_addr>;

		sw-reset = <&gpu_gx_sw_reset>;

		qcom,reset-aon-logic;

		qcom,toggle-sw-collapse-in-disable;

		status = "disabled";

	};

arch/arm64/boot/dts/qcom/sdm855.dtsi

+3 −0
Original line number Diff line number Diff line
@@ -2083,6 +2083,9 @@ 
&gpu_gx_gdsc {

	parent-supply = <&pm855l_s2_level>;

	qcom,vote-parent-supply-voltage;

	clock-names = "core_root_clk";

	clocks = <&clock_gpucc GPU_CC_GX_GFX3D_CLK_SRC>;

	qcom,force-enable-root-clk;

	status = "ok";

};

include/dt-bindings/clock/qcom,gpucc-sdm855.h

+1 −0
Original line number Diff line number Diff line
@@ -40,6 +40,7 @@ 
#define GPU_CC_RBCPR_CLK					23

#define GPU_CC_RBCPR_CLK_SRC					24

#define GPU_CC_SLEEP_CLK					25

#define GPU_CC_GX_GFX3D_CLK_SRC					26



#define GPUCC_GPU_CC_ACD_BCR					0

#define GPUCC_GPU_CC_CX_BCR					1