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Commit 67cfbfdf authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/gf100-/gr: unhardcode attribute cb config 



Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent b81146b0

drivers/gpu/drm/nouveau/core/engine/graph/ctxgk110b.c

+6 −1
Original line number Diff line number Diff line
@@ -82,7 +82,7 @@ gk110b_grctx_oclass = &(struct nvc0_grctx_oclass) { 
		.wr32 = _nouveau_graph_context_wr32,

	},

	.main  = nve4_grctx_generate_main,

	.mods  = nvf0_grctx_generate_mods,

	.mods  = nve4_grctx_generate_mods,

	.unkn  = nve4_grctx_generate_unkn,

	.hub   = nvf0_grctx_pack_hub,

	.gpc   = nvf0_grctx_pack_gpc,
@@ -97,4 +97,9 @@ gk110b_grctx_oclass = &(struct nvc0_grctx_oclass) { 
	.bundle_token_limit = 0x600,

	.pagepool = nve4_grctx_generate_pagepool,

	.pagepool_size = 0x8000,

	.attrib = nvd7_grctx_generate_attrib,

	.attrib_nr_max = 0x324,

	.attrib_nr = 0x218,

	.alpha_nr_max = 0x7ff,

	.alpha_nr = 0x648,

}.base;

drivers/gpu/drm/nouveau/core/engine/graph/ctxgk20a.c

+5 −0
Original line number Diff line number Diff line
@@ -56,4 +56,9 @@ gk20a_grctx_oclass = &(struct nvc0_grctx_oclass) { 
	.bundle_token_limit = 0x100,

	.pagepool = nve4_grctx_generate_pagepool,

	.pagepool_size = 0x8000,

	.attrib = nvd7_grctx_generate_attrib,

	.attrib_nr_max = 0x240,

	.attrib_nr = 0x240,

	.alpha_nr_max = 0x648 + (0x648 / 2),

	.alpha_nr = 0x648,

}.base;

drivers/gpu/drm/nouveau/core/engine/graph/ctxgm107.c

+45 −21
Original line number Diff line number Diff line
@@ -891,29 +891,47 @@ gm107_grctx_generate_pagepool(struct nvc0_grctx *info) 
}



static void

gm107_grctx_generate_attrib(struct nvc0_grctx *info)

{

	struct nvc0_graph_priv *priv = info->priv;

	const struct nvc0_grctx_oclass *impl = (void *)nvc0_grctx_impl(priv);

	const u32  alpha = impl->alpha_nr;

	const u32 attrib = impl->attrib_nr;

	const u32   size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max);

	const u32 access = NV_MEM_ACCESS_RW;

	const int s = 12;

	const int b = mmio_vram(info, size * priv->tpc_total, (1 << s), access);

	const int max_batches = 0xffff;

	u32 bo = 0;

	u32 ao = bo + impl->attrib_nr_max * priv->tpc_total;

	int gpc, ppc, n = 0;



	mmio_refn(info, 0x418810, 0x80000000, s, b);

	mmio_refn(info, 0x419848, 0x10000000, s, b);

	mmio_refn(info, 0x419c2c, 0x10000000, s, b);

	mmio_wr32(info, 0x405830, (attrib << 16) | alpha);

	mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) | max_batches);



	for (gpc = 0; gpc < priv->gpc_nr; gpc++) {

		for (ppc = 0; ppc < priv->ppc_nr[gpc]; ppc++, n++) {

			const u32 as =  alpha * priv->ppc_tpc_nr[gpc][ppc];

			const u32 bs = attrib * priv->ppc_tpc_nr[gpc][ppc];

			const u32 u = 0x418ea0 + (n * 0x04);

			const u32 o = PPC_UNIT(gpc, ppc, 0);

			mmio_wr32(info, o + 0xc0, bs);

			mmio_wr32(info, o + 0xf4, bo);

			bo += impl->attrib_nr_max * priv->ppc_tpc_nr[gpc][ppc];

			mmio_wr32(info, o + 0xe4, as);

			mmio_wr32(info, o + 0xf8, ao);

			ao += impl->alpha_nr_max * priv->ppc_tpc_nr[gpc][ppc];

			mmio_wr32(info, u, (0x715 /*XXX*/ << 16) | bs);

		}

	}

}



void

gm107_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)

{

	mmio_data(0x200000, 0x1000, NV_MEM_ACCESS_RW);



	mmio_list(0x418810, 0x80000000, 12, 2);

	mmio_list(0x419848, 0x10000000, 12, 2);

	mmio_list(0x419c2c, 0x10000000, 12, 2);



	mmio_list(0x405830, 0x0aa01000,  0, 0);

	mmio_list(0x4064c4, 0x0400ffff,  0, 0);



	/*XXX*/

	mmio_list(0x5030c0, 0x00001540,  0, 0);

	mmio_list(0x5030f4, 0x00000000,  0, 0);

	mmio_list(0x5030e4, 0x00002000,  0, 0);

	mmio_list(0x5030f8, 0x00003fc0,  0, 0);

	mmio_list(0x418ea0, 0x07151540,  0, 0);



	mmio_list(0x5032c0, 0x00001540,  0, 0);

	mmio_list(0x5032f4, 0x00001fe0,  0, 0);

	mmio_list(0x5032e4, 0x00002000,  0, 0);

	mmio_list(0x5032f8, 0x00006fc0,  0, 0);

	mmio_list(0x418ea4, 0x07151540,  0, 0);

}



static void
@@ -952,6 +970,7 @@ gm107_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) 


	oclass->bundle(info);

	oclass->pagepool(info);

	oclass->attrib(info);

	oclass->mods(priv, info);

	oclass->unkn(priv);
@@ -1012,4 +1031,9 @@ gm107_grctx_oclass = &(struct nvc0_grctx_oclass) { 
	.bundle_token_limit = 0x2c0,

	.pagepool = gm107_grctx_generate_pagepool,

	.pagepool_size = 0x8000,

	.attrib = gm107_grctx_generate_attrib,

	.attrib_nr_max = 0xff0,

	.attrib_nr = 0xaa0,

	.alpha_nr_max = 0x1800,

	.alpha_nr = 0x1000,

}.base;

drivers/gpu/drm/nouveau/core/engine/graph/ctxnv108.c

+5 −25
Original line number Diff line number Diff line
@@ -534,31 +534,6 @@ nv108_grctx_pack_ppc[] = { 
static void

nv108_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)

{

	u32 magic[GPC_MAX][2];

	u32 offset;

	int gpc;



	mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW);

	mmio_list(0x418810, 0x80000000, 12, 2);

	mmio_list(0x419848, 0x10000000, 12, 2);



	mmio_list(0x405830, 0x02180648,  0, 0);

	mmio_list(0x4064c4, 0x0192ffff,  0, 0);



	for (gpc = 0, offset = 0; gpc < priv->gpc_nr; gpc++) {

		u16 magic0 = 0x0218 * priv->tpc_nr[gpc];

		u16 magic1 = 0x0648 * priv->tpc_nr[gpc];

		magic[gpc][0]  = 0x10000000 | (magic0 << 16) | offset;

		magic[gpc][1]  = 0x00000000 | (magic1 << 16);

		offset += 0x0324 * priv->tpc_nr[gpc];

	}



	for (gpc = 0; gpc < priv->gpc_nr; gpc++) {

		mmio_list(GPC_UNIT(gpc, 0x30c0), magic[gpc][0], 0, 0);

		mmio_list(GPC_UNIT(gpc, 0x30e4), magic[gpc][1] | offset, 0, 0);

		offset += 0x07ff * priv->tpc_nr[gpc];

	}



	mmio_list(0x17e91c, 0x0b040a0b, 0, 0);

	mmio_list(0x17e920, 0x00090d08, 0, 0);

}
@@ -590,4 +565,9 @@ nv108_grctx_oclass = &(struct nvc0_grctx_oclass) { 
	.bundle_token_limit = 0x200,

	.pagepool = nve4_grctx_generate_pagepool,

	.pagepool_size = 0x8000,

	.attrib = nvd7_grctx_generate_attrib,

	.attrib_nr_max = 0x324,

	.attrib_nr = 0x218,

	.alpha_nr_max = 0x7ff,

	.alpha_nr = 0x648,

}.base;

drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c

+26 −12
Original line number Diff line number Diff line
@@ -1047,25 +1047,35 @@ nvc0_grctx_generate_pagepool(struct nvc0_grctx *info) 
}



void

nvc0_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)

nvc0_grctx_generate_attrib(struct nvc0_grctx *info)

{

	struct nvc0_graph_priv *priv = info->priv;

	const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(priv);

	const u32 attrib = impl->attrib_nr;

	const u32   size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max);

	const u32 access = NV_MEM_ACCESS_RW;

	const int s = 12;

	const int b = mmio_vram(info, size * priv->tpc_total, (1 << s), access);

	int gpc, tpc;

	u32 offset;



	mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW);



	mmio_list(0x418810, 0x80000000, 12, 2);

	mmio_list(0x419848, 0x10000000, 12, 2);

	u32 bo = 0;



	mmio_list(0x405830, 0x02180000, 0, 0);

	mmio_refn(info, 0x418810, 0x80000000, s, b);

	mmio_refn(info, 0x419848, 0x10000000, s, b);

	mmio_wr32(info, 0x405830, (attrib << 16));



	for (gpc = 0, offset = 0; gpc < priv->gpc_nr; gpc++) {

	for (gpc = 0; gpc < priv->gpc_nr; gpc++) {

		for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {

			u32 addr = TPC_UNIT(gpc, tpc, 0x0520);

			mmio_list(addr, 0x02180000 | offset, 0, 0);

			offset += 0x0324;

			const u32 o = TPC_UNIT(gpc, tpc, 0x0520);

			mmio_skip(info, o, (attrib << 16) | ++bo);

			mmio_wr32(info, o, (attrib << 16) | --bo);

			bo += impl->attrib_nr_max;

		}

	}

}



void

nvc0_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)

{

}



void
@@ -1236,6 +1246,7 @@ nvc0_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) 


	oclass->bundle(info);

	oclass->pagepool(info);

	oclass->attrib(info);

	oclass->mods(priv, info);

	oclass->unkn(priv);
@@ -1376,4 +1387,7 @@ nvc0_grctx_oclass = &(struct nvc0_grctx_oclass) { 
	.bundle_size = 0x1800,

	.pagepool = nvc0_grctx_generate_pagepool,

	.pagepool_size = 0x8000,

	.attrib = nvc0_grctx_generate_attrib,

	.attrib_nr_max = 0x324,

	.attrib_nr = 0x218,

}.base;