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Commit 67c6def0 authored by Zhiqiang Tu's avatar Zhiqiang Tu
Browse files

ARM: dts: msm: Add pcie for sa8195p 



Add pcie support which is required by wlan.

Change-Id: Id45400c8800f9855c52c3b6342f1d9f0ee5869ef
Signed-off-by: default avatarZhiqiang Tu <ztu@codeaurora.org>
parent 62d644e7

arch/arm64/boot/dts/qcom/sa8195p-pcie.dtsi

0 → 100644
+805 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#include <dt-bindings/clock/qcom,gcc-sdmshrike.h>



&soc {

	pcie0: qcom,pcie@1c00000 {

		compatible = "qcom,pci-msm";

		cell-index = <0>;



		reg = <0x1c00000 0x4000>,

			<0x1c06000 0x1000>,

			<0x60000000 0xf1d>,

			<0x60000f20 0xa8>,

			<0x60001000 0x1000>,

			<0x60100000 0x100000>,

			<0x60200000 0x100000>,

			<0x60300000 0x3d00000>;



		reg-names = "parf", "phy", "dm_core", "elbi",

				"iatu", "conf", "io", "bars";



		#address-cells = <3>;

		#size-cells = <2>;

		ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>,

			<0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>;

		interrupt-parent = <&pcie0>;

		interrupts = <0 1 2 3 4>;

		interrupt-names = "int_global_int", "int_a", "int_b", "int_c",

				"int_d";

		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 0xffffffff>;

		interrupt-map = < 0 0 0 0 &intc 0 140 0

				0 0 0 1 &intc 0 149 0

				0 0 0 2 &intc 0 150 0

				0 0 0 3 &intc 0 151 0

				0 0 0 4 &intc 0 152 0>;



		qcom,phy-sequence = <0x0840 0x03 0x0

				0x0094 0x08 0x0

				0x0154 0x34 0x0

				0x016c 0x08 0x0

				0x0058 0x0f 0x0

				0x00a4 0x42 0x0

				0x0110 0x24 0x0

				0x011c 0x03 0x0

				0x0118 0xb4 0x0

				0x010c 0x02 0x0

				0x01bc 0x11 0x0

				0x00bc 0x82 0x0

				0x00d4 0x03 0x0

				0x00d0 0x55 0x0

				0x00cc 0x55 0x0

				0x00b0 0x1a 0x0

				0x00ac 0x0a 0x0

				0x00c4 0x68 0x0

				0x00e0 0x02 0x0

				0x00dc 0xaa 0x0

				0x00d8 0xab 0x0

				0x00b8 0x34 0x0

				0x00b4 0x14 0x0

				0x0158 0x01 0x0

				0x0074 0x06 0x0

				0x007c 0x16 0x0

				0x0084 0x36 0x0

				0x0078 0x06 0x0

				0x0080 0x16 0x0

				0x0088 0x36 0x0

				0x01b0 0x1e 0x0

				0x01ac 0xb9 0x0

				0x01b8 0x18 0x0

				0x01b4 0x94 0x0

				0x0050 0x07 0x0

				0x0010 0x00 0x0

				0x001c 0x31 0x0

				0x0020 0x01 0x0

				0x0024 0xde 0x0

				0x0028 0x07 0x0

				0x0030 0x4c 0x0

				0x0034 0x06 0x0

				0x029c 0x12 0x0

				0x0284 0x35 0x0

				0x023c 0x11 0x0

				0x051c 0x03 0x0

				0x0518 0x1c 0x0

				0x0524 0x1e 0x0

				0x04e8 0x00 0x0

				0x04ec 0x0e 0x0

				0x04f0 0x4a 0x0

				0x04f4 0x0f 0x0

				0x05b4 0x04 0x0

				0x0434 0x7f 0x0

				0x0444 0x70 0x0

				0x0510 0x17 0x0

				0x04d4 0x54 0x0

				0x04d8 0x07 0x0

				0x0598 0xd4 0x0

				0x059c 0x54 0x0

				0x05a0 0xdb 0x0

				0x05a4 0x3b 0x0

				0x05a8 0x31 0x0

				0x0584 0x24 0x0

				0x0588 0xe4 0x0

				0x058c 0xec 0x0

				0x0590 0x3b 0x0

				0x0594 0x36 0x0

				0x0570 0xff 0x0

				0x0574 0xff 0x0

				0x0578 0xff 0x0

				0x057c 0x7f 0x0

				0x0580 0x66 0x0

				0x04fc 0x00 0x0

				0x04f8 0xc0 0x0

				0x0460 0x30 0x0

				0x0464 0xc0 0x0

				0x05bc 0x0c 0x0

				0x04dc 0x0d 0x0

				0x0408 0x0c 0x0

				0x0414 0x03 0x0

				0x09a4 0x01 0x0

				0x0c90 0x00 0x0

				0x0c40 0x01 0x0

				0x0c48 0x01 0x0

				0x0c50 0x00 0x0

				0x0cbc 0x00 0x0

				0x0ce0 0x58 0x0

				0x0048 0x90 0x0

				0x0c1c 0xc1 0x0

				0x0988 0x88 0x0

				0x0998 0x0b 0x0

				0x08dc 0x0d 0x0

				0x09ec 0x01 0x0

				0x0800 0x00 0x0

				0x0844 0x03 0x0>;



		pinctrl-names = "default";

		pinctrl-0 = <&pcie0_clkreq_default

			&pcie0_perst_default

			&pcie0_wake_default>;



		perst-gpio = <&tlmm 35 0>;

		wake-gpio = <&tlmm 37 0>;



		gdsc-vdd-supply = <&pcie_0_gdsc>;

		vreg-1.8-supply = <&pm8195_1_l9>;

		vreg-0.9-supply = <&pm8195_3_l5>;

		vreg-cx-supply = <&VDD_CX_LEVEL>;



		qcom,vreg-1.8-voltage-level = <1200000 1200000 24000>;

		qcom,vreg-0.9-voltage-level = <880000 880000 24000>;

		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX

						RPMH_REGULATOR_LEVEL_NOM 0>;



		msi-parent = <&pcie0_msi>;



		qcom,no-l0s-supported;

		qcom,no-l1-supported;

		qcom,no-l1ss-supported;

		qcom,no-aux-clk-sync;



		qcom,ep-latency = <10>;



		qcom,slv-addr-space-size = <0x4000000>;



		qcom,phy-status-offset = <0x814>;

		qcom,phy-status-bit = <6>;

		qcom,phy-power-down-offset = <0x840>;



		qcom,boot-option = <0x1>;



		linux,pci-domain = <0>;



		qcom,pcie-phy-ver = <2110>;

		qcom,use-19p2mhz-aux-clk;



		qcom,smmu-sid-base = <0x1d80>;



		iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,

			<0x100 &apps_smmu 0x1d81 0x1>,

			<0x200 &apps_smmu 0x1d82 0x1>,

			<0x300 &apps_smmu 0x1d83 0x1>,

			<0x400 &apps_smmu 0x1d84 0x1>,

			<0x500 &apps_smmu 0x1d85 0x1>,

			<0x600 &apps_smmu 0x1d86 0x1>,

			<0x700 &apps_smmu 0x1d87 0x1>,

			<0x800 &apps_smmu 0x1d88 0x1>,

			<0x900 &apps_smmu 0x1d89 0x1>,

			<0xa00 &apps_smmu 0x1d8a 0x1>,

			<0xb00 &apps_smmu 0x1d8b 0x1>,

			<0xc00 &apps_smmu 0x1d8c 0x1>,

			<0xd00 &apps_smmu 0x1d8d 0x1>,

			<0xe00 &apps_smmu 0x1d8e 0x1>,

			<0xf00 &apps_smmu 0x1d8f 0x1>;



		qcom,msm-bus,name = "pcie0";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<45 512 0 0>,

				<45 512 500 800>;



		clocks = <&clock_gcc GCC_PCIE_0_PIPE_CLK>,

			<&clock_rpmh RPMH_CXO_CLK>,

			<&clock_gcc GCC_PCIE_0_AUX_CLK>,

			<&clock_gcc GCC_PCIE_0_CFG_AHB_CLK>,

			<&clock_gcc GCC_PCIE_0_MSTR_AXI_CLK>,

			<&clock_gcc GCC_PCIE_0_SLV_AXI_CLK>,

			<&clock_gcc GCC_PCIE_0_CLKREF_CLK>,

			<&clock_gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,

			<&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,

			<&clock_gcc GCC_PCIE0_PHY_REFGEN_CLK>,

			<&clock_gcc GCC_PCIE_PHY_AUX_CLK>;



		clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",

				"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",

				"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",

				"pcie_0_ldo", "pcie_0_slv_q2a_axi_clk",

				"pcie_tbu_clk", "pcie_phy_refgen_clk",

				"pcie_phy_aux_clk";



		max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,

					<0>, <0>, <0>, <0>, <100000000>, <0>;



		resets = <&clock_gcc GCC_PCIE_0_BCR>,

			<&clock_gcc GCC_PCIE_0_PHY_BCR>;



		reset-names = "pcie_0_core_reset",

				"pcie_0_phy_reset";



		pcie_rc0: pcie_rc0 {

			reg = <0 0 0 0 0>;

			pci-ids = "17cb:0108";

		};

	};



	pcie0_msi: qcom,pcie0_msi@17a00040 {

		compatible = "qcom,pci-msi";

		msi-controller;

		reg = <0x17a00040 0x0>;

		interrupt-parent = <&pdc>;

		interrupts = <GIC_SPI 868 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 869 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 870 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 871 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 872 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 873 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 874 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 875 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 876 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 877 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 878 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 879 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 880 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 881 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 882 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 883 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 884 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 885 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 886 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 887 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 888 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 889 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 890 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 891 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 892 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 893 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 894 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 895 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 896 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 897 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 898 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 899 IRQ_TYPE_EDGE_RISING>;

	};



	pcie1: qcom,pcie@1c08000 {

		compatible = "qcom,pci-msm";

		cell-index = <1>;



		reg = <0x1c08000 0x4000>,

			<0x1c0e000 0x2000>,

			<0x40000000 0xf1d>,

			<0x40000f20 0xa8>,

			<0x40001000 0x1000>,

			<0x40100000 0x100000>,

			<0x40200000 0x100000>,

			<0x40300000 0x1fd00000>;



		reg-names = "parf", "phy", "dm_core", "elbi",

				"iatu", "conf", "io", "bars";



		#address-cells = <3>;

		#size-cells = <2>;

		ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,

			<0x02000000 0x0 0x40300000 0x40300000 0x0 0x1fd00000>;

		interrupt-parent = <&pcie1>;

		interrupts = <0 1 2 3 4>;

		interrupt-names = "int_global_int", "int_a", "int_b", "int_c",

				"int_d";

		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 0xffffffff>;

		interrupt-map = <0 0 0 0 &intc 0 306 0

				0 0 0 1 &intc 0 434 0

				0 0 0 2 &intc 0 435 0

				0 0 0 3 &intc 0 438 0

				0 0 0 4 &intc 0 439 0>;



		qcom,phy-sequence = <0x0a40 0x03 0x0

				0x0010 0x00 0x0

				0x001c 0x31 0x0

				0x0020 0x01 0x0

				0x0024 0xde 0x0

				0x0028 0x07 0x0

				0x0030 0x4c 0x0

				0x0034 0x06 0x0

				0x0048 0x90 0x0

				0x0058 0x0f 0x0

				0x0074 0x06 0x0

				0x0078 0x06 0x0

				0x007c 0x16 0x0

				0x0080 0x16 0x0

				0x0084 0x36 0x0

				0x0088 0x36 0x0

				0x0094 0x08 0x0

				0x00a4 0x42 0x0

				0x00ac 0x0a 0x0

				0x00b0 0x1a 0x0

				0x00b4 0x14 0x0

				0x00b8 0x34 0x0

				0x00bc 0x82 0x0

				0x00c4 0x68 0x0

				0x00cc 0x55 0x0

				0x00d0 0x55 0x0

				0x00d4 0x03 0x0

				0x00d8 0xab 0x0

				0x00dc 0xaa 0x0

				0x00e0 0x02 0x0

				0x010c 0x02 0x0

				0x0110 0x24 0x0

				0x0118 0xb4 0x0

				0x011c 0x03 0x0

				0x0154 0x34 0x0

				0x0158 0x01 0x0

				0x016c 0x08 0x0

				0x01ac 0xb9 0x0

				0x01b0 0x1e 0x0

				0x01b4 0x94 0x0

				0x01b8 0x18 0x0

				0x01bc 0x11 0x0

				0x023c 0x11 0x0

				0x0284 0x35 0x0

				0x029c 0x12 0x0

				0x0304 0x02 0x0

				0x0408 0x0c 0x0

				0x0414 0x03 0x0

				0x0434 0x7f 0x0

				0x0444 0x70 0x0

				0x0460 0x30 0x0

				0x0464 0xc0 0x0

				0x04d4 0x54 0x0

				0x04d8 0x07 0x0

				0x04dc 0x0d 0x0

				0x04e8 0x00 0x0

				0x04ec 0x0e 0x0

				0x04f0 0x4a 0x0

				0x04f4 0x0f 0x0

				0x04f8 0xc0 0x0

				0x04fc 0x00 0x0

				0x0510 0x17 0x0

				0x0518 0x1c 0x0

				0x051c 0x03 0x0

				0x0524 0x1e 0x0

				0x0570 0xff 0x0

				0x0574 0xff 0x0

				0x0578 0xff 0x0

				0x057c 0x7f 0x0

				0x0580 0x66 0x0

				0x0584 0x24 0x0

				0x0588 0xe4 0x0

				0x058c 0xec 0x0

				0x0590 0x3b 0x0

				0x0594 0x36 0x0

				0x0598 0xd4 0x0

				0x059c 0x54 0x0

				0x05a0 0xdb 0x0

				0x05a4 0x3b 0x0

				0x05a8 0x31 0x0

				0x05bc 0x0c 0x0

				0x063c 0x11 0x0

				0x0684 0x35 0x0

				0x069c 0x12 0x0

				0x0704 0x20 0x0

				0x0808 0x0c 0x0

				0x0814 0x03 0x0

				0x0834 0x7f 0x0

				0x0844 0x70 0x0

				0x0860 0x30 0x0

				0x0864 0xc0 0x0

				0x08d4 0x54 0x0

				0x08d8 0x07 0x0

				0x08dc 0x0d 0x0

				0x08e8 0x00 0x0

				0x08ec 0x0e 0x0

				0x08f0 0x4a 0x0

				0x08f4 0x0f 0x0

				0x08f8 0xc0 0x0

				0x08fc 0x00 0x0

				0x0910 0x17 0x0

				0x0918 0x1c 0x0

				0x091c 0x03 0x0

				0x0924 0x1e 0x0

				0x0970 0xff 0x0

				0x0974 0xff 0x0

				0x0978 0xff 0x0

				0x097c 0x7f 0x0

				0x0980 0x66 0x0

				0x0984 0x24 0x0

				0x0988 0xe4 0x0

				0x098c 0xec 0x0

				0x0990 0x3b 0x0

				0x0994 0x36 0x0

				0x0998 0xd4 0x0

				0x099c 0x54 0x0

				0x09a0 0xdb 0x0

				0x09a4 0x3b 0x0

				0x09a8 0x31 0x0

				0x09bc 0x0c 0x0

				0x0adc 0x05 0x0

				0x0b88 0x88 0x0

				0x0b98 0x0b 0x0

				0x0ba4 0x01 0x0

				0x0bec 0x01 0x0

				0x0e0c 0x0d 0x0

				0x0e14 0x07 0x0

				0x0e1c 0xc1 0x0

				0x0e40 0x01 0x0

				0x0e48 0x01 0x0

				0x0e90 0x00 0x0

				0x0ebc 0x00 0x0

				0x0ee0 0x58 0x0

				0x0a00 0x00 0x0

				0x0a44 0x03 0x0>;



		pinctrl-names = "default";

		pinctrl-0 = <&pcie1_clkreq_default

			&pcie1_perst_default

			&pcie1_wake_default>;



		perst-gpio = <&tlmm 102 0>;

		wake-gpio = <&tlmm 104 0>;



		gdsc-vdd-supply = <&pcie_1_gdsc>;

		vreg-1.8-supply = <&pm8195_1_l9>;

		vreg-0.9-supply = <&pm8195_3_l5>;

		vreg-cx-supply = <&VDD_CX_LEVEL>;



		qcom,vreg-1.8-voltage-level = <1200000 1200000 24000>;

		qcom,vreg-0.9-voltage-level = <880000 880000 24000>;

		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX

						RPMH_REGULATOR_LEVEL_NOM 0>;



		msi-parent = <&pcie1_msi>;



		qcom,no-l0s-supported;



		qcom,ep-latency = <10>;



		qcom,slv-addr-space-size = <0x20000000>;



		qcom,phy-status-offset = <0xa14>;

		qcom,phy-status-bit = <6>;

		qcom,phy-power-down-offset = <0xa40>;



		qcom,boot-option = <0x1>;



		linux,pci-domain = <1>;



		qcom,pcie-phy-ver = <2105>;

		qcom,use-19p2mhz-aux-clk;



		qcom,smmu-sid-base = <0x1e00>;



		iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,

			<0x100 &apps_smmu 0x1e01 0x1>,

			<0x200 &apps_smmu 0x1e02 0x1>,

			<0x300 &apps_smmu 0x1e03 0x1>,

			<0x400 &apps_smmu 0x1e04 0x1>,

			<0x500 &apps_smmu 0x1e05 0x1>,

			<0x600 &apps_smmu 0x1e06 0x1>,

			<0x700 &apps_smmu 0x1e07 0x1>,

			<0x800 &apps_smmu 0x1e08 0x1>,

			<0x900 &apps_smmu 0x1e09 0x1>,

			<0xa00 &apps_smmu 0x1e0a 0x1>,

			<0xb00 &apps_smmu 0x1e0b 0x1>,

			<0xc00 &apps_smmu 0x1e0c 0x1>,

			<0xd00 &apps_smmu 0x1e0d 0x1>,

			<0xe00 &apps_smmu 0x1e0e 0x1>,

			<0xf00 &apps_smmu 0x1e0f 0x1>;



		qcom,msm-bus,name = "pcie1";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<100 512 0 0>,

				<100 512 500 800>;



		clocks = <&clock_gcc GCC_PCIE_1_PIPE_CLK>,

			<&clock_rpmh RPMH_CXO_CLK>,

			<&clock_gcc GCC_PCIE_1_AUX_CLK>,

			<&clock_gcc GCC_PCIE_1_CFG_AHB_CLK>,

			<&clock_gcc GCC_PCIE_1_MSTR_AXI_CLK>,

			<&clock_gcc GCC_PCIE_1_SLV_AXI_CLK>,

			<&clock_gcc GCC_PCIE_1_CLKREF_CLK>,

			<&clock_gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,

			<&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,

			<&clock_gcc GCC_PCIE1_PHY_REFGEN_CLK>,

			<&clock_gcc GCC_PCIE_PHY_AUX_CLK>;



		clock-names = "pcie_1_pipe_clk", "pcie_1_ref_clk_src",

				"pcie_1_aux_clk", "pcie_1_cfg_ahb_clk",

				"pcie_1_mstr_axi_clk", "pcie_1_slv_axi_clk",

				"pcie_1_ldo", "pcie_1_slv_q2a_axi_clk",

				"pcie_tbu_clk", "pcie_phy_refgen_clk",

				"pcie_phy_aux_clk";



		max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,

					<0>, <0>, <0>, <0>, <100000000>, <0>;



		resets = <&clock_gcc GCC_PCIE_1_BCR>,

			<&clock_gcc GCC_PCIE_1_PHY_BCR>;



		reset-names = "pcie_1_core_reset",

				"pcie_1_phy_reset";



		pcie_rc1: pcie_rc1 {

			reg = <0 0 0 0 0>;

			pci-ids = "17cb:0108";

		};

	};



	pcie1_msi: qcom,pcie1_msi@17a00040 {

		compatible = "qcom,pci-msi";

		msi-controller;

		reg = <0x17a00040 0x0>;

		interrupt-parent = <&pdc>;

		interrupts = <GIC_SPI 900 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 901 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 902 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 903 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 904 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 905 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 906 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 907 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 908 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 909 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 910 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 911 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 912 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 913 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 914 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 915 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 916 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 917 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 918 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 919 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 920 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 921 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 922 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 923 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 924 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 925 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 926 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 927 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 928 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 929 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 930 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 931 IRQ_TYPE_EDGE_RISING>;

	};



	pcie1_edma: qcom,pcie1_edma@40002000 {

		compatible = "qcom,pci-edma";

		#dma-cells = <2>;

		reg = <0x40002000 0x2000>;

		interrupt-parent = <&intc>;

		interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "pci-edma-int";

	};



	pcie_ep: qcom,pcie@40004000 {

		compatible = "qcom,pcie-ep";



		reg = <0x40004000 0x1000>,

			<0x40000000 0xf1d>,

			<0x40000f20 0xa8>,

			<0x40001000 0x1000>,

			<0x40002000 0x2000>,

			<0x01c08000 0x3000>,

			<0x01c0e000 0x2000>,

			<0x01c0b000 0x1000>;

		reg-names = "msi", "dm_core", "elbi", "iatu", "edma", "parf",

				"phy", "mmio";



		#address-cells = <0>;

		interrupt-parent = <&pcie_ep>;

		interrupts = <0>;

		#interrupt-cells = <1>;

		interrupt-map-mask = <0xffffffff>;

		interrupt-map = <0 &intc 0 306 0>;

		interrupt-names = "int_global";



		pinctrl-names = "default";

		pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default

			&pcie_ep_wake_default>;



		clkreq-gpio = <&tlmm 103 0>;

		perst-gpio = <&tlmm 102 0>;

		wake-gpio = <&tlmm 104 0>;



		gdsc-vdd-supply = <&pcie_1_gdsc>;

		vreg-1.8-supply = <&pm8195_1_l9>;

		vreg-0.9-supply = <&pm8195_3_l5>;

		vreg-cx-supply = <&VDD_CX_LEVEL>;



		qcom,vreg-1.8-voltage-level = <1200000 1200000 24000>;

		qcom,vreg-0.9-voltage-level = <880000 880000 24000>;

		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX

						RPMH_REGULATOR_LEVEL_NOM 0>;



		clocks = <&clock_gcc GCC_PCIE_1_PIPE_CLK>,

			<&clock_gcc GCC_PCIE_1_CFG_AHB_CLK>,

			<&clock_gcc GCC_PCIE_1_MSTR_AXI_CLK>,

			<&clock_gcc GCC_PCIE_1_SLV_AXI_CLK>,

			<&clock_gcc GCC_PCIE_1_AUX_CLK>,

			<&clock_gcc GCC_PCIE_1_CLKREF_CLK>,

			<&clock_gcc GCC_PCIE_PHY_AUX_CLK>,

			<&clock_gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>;



		clock-names = "pcie_pipe_clk", "pcie_cfg_ahb_clk",

				"pcie_mstr_axi_clk", "pcie_slv_axi_clk",

				"pcie_aux_clk", "pcie_ldo", "pcie_sleep_clk",

				"pcie_slv_q2a_axi_clk";



		resets = <&clock_gcc GCC_PCIE_1_BCR>,

			<&clock_gcc GCC_PCIE_1_PHY_BCR>;



		reset-names = "pcie_core_reset",

				"pcie_phy_reset";



		qcom,msm-bus,name = "pcie-ep";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<100 512 0 0>,

				<100 512 500 800>;



		qcom,pcie-link-speed = <3>;

		qcom,pcie-phy-ver = <6>;

		qcom,pcie-aggregated-irq;

		qcom,pcie-mhi-a7-irq;

		qcom,phy-status-reg = <0xa14>;



		qcom,phy-init = <0x0a40 0x01 0x0 0x1

				0x0094 0x00 0x0 0x1

				0x000c 0x02 0x0 0x1

				0x004c 0x07 0x0 0x1

				0x0050 0x07 0x0 0x1

				0x0058 0x0f 0x0 0x1

				0x0074 0x36 0x0 0x1

				0x0078 0x36 0x0 0x1

				0x007c 0x12 0x0 0x1

				0x0080 0x12 0x0 0x1

				0x0084 0x00 0x0 0x1

				0x0088 0x00 0x0 0x1

				0x00a4 0x42 0x0 0x1

				0x00ac 0xff 0x0 0x1

				0x00b0 0x04 0x0 0x1

				0x00b4 0xff 0x0 0x1

				0x00b8 0x09 0x0 0x1

				0x00bc 0x19 0x0 0x1

				0x00c4 0x14 0x0 0x1

				0x00ec 0xfb 0x0 0x1

				0x00f0 0x01 0x0 0x1

				0x00f4 0xfb 0x0 0x1

				0x00f8 0x01 0x0 0x1

				0x010c 0x02 0x0 0x1

				0x0110 0x24 0x0 0x1

				0x0118 0xb4 0x0 0x1

				0x011c 0x03 0x0 0x1

				0x0158 0x01 0x0 0x1

				0x016c 0x08 0x0 0x1

				0x01ac 0x56 0x0 0x1

				0x01b0 0x1d 0x0 0x1

				0x01b4 0x78 0x0 0x1

				0x01b8 0x17 0x0 0x1

				0x0154 0x31 0x0 0x1

				0x01bc 0x11 0x0 0x1

				0x0284 0x05 0x0 0x1

				0x029c 0x12 0x0 0x1

				0x0414 0x04 0x0 0x1

				0x0434 0x7f 0x0 0x1

				0x0444 0x70 0x0 0x1

				0x04d8 0x01 0x0 0x1

				0x04ec 0x0e 0x0 0x1

				0x04f0 0x4a 0x0 0x1

				0x04f4 0x0f 0x0 0x1

				0x04f8 0xc0 0x0 0x1

				0x04fc 0x00 0x0 0x1

				0x0510 0x17 0x0 0x1

				0x0518 0x1c 0x0 0x1

				0x051c 0x03 0x0 0x1

				0x0524 0x14 0x0 0x1

				0x05b4 0x04 0x0 0x1

				0x0570 0xbd 0x0 0x1

				0x0574 0xbd 0x0 0x1

				0x0578 0x7f 0x0 0x1

				0x057c 0xdb 0x0 0x1

				0x0580 0x76 0x0 0x1

				0x0584 0x24 0x0 0x1

				0x0588 0xe4 0x0 0x1

				0x058c 0xec 0x0 0x1

				0x0590 0x39 0x0 0x1

				0x0594 0x37 0x0 0x1

				0x0598 0xd4 0x0 0x1

				0x059c 0x54 0x0 0x1

				0x05a0 0xdb 0x0 0x1

				0x05a4 0x39 0x0 0x1

				0x05a8 0x31 0x0 0x1

				0x0684 0x05 0x0 0x1

				0x069c 0x12 0x0 0x1

				0x0814 0x04 0x0 0x1

				0x0834 0x7f 0x0 0x1

				0x0844 0x70 0x0 0x1

				0x08d8 0x01 0x0 0x1

				0x08ec 0x0e 0x0 0x1

				0x08f0 0x4a 0x0 0x1

				0x08f4 0x0f 0x0 0x1

				0x08f8 0xc0 0x0 0x1

				0x08fc 0x00 0x0 0x1

				0x0910 0x17 0x0 0x1

				0x0918 0x1c 0x0 0x1

				0x091c 0x03 0x0 0x1

				0x0924 0x14 0x0 0x1

				0x09b4 0x04 0x0 0x1

				0x0970 0xbd 0x0 0x1

				0x0974 0xbd 0x0 0x1

				0x0978 0x7f 0x0 0x1

				0x097c 0xdb 0x0 0x1

				0x0980 0x76 0x0 0x1

				0x0984 0x24 0x0 0x1

				0x0988 0xe4 0x0 0x1

				0x098c 0xec 0x0 0x1

				0x0990 0x39 0x0 0x1

				0x0994 0x37 0x0 0x1

				0x0998 0xd4 0x0 0x1

				0x099c 0x54 0x0 0x1

				0x09a0 0xdb 0x0 0x1

				0x09a4 0x39 0x0 0x1

				0x09a8 0x31 0x0 0x1

				0x0a98 0x01 0x0 0x1

				0x0abc 0x56 0x0 0x1

				0x0adc 0x0d 0x0 0x1

				0x0b88 0xaa 0x0 0x1

				0x0ba4 0x01 0x0 0x1

				0x0e0c 0x04 0x0 0x1

				0x0e14 0x07 0x0 0x1

				0x0e40 0x01 0x0 0x1

				0x0e48 0x01 0x0 0x1

				0x0e78 0x50 0x0 0x1

				0x0ea0 0x11 0x0 0x1

				0x0ebc 0x00 0x0 0x1

				0x0ee0 0x58 0x0 0x1

				0x0a00 0x00 0x0 0x1

				0x0a44 0x03 0x0 0x1>;



		edma-parent = <&pcie1_edma>;

		iommus = <&apps_smmu 0x1e00 0x0>;

		qcom,pcie-edma;

		status = "disabled";

	};



	mhi_device: mhi_dev@1c0b000 {

		compatible = "qcom,msm-mhi-dev";

		reg = <0x1c0b000 0x1000>;

		reg-names = "mhi_mmio_base";

		qcom,mhi-ep-msi = <0>;

		qcom,mhi-version = <0x1000000>;

		qcom,use-pcie-edma;

		dmas = <&pcie1_edma 0 0>, <&pcie1_edma 1 0>;

		dma-names = "tx", "rx";

		interrupts = <0 440 0>;

		interrupt-names = "mhi-device-inta";

		qcom,mhi-ifc-id = <0x010817cb>;

		qcom,mhi-interrupt;

		status = "disabled";

	};

};