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Commit 66f0a6fb authored by Zhiqiang Tu's avatar Zhiqiang Tu Committed by Chao Bi
Browse files

clk: qcom: fix pcie virtual clock name mismatch 



The clock name mismatch between frontend and backend causes
clock operation failure.

Change-Id: If0d09485251e7a031d56fe51385026a6f1227b9b
Signed-off-by: default avatarZhiqiang Tu <ztu@codeaurora.org>
parent 711638a2

drivers/clk/qcom/virtio_clk_sm6150.c

+1 −1
Original line number Diff line number Diff line
@@ -48,7 +48,7 @@ static const char * const sm6150_gcc_virtio_clocks[] = { 
	[GCC_PCIE_0_CFG_AHB_CLK] = "gcc_pcie_0_cfg_ahb_clk",

	[GCC_PCIE_0_MSTR_AXI_CLK] = "gcc_pcie_0_mstr_axi_clk",

	[GCC_PCIE_0_SLV_AXI_CLK] = "gcc_pcie_0_slv_axi_clk",

	[GCC_PCIE_0_CLKREF_CLK] = "gcc_pcie_0_clkref_clk",

	[GCC_PCIE_0_CLKREF_CLK] = "gcc_pcie_0_clkref_en",

	[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = "gcc_pcie_0_slv_q2a_axi_clk",

	[GCC_PCIE0_PHY_REFGEN_CLK] = "gcc_pcie0_phy_refgen_clk",

	[GCC_PCIE_PHY_AUX_CLK] = "gcc_pcie_phy_aux_clk",

drivers/clk/qcom/virtio_clk_sm8150.c

+1 −1
Original line number Diff line number Diff line
@@ -65,7 +65,7 @@ static const char * const sm8150_gcc_virtio_clocks[] = { 
	[GCC_PCIE_0_CFG_AHB_CLK] = "gcc_pcie_0_cfg_ahb_clk",

	[GCC_PCIE_0_MSTR_AXI_CLK] = "gcc_pcie_0_mstr_axi_clk",

	[GCC_PCIE_0_SLV_AXI_CLK] = "gcc_pcie_0_slv_axi_clk",

	[GCC_PCIE_0_CLKREF_CLK] = "gcc_pcie_0_clkref_clk",

	[GCC_PCIE_0_CLKREF_CLK] = "gcc_pcie_0_clkref_en",

	[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = "gcc_pcie_0_slv_q2a_axi_clk",

	[GCC_AGGRE_NOC_PCIE_TBU_CLK] = "gcc_aggre_noc_pcie_tbu_clk",

	[GCC_PCIE0_PHY_REFGEN_CLK] = "gcc_pcie0_phy_refgen_clk",