x86/mce/AMD: Ensure the deferred error interrupt is of type APIC on SMCA systems (66ef269d) · Commits · e / devices / android_kernel_oneplus_sm8150

The Deferred Error Interrupt Type is set per bank on Scalable MCA systems. This is done in a bitfield in the MCA_CONFIG register of each bank. We should set its type to APIC-based interrupt and not assume BIOS has set it for us. Signed-off-by:

Yazen Ghannam <Yazen.Ghannam@amd.com> Signed-off-by:

Borislav Petkov <bp@suse.de> Link: http://lkml.kernel.org/r/1472737486-1720-1-git-send-email-Yazen.Ghannam@amd.com Signed-off-by:

Thomas Gleixner <tglx@linutronix.de>

arch/x86/kernel/cpu/mcheck/mce_amd.c

+14 −0

Original line number	Diff line number	Diff line
		@@ -463,6 +463,20 @@ prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr,
		*/
		smca_high &= ~BIT(2);

		/*
		* SMCA sets the Deferred Error Interrupt type per bank.
		*
		* MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us
		* if the DeferredIntType bit field is available.
		*
		* MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the
		* high portion of the MSR). OS should set this to 0x1 to enable
		* APIC based interrupt. First, check that no interrupt has been
		* set.
		*/
		if ((smca_low & BIT(5)) && !((smca_high >> 5) & 0x3))
		smca_high \|= BIT(5);

		wrmsr(smca_addr, smca_low, smca_high);
		}