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Commit 66dbebfa authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge changes Ie48eb991,I10c84872 into msm-next 

* changes:
  ARM: dts: msm: Add jtagv8 devices for SDM855
  ARM: dts: msm: Add coresight devices for SDM855
parents 089ac12e 3a3396d1

arch/arm64/boot/dts/qcom/sdm855-coresight.dtsi

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+2410 −0

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arch/arm64/boot/dts/qcom/sdm855.dtsi

+89 −0
Original line number Diff line number Diff line
@@ -462,6 +462,94 @@ 
	ranges = <0 0 0 0xffffffff>;

	compatible = "simple-bus";



	jtag_mm0: jtagmm@7040000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x7040000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";



		qcom,coresight-jtagmm-cpu = <&CPU0>;

	};



	jtag_mm1: jtagmm@7140000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x7140000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";



		qcom,coresight-jtagmm-cpu = <&CPU1>;

	};



	jtag_mm2: jtagmm@7240000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x7240000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";



		qcom,coresight-jtagmm-cpu = <&CPU2>;

	};



	jtag_mm3: jtagmm@7340000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x7340000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";



		qcom,coresight-jtagmm-cpu = <&CPU3>;

	};



	jtag_mm4: jtagmm@7440000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x7440000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";



		qcom,coresight-jtagmm-cpu = <&CPU4>;

	};



	jtag_mm5: jtagmm@7540000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x7540000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";



		qcom,coresight-jtagmm-cpu = <&CPU5>;

	};



	jtag_mm6: jtagmm@7640000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x7640000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";



		qcom,coresight-jtagmm-cpu = <&CPU6>;

	};



	jtag_mm7: jtagmm@7740000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x7740000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";



		qcom,coresight-jtagmm-cpu = <&CPU7>;

	};



	intc: interrupt-controller@17a00000 {

		compatible = "arm,gic-v3";

		#interrupt-cells = <3>;
@@ -1475,4 +1563,5 @@ 
#include "sdm855-regulator.dtsi"

#include "sdm855-ion.dtsi"

#include "sdm855-smp2p.dtsi"

#include "sdm855-coresight.dtsi"

#include "msm-arm-smmu-sdm855.dtsi"