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Commit 66953a2e authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "UPSTREAM: Merge commit '2e180d28' into mainline PC208 0724"

parents c6abd655 00eff686

Documentation/devicetree/bindings/media/video/msm-cam-fd.txt

+5 −0
Original line number Diff line number Diff line
@@ -108,6 +108,11 @@ about the device register map, interrupt map, clocks, regulators. 
  Value type: <string>

  Definition: Source clock name.



- clock-control-debugfs

  Usage: optional

  Value type: <string>

  Definition: Enable/Disable clk rate control.



- clock-cntl-level

  Usage: required

  Value type: <string>

Documentation/devicetree/bindings/media/video/msm-cam-icp.txt

+5 −0
Original line number Diff line number Diff line
@@ -110,6 +110,11 @@ and name of firmware image. 
  Value type: <string>

  Definition: Source clock name.



- clock-control-debugfs

  Usage: optional

  Value type: <string>

  Definition: Enable/Disable clk rate control.



- clocks

  Usage: required

  Value type: <phandle>

Documentation/devicetree/bindings/media/video/msm-cam-ife-csid.txt

+4 −1
Original line number Diff line number Diff line
@@ -79,7 +79,10 @@ First Level Node - CAM IFE CSID device 
  Value type: <string>

  Definition: Source clock name.





- clock-control-debugfs

  Usage: optional

  Value type: <string>

  Definition: Enable/Disable clk rate control.



Example:

Documentation/devicetree/bindings/media/video/msm-cam-vfe.txt

+5 −0
Original line number Diff line number Diff line
@@ -91,6 +91,11 @@ Optional properties: 
  Value type: <u32>

  Definition: List of clocks rates for optional clocks.



- clock-control-debugfs

  Usage: optional

  Value type: <string>

  Definition: Enable/Disable clk rate control.



Example:

	qcom,vfe0@acaf000 {

		cell-index = <0>;

arch/arm64/boot/dts/qcom/sm8150-camera.dtsi

+16 −1
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@ 
			"csiphy0_clk",

			"csi0phytimer_clk_src",

			"csi0phytimer_clk";

		src-clock-name = "csi0phytimer_clk_src";

		clock-cntl-level = "turbo";

		clock-rates =

			<400000000 0 300000000 0>;
@@ -63,6 +64,7 @@ 
			"csiphy1_clk",

			"csi1phytimer_clk_src",

			"csi1phytimer_clk";

		src-clock-name = "csi1phytimer_clk_src";

		clock-cntl-level = "turbo";

		clock-rates =

			<400000000 0 300000000 0>;
@@ -90,6 +92,7 @@ 
			"csiphy2_clk",

			"csi2phytimer_clk_src",

			"csi2phytimer_clk";

		src-clock-name = "csi2phytimer_clk_src";

		clock-cntl-level = "turbo";

		clock-rates =

			<400000000 0 300000000 0>;
@@ -116,6 +119,7 @@ 
			"csiphy3_clk",

			"csi3phytimer_clk_src",

			"csi3phytimer_clk";

		src-clock-name = "csi3phytimer_clk_src";

		clock-cntl-level = "turbo";

		clock-rates =

			<400000000 0 300000000 0>;
@@ -498,7 +502,6 @@ 
		reg-cam-base = <0x40000 0x42000>;

		interrupt-names = "cpas_camnoc";

		interrupts = <0 459 0>;

		qcom,cpas-hw-ver = <0x175100>; /* Titan v175 v1.0.0 */

		camnoc-axi-min-ib-bw = <3000000000>;

		regulator-names = "camss-vdd";

		camss-vdd-supply = <&titan_top_gdsc>;
@@ -735,6 +738,7 @@ 
			<600000000 0 0 0 760000000 0 0>;

		clock-cntl-level = "svs", "svs_l1", "turbo";

		src-clock-name = "ife_csid_clk_src";

		clock-control-debugfs = "true";

		status = "ok";

	};
@@ -763,6 +767,7 @@ 
			<760000000 0 0>;

		clock-cntl-level = "svs", "svs_l1", "turbo";

		src-clock-name = "ife_clk_src";

		clock-control-debugfs = "true";

		clock-names-option =  "ife_dsp_clk";

		clocks-option = <&clock_camcc CAM_CC_IFE_0_DSP_CLK>;

		clock-rates-option = <760000000>;
@@ -802,6 +807,7 @@ 
			<600000000 0 0 0 760000000 0 0>;

		clock-cntl-level = "svs", "svs_l1", "turbo";

		src-clock-name = "ife_csid_clk_src";

		clock-control-debugfs = "true";

		status = "ok";

	};
@@ -830,6 +836,7 @@ 
			<760000000 0 0>;

		clock-cntl-level = "svs", "svs_l1", "turbo";

		src-clock-name = "ife_clk_src";

		clock-control-debugfs = "true";

		clock-names-option =  "ife_dsp_clk";

		clocks-option = <&clock_camcc CAM_CC_IFE_1_DSP_CLK>;

		clock-rates-option = <760000000>;
@@ -866,6 +873,7 @@ 
			<600000000 0 0 0 600000000 0>;

		clock-cntl-level = "svs", "svs_l1", "turbo";

		src-clock-name = "ife_csid_clk_src";

		clock-control-debugfs = "true";

		status = "ok";

	};
@@ -891,6 +899,7 @@ 
			<600000000 0>;

		clock-cntl-level = "svs", "svs_l1", "turbo";

		src-clock-name = "ife_clk_src";

		clock-control-debugfs = "true";

		status = "ok";

	};
@@ -924,6 +933,7 @@ 
			<600000000 0 0 0 600000000 0>;

		clock-cntl-level = "svs", "svs_l1", "turbo";

		src-clock-name = "ife_csid_clk_src";

		clock-control-debugfs = "true";

		status = "ok";

	};
@@ -949,6 +959,7 @@ 
			<600000000 0>;

		clock-cntl-level = "svs", "svs_l1", "turbo";

		src-clock-name = "ife_clk_src";

		clock-control-debugfs = "true";

		status = "ok";

	};
@@ -1011,6 +1022,7 @@ 
			"ipe_0_clk_src",

			"ipe_0_clk";

		src-clock-name = "ipe_0_clk_src";

		clock-control-debugfs = "true";

		clocks =

			<&clock_camcc CAM_CC_IPE_0_AHB_CLK>,

			<&clock_camcc CAM_CC_IPE_0_AREG_CLK>,
@@ -1043,6 +1055,7 @@ 
			"ipe_1_clk_src",

			"ipe_1_clk";

		src-clock-name = "ipe_1_clk_src";

		clock-control-debugfs = "true";

		clocks =

			<&clock_camcc CAM_CC_IPE_1_AHB_CLK>,

			<&clock_camcc CAM_CC_IPE_1_AREG_CLK>,
@@ -1075,6 +1088,7 @@ 
			"bps_clk_src",

			"bps_clk";

		src-clock-name = "bps_clk_src";

		clock-control-debugfs = "true";

		clocks =

			<&clock_camcc CAM_CC_BPS_AHB_CLK>,

			<&clock_camcc CAM_CC_BPS_AREG_CLK>,
@@ -1174,6 +1188,7 @@ 
			<&clock_camcc CAM_CC_FD_CORE_CLK>,

			<&clock_camcc CAM_CC_FD_CORE_UAR_CLK>;

		src-clock-name = "fd_core_clk_src";

		clock-control-debugfs = "true";

		clock-cntl-level = "svs", "svs_l1", "turbo";

		clock-rates =

			<400000000 0 0>,