Loading arch/arm/kernel/hw_breakpoint.c +23 −0 Original line number Diff line number Diff line Loading @@ -226,6 +226,18 @@ static int get_num_brps(void) return core_has_mismatch_brps() ? brps - 1 : brps; } /* Determine if halting mode is enabled */ static int halting_mode_enabled(void) { u32 dscr; ARM_DBG_READ(c0, c1, 0, dscr); WARN_ONCE(dscr & ARM_DSCR_HDBGEN, "halting debug mode enabled. Unable to access hardware resources.\n"); return !!(dscr & ARM_DSCR_HDBGEN); } /* * In order to access the breakpoint/watchpoint control registers, * we must be running in debug monitor mode. Unfortunately, we can Loading Loading @@ -930,6 +942,17 @@ static void reset_ctrl_regs(unsigned int cpu) int i, raw_num_brps, err = 0; u32 val; /* * Bail out without clearing the breakpoint registers if halting * debug mode or monitor debug mode is enabled. Checking for monitor * debug mode here ensures we don't clear the breakpoint registers * across power collapse if save and restore code has already * preserved the debug register values or they weren't lost and * monitor mode was already enabled earlier. */ if (halting_mode_enabled() || monitor_mode_enabled()) return; /* * v7 debug contains save and restore registers so that debug state * can be maintained across low-power modes without leaving the debug Loading Loading
arch/arm/kernel/hw_breakpoint.c +23 −0 Original line number Diff line number Diff line Loading @@ -226,6 +226,18 @@ static int get_num_brps(void) return core_has_mismatch_brps() ? brps - 1 : brps; } /* Determine if halting mode is enabled */ static int halting_mode_enabled(void) { u32 dscr; ARM_DBG_READ(c0, c1, 0, dscr); WARN_ONCE(dscr & ARM_DSCR_HDBGEN, "halting debug mode enabled. Unable to access hardware resources.\n"); return !!(dscr & ARM_DSCR_HDBGEN); } /* * In order to access the breakpoint/watchpoint control registers, * we must be running in debug monitor mode. Unfortunately, we can Loading Loading @@ -930,6 +942,17 @@ static void reset_ctrl_regs(unsigned int cpu) int i, raw_num_brps, err = 0; u32 val; /* * Bail out without clearing the breakpoint registers if halting * debug mode or monitor debug mode is enabled. Checking for monitor * debug mode here ensures we don't clear the breakpoint registers * across power collapse if save and restore code has already * preserved the debug register values or they weren't lost and * monitor mode was already enabled earlier. */ if (halting_mode_enabled() || monitor_mode_enabled()) return; /* * v7 debug contains save and restore registers so that debug state * can be maintained across low-power modes without leaving the debug Loading