Loading drivers/clk/qcom/clk-rcg2.c +6 −6 Original line number Diff line number Diff line Loading @@ -151,9 +151,6 @@ static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index) regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + rcg->cfg_off + CFG_REG, &old_cfg); if (rcg->flags & DFS_ENABLE_RCG) return 0; ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + rcg->cfg_off + CFG_REG, CFG_SRC_SEL_MASK, cfg); if (ret) Loading Loading @@ -387,8 +384,9 @@ static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) struct clk_hw *hw = &rcg->clkr.hw; int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src); /* Skip configuration if DFS control has been enabled for the RCG. */ if (rcg->flags & DFS_ENABLE_RCG) return -EPERM; return 0; if (index < 0) return index; Loading Loading @@ -537,7 +535,7 @@ static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate, } ret = clk_rcg2_configure(rcg, f); if (ret && ret != -EPERM) if (ret) return ret; if (rcg->flags & FORCE_ENABLE_RCG) { Loading Loading @@ -1442,7 +1440,9 @@ int clk_rcg2_get_dfs_clock_rate(struct clk_rcg2 *clk, struct device *dev, "RCG flags %x\n", i, dfs_freq_tbl[i].freq, dfs_freq_tbl[i].src, dfs_freq_tbl[i].pre_div, dfs_freq_tbl[i].m, dfs_freq_tbl[i].n, rcg_flags); /* Skip the safe configuration if DFS has been enabled for the RCG. */ if (clk->enable_safe_config) clk->enable_safe_config = false; clk->flags |= rcg_flags; clk->freq_tbl = dfs_freq_tbl; err: Loading Loading
drivers/clk/qcom/clk-rcg2.c +6 −6 Original line number Diff line number Diff line Loading @@ -151,9 +151,6 @@ static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index) regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + rcg->cfg_off + CFG_REG, &old_cfg); if (rcg->flags & DFS_ENABLE_RCG) return 0; ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + rcg->cfg_off + CFG_REG, CFG_SRC_SEL_MASK, cfg); if (ret) Loading Loading @@ -387,8 +384,9 @@ static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) struct clk_hw *hw = &rcg->clkr.hw; int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src); /* Skip configuration if DFS control has been enabled for the RCG. */ if (rcg->flags & DFS_ENABLE_RCG) return -EPERM; return 0; if (index < 0) return index; Loading Loading @@ -537,7 +535,7 @@ static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate, } ret = clk_rcg2_configure(rcg, f); if (ret && ret != -EPERM) if (ret) return ret; if (rcg->flags & FORCE_ENABLE_RCG) { Loading Loading @@ -1442,7 +1440,9 @@ int clk_rcg2_get_dfs_clock_rate(struct clk_rcg2 *clk, struct device *dev, "RCG flags %x\n", i, dfs_freq_tbl[i].freq, dfs_freq_tbl[i].src, dfs_freq_tbl[i].pre_div, dfs_freq_tbl[i].m, dfs_freq_tbl[i].n, rcg_flags); /* Skip the safe configuration if DFS has been enabled for the RCG. */ if (clk->enable_safe_config) clk->enable_safe_config = false; clk->flags |= rcg_flags; clk->freq_tbl = dfs_freq_tbl; err: Loading